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/drivers/gpu/drm/radeon/evergreen_cs.c

https://gitlab.com/tbwtiot/kernel_source
C | 3514 lines | 3157 code | 168 blank | 189 comment | 421 complexity | 0ccf203e8bc0538e0da0bcd10c886abd MD5 | raw file

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   1/*
   2 * Copyright 2010 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 * Copyright 2009 Jerome Glisse.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 *          Jerome Glisse
  27 */
  28#include <drm/drmP.h>
  29#include "radeon.h"
  30#include "evergreend.h"
  31#include "evergreen_reg_safe.h"
  32#include "cayman_reg_safe.h"
  33
  34#define MAX(a,b)                   (((a)>(b))?(a):(b))
  35#define MIN(a,b)                   (((a)<(b))?(a):(b))
  36
  37int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
  38			   struct radeon_cs_reloc **cs_reloc);
  39struct evergreen_cs_track {
  40	u32			group_size;
  41	u32			nbanks;
  42	u32			npipes;
  43	u32			row_size;
  44	/* value we track */
  45	u32			nsamples;		/* unused */
  46	struct radeon_bo	*cb_color_bo[12];
  47	u32			cb_color_bo_offset[12];
  48	struct radeon_bo	*cb_color_fmask_bo[8];	/* unused */
  49	struct radeon_bo	*cb_color_cmask_bo[8];	/* unused */
  50	u32			cb_color_info[12];
  51	u32			cb_color_view[12];
  52	u32			cb_color_pitch[12];
  53	u32			cb_color_slice[12];
  54	u32			cb_color_slice_idx[12];
  55	u32			cb_color_attrib[12];
  56	u32			cb_color_cmask_slice[8];/* unused */
  57	u32			cb_color_fmask_slice[8];/* unused */
  58	u32			cb_target_mask;
  59	u32			cb_shader_mask; /* unused */
  60	u32			vgt_strmout_config;
  61	u32			vgt_strmout_buffer_config;
  62	struct radeon_bo	*vgt_strmout_bo[4];
  63	u32			vgt_strmout_bo_offset[4];
  64	u32			vgt_strmout_size[4];
  65	u32			db_depth_control;
  66	u32			db_depth_view;
  67	u32			db_depth_slice;
  68	u32			db_depth_size;
  69	u32			db_z_info;
  70	u32			db_z_read_offset;
  71	u32			db_z_write_offset;
  72	struct radeon_bo	*db_z_read_bo;
  73	struct radeon_bo	*db_z_write_bo;
  74	u32			db_s_info;
  75	u32			db_s_read_offset;
  76	u32			db_s_write_offset;
  77	struct radeon_bo	*db_s_read_bo;
  78	struct radeon_bo	*db_s_write_bo;
  79	bool			sx_misc_kill_all_prims;
  80	bool			cb_dirty;
  81	bool			db_dirty;
  82	bool			streamout_dirty;
  83	u32			htile_offset;
  84	u32			htile_surface;
  85	struct radeon_bo	*htile_bo;
  86};
  87
  88static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
  89{
  90	if (tiling_flags & RADEON_TILING_MACRO)
  91		return ARRAY_2D_TILED_THIN1;
  92	else if (tiling_flags & RADEON_TILING_MICRO)
  93		return ARRAY_1D_TILED_THIN1;
  94	else
  95		return ARRAY_LINEAR_GENERAL;
  96}
  97
  98static u32 evergreen_cs_get_num_banks(u32 nbanks)
  99{
 100	switch (nbanks) {
 101	case 2:
 102		return ADDR_SURF_2_BANK;
 103	case 4:
 104		return ADDR_SURF_4_BANK;
 105	case 8:
 106	default:
 107		return ADDR_SURF_8_BANK;
 108	case 16:
 109		return ADDR_SURF_16_BANK;
 110	}
 111}
 112
 113static void evergreen_cs_track_init(struct evergreen_cs_track *track)
 114{
 115	int i;
 116
 117	for (i = 0; i < 8; i++) {
 118		track->cb_color_fmask_bo[i] = NULL;
 119		track->cb_color_cmask_bo[i] = NULL;
 120		track->cb_color_cmask_slice[i] = 0;
 121		track->cb_color_fmask_slice[i] = 0;
 122	}
 123
 124	for (i = 0; i < 12; i++) {
 125		track->cb_color_bo[i] = NULL;
 126		track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 127		track->cb_color_info[i] = 0;
 128		track->cb_color_view[i] = 0xFFFFFFFF;
 129		track->cb_color_pitch[i] = 0;
 130		track->cb_color_slice[i] = 0xfffffff;
 131		track->cb_color_slice_idx[i] = 0;
 132	}
 133	track->cb_target_mask = 0xFFFFFFFF;
 134	track->cb_shader_mask = 0xFFFFFFFF;
 135	track->cb_dirty = true;
 136
 137	track->db_depth_slice = 0xffffffff;
 138	track->db_depth_view = 0xFFFFC000;
 139	track->db_depth_size = 0xFFFFFFFF;
 140	track->db_depth_control = 0xFFFFFFFF;
 141	track->db_z_info = 0xFFFFFFFF;
 142	track->db_z_read_offset = 0xFFFFFFFF;
 143	track->db_z_write_offset = 0xFFFFFFFF;
 144	track->db_z_read_bo = NULL;
 145	track->db_z_write_bo = NULL;
 146	track->db_s_info = 0xFFFFFFFF;
 147	track->db_s_read_offset = 0xFFFFFFFF;
 148	track->db_s_write_offset = 0xFFFFFFFF;
 149	track->db_s_read_bo = NULL;
 150	track->db_s_write_bo = NULL;
 151	track->db_dirty = true;
 152	track->htile_bo = NULL;
 153	track->htile_offset = 0xFFFFFFFF;
 154	track->htile_surface = 0;
 155
 156	for (i = 0; i < 4; i++) {
 157		track->vgt_strmout_size[i] = 0;
 158		track->vgt_strmout_bo[i] = NULL;
 159		track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
 160	}
 161	track->streamout_dirty = true;
 162	track->sx_misc_kill_all_prims = false;
 163}
 164
 165struct eg_surface {
 166	/* value gathered from cs */
 167	unsigned	nbx;
 168	unsigned	nby;
 169	unsigned	format;
 170	unsigned	mode;
 171	unsigned	nbanks;
 172	unsigned	bankw;
 173	unsigned	bankh;
 174	unsigned	tsplit;
 175	unsigned	mtilea;
 176	unsigned	nsamples;
 177	/* output value */
 178	unsigned	bpe;
 179	unsigned	layer_size;
 180	unsigned	palign;
 181	unsigned	halign;
 182	unsigned long	base_align;
 183};
 184
 185static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
 186					  struct eg_surface *surf,
 187					  const char *prefix)
 188{
 189	surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
 190	surf->base_align = surf->bpe;
 191	surf->palign = 1;
 192	surf->halign = 1;
 193	return 0;
 194}
 195
 196static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
 197						  struct eg_surface *surf,
 198						  const char *prefix)
 199{
 200	struct evergreen_cs_track *track = p->track;
 201	unsigned palign;
 202
 203	palign = MAX(64, track->group_size / surf->bpe);
 204	surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
 205	surf->base_align = track->group_size;
 206	surf->palign = palign;
 207	surf->halign = 1;
 208	if (surf->nbx & (palign - 1)) {
 209		if (prefix) {
 210			dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
 211				 __func__, __LINE__, prefix, surf->nbx, palign);
 212		}
 213		return -EINVAL;
 214	}
 215	return 0;
 216}
 217
 218static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
 219				      struct eg_surface *surf,
 220				      const char *prefix)
 221{
 222	struct evergreen_cs_track *track = p->track;
 223	unsigned palign;
 224
 225	palign = track->group_size / (8 * surf->bpe * surf->nsamples);
 226	palign = MAX(8, palign);
 227	surf->layer_size = surf->nbx * surf->nby * surf->bpe;
 228	surf->base_align = track->group_size;
 229	surf->palign = palign;
 230	surf->halign = 8;
 231	if ((surf->nbx & (palign - 1))) {
 232		if (prefix) {
 233			dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
 234				 __func__, __LINE__, prefix, surf->nbx, palign,
 235				 track->group_size, surf->bpe, surf->nsamples);
 236		}
 237		return -EINVAL;
 238	}
 239	if ((surf->nby & (8 - 1))) {
 240		if (prefix) {
 241			dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
 242				 __func__, __LINE__, prefix, surf->nby);
 243		}
 244		return -EINVAL;
 245	}
 246	return 0;
 247}
 248
 249static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
 250				      struct eg_surface *surf,
 251				      const char *prefix)
 252{
 253	struct evergreen_cs_track *track = p->track;
 254	unsigned palign, halign, tileb, slice_pt;
 255	unsigned mtile_pr, mtile_ps, mtileb;
 256
 257	tileb = 64 * surf->bpe * surf->nsamples;
 258	slice_pt = 1;
 259	if (tileb > surf->tsplit) {
 260		slice_pt = tileb / surf->tsplit;
 261	}
 262	tileb = tileb / slice_pt;
 263	/* macro tile width & height */
 264	palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
 265	halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
 266	mtileb = (palign / 8) * (halign / 8) * tileb;
 267	mtile_pr = surf->nbx / palign;
 268	mtile_ps = (mtile_pr * surf->nby) / halign;
 269	surf->layer_size = mtile_ps * mtileb * slice_pt;
 270	surf->base_align = (palign / 8) * (halign / 8) * tileb;
 271	surf->palign = palign;
 272	surf->halign = halign;
 273
 274	if ((surf->nbx & (palign - 1))) {
 275		if (prefix) {
 276			dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
 277				 __func__, __LINE__, prefix, surf->nbx, palign);
 278		}
 279		return -EINVAL;
 280	}
 281	if ((surf->nby & (halign - 1))) {
 282		if (prefix) {
 283			dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
 284				 __func__, __LINE__, prefix, surf->nby, halign);
 285		}
 286		return -EINVAL;
 287	}
 288
 289	return 0;
 290}
 291
 292static int evergreen_surface_check(struct radeon_cs_parser *p,
 293				   struct eg_surface *surf,
 294				   const char *prefix)
 295{
 296	/* some common value computed here */
 297	surf->bpe = r600_fmt_get_blocksize(surf->format);
 298
 299	switch (surf->mode) {
 300	case ARRAY_LINEAR_GENERAL:
 301		return evergreen_surface_check_linear(p, surf, prefix);
 302	case ARRAY_LINEAR_ALIGNED:
 303		return evergreen_surface_check_linear_aligned(p, surf, prefix);
 304	case ARRAY_1D_TILED_THIN1:
 305		return evergreen_surface_check_1d(p, surf, prefix);
 306	case ARRAY_2D_TILED_THIN1:
 307		return evergreen_surface_check_2d(p, surf, prefix);
 308	default:
 309		dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
 310				__func__, __LINE__, prefix, surf->mode);
 311		return -EINVAL;
 312	}
 313	return -EINVAL;
 314}
 315
 316static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
 317					      struct eg_surface *surf,
 318					      const char *prefix)
 319{
 320	switch (surf->mode) {
 321	case ARRAY_2D_TILED_THIN1:
 322		break;
 323	case ARRAY_LINEAR_GENERAL:
 324	case ARRAY_LINEAR_ALIGNED:
 325	case ARRAY_1D_TILED_THIN1:
 326		return 0;
 327	default:
 328		dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
 329				__func__, __LINE__, prefix, surf->mode);
 330		return -EINVAL;
 331	}
 332
 333	switch (surf->nbanks) {
 334	case 0: surf->nbanks = 2; break;
 335	case 1: surf->nbanks = 4; break;
 336	case 2: surf->nbanks = 8; break;
 337	case 3: surf->nbanks = 16; break;
 338	default:
 339		dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
 340			 __func__, __LINE__, prefix, surf->nbanks);
 341		return -EINVAL;
 342	}
 343	switch (surf->bankw) {
 344	case 0: surf->bankw = 1; break;
 345	case 1: surf->bankw = 2; break;
 346	case 2: surf->bankw = 4; break;
 347	case 3: surf->bankw = 8; break;
 348	default:
 349		dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
 350			 __func__, __LINE__, prefix, surf->bankw);
 351		return -EINVAL;
 352	}
 353	switch (surf->bankh) {
 354	case 0: surf->bankh = 1; break;
 355	case 1: surf->bankh = 2; break;
 356	case 2: surf->bankh = 4; break;
 357	case 3: surf->bankh = 8; break;
 358	default:
 359		dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
 360			 __func__, __LINE__, prefix, surf->bankh);
 361		return -EINVAL;
 362	}
 363	switch (surf->mtilea) {
 364	case 0: surf->mtilea = 1; break;
 365	case 1: surf->mtilea = 2; break;
 366	case 2: surf->mtilea = 4; break;
 367	case 3: surf->mtilea = 8; break;
 368	default:
 369		dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
 370			 __func__, __LINE__, prefix, surf->mtilea);
 371		return -EINVAL;
 372	}
 373	switch (surf->tsplit) {
 374	case 0: surf->tsplit = 64; break;
 375	case 1: surf->tsplit = 128; break;
 376	case 2: surf->tsplit = 256; break;
 377	case 3: surf->tsplit = 512; break;
 378	case 4: surf->tsplit = 1024; break;
 379	case 5: surf->tsplit = 2048; break;
 380	case 6: surf->tsplit = 4096; break;
 381	default:
 382		dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
 383			 __func__, __LINE__, prefix, surf->tsplit);
 384		return -EINVAL;
 385	}
 386	return 0;
 387}
 388
 389static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
 390{
 391	struct evergreen_cs_track *track = p->track;
 392	struct eg_surface surf;
 393	unsigned pitch, slice, mslice;
 394	unsigned long offset;
 395	int r;
 396
 397	mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
 398	pitch = track->cb_color_pitch[id];
 399	slice = track->cb_color_slice[id];
 400	surf.nbx = (pitch + 1) * 8;
 401	surf.nby = ((slice + 1) * 64) / surf.nbx;
 402	surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
 403	surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
 404	surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
 405	surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
 406	surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
 407	surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
 408	surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
 409	surf.nsamples = 1;
 410
 411	if (!r600_fmt_is_valid_color(surf.format)) {
 412		dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
 413			 __func__, __LINE__, surf.format,
 414			id, track->cb_color_info[id]);
 415		return -EINVAL;
 416	}
 417
 418	r = evergreen_surface_value_conv_check(p, &surf, "cb");
 419	if (r) {
 420		return r;
 421	}
 422
 423	r = evergreen_surface_check(p, &surf, "cb");
 424	if (r) {
 425		dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 426			 __func__, __LINE__, id, track->cb_color_pitch[id],
 427			 track->cb_color_slice[id], track->cb_color_attrib[id],
 428			 track->cb_color_info[id]);
 429		return r;
 430	}
 431
 432	offset = track->cb_color_bo_offset[id] << 8;
 433	if (offset & (surf.base_align - 1)) {
 434		dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
 435			 __func__, __LINE__, id, offset, surf.base_align);
 436		return -EINVAL;
 437	}
 438
 439	offset += surf.layer_size * mslice;
 440	if (offset > radeon_bo_size(track->cb_color_bo[id])) {
 441		/* old ddx are broken they allocate bo with w*h*bpp but
 442		 * program slice with ALIGN(h, 8), catch this and patch
 443		 * command stream.
 444		 */
 445		if (!surf.mode) {
 446			volatile u32 *ib = p->ib.ptr;
 447			unsigned long tmp, nby, bsize, size, min = 0;
 448
 449			/* find the height the ddx wants */
 450			if (surf.nby > 8) {
 451				min = surf.nby - 8;
 452			}
 453			bsize = radeon_bo_size(track->cb_color_bo[id]);
 454			tmp = track->cb_color_bo_offset[id] << 8;
 455			for (nby = surf.nby; nby > min; nby--) {
 456				size = nby * surf.nbx * surf.bpe * surf.nsamples;
 457				if ((tmp + size * mslice) <= bsize) {
 458					break;
 459				}
 460			}
 461			if (nby > min) {
 462				surf.nby = nby;
 463				slice = ((nby * surf.nbx) / 64) - 1;
 464				if (!evergreen_surface_check(p, &surf, "cb")) {
 465					/* check if this one works */
 466					tmp += surf.layer_size * mslice;
 467					if (tmp <= bsize) {
 468						ib[track->cb_color_slice_idx[id]] = slice;
 469						goto old_ddx_ok;
 470					}
 471				}
 472			}
 473		}
 474		dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
 475			 "offset %d, max layer %d, bo size %ld, slice %d)\n",
 476			 __func__, __LINE__, id, surf.layer_size,
 477			track->cb_color_bo_offset[id] << 8, mslice,
 478			radeon_bo_size(track->cb_color_bo[id]), slice);
 479		dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
 480			 __func__, __LINE__, surf.nbx, surf.nby,
 481			surf.mode, surf.bpe, surf.nsamples,
 482			surf.bankw, surf.bankh,
 483			surf.tsplit, surf.mtilea);
 484		return -EINVAL;
 485	}
 486old_ddx_ok:
 487
 488	return 0;
 489}
 490
 491static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
 492						unsigned nbx, unsigned nby)
 493{
 494	struct evergreen_cs_track *track = p->track;
 495	unsigned long size;
 496
 497	if (track->htile_bo == NULL) {
 498		dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
 499				__func__, __LINE__, track->db_z_info);
 500		return -EINVAL;
 501	}
 502
 503	if (G_028ABC_LINEAR(track->htile_surface)) {
 504		/* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
 505		nbx = round_up(nbx, 16 * 8);
 506		/* height is npipes htiles aligned == npipes * 8 pixel aligned */
 507		nby = round_up(nby, track->npipes * 8);
 508	} else {
 509		/* always assume 8x8 htile */
 510		/* align is htile align * 8, htile align vary according to
 511		 * number of pipe and tile width and nby
 512		 */
 513		switch (track->npipes) {
 514		case 8:
 515			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 516			nbx = round_up(nbx, 64 * 8);
 517			nby = round_up(nby, 64 * 8);
 518			break;
 519		case 4:
 520			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 521			nbx = round_up(nbx, 64 * 8);
 522			nby = round_up(nby, 32 * 8);
 523			break;
 524		case 2:
 525			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 526			nbx = round_up(nbx, 32 * 8);
 527			nby = round_up(nby, 32 * 8);
 528			break;
 529		case 1:
 530			/* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 531			nbx = round_up(nbx, 32 * 8);
 532			nby = round_up(nby, 16 * 8);
 533			break;
 534		default:
 535			dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
 536					__func__, __LINE__, track->npipes);
 537			return -EINVAL;
 538		}
 539	}
 540	/* compute number of htile */
 541	nbx = nbx >> 3;
 542	nby = nby >> 3;
 543	/* size must be aligned on npipes * 2K boundary */
 544	size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
 545	size += track->htile_offset;
 546
 547	if (size > radeon_bo_size(track->htile_bo)) {
 548		dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
 549				__func__, __LINE__, radeon_bo_size(track->htile_bo),
 550				size, nbx, nby);
 551		return -EINVAL;
 552	}
 553	return 0;
 554}
 555
 556static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
 557{
 558	struct evergreen_cs_track *track = p->track;
 559	struct eg_surface surf;
 560	unsigned pitch, slice, mslice;
 561	unsigned long offset;
 562	int r;
 563
 564	mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
 565	pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
 566	slice = track->db_depth_slice;
 567	surf.nbx = (pitch + 1) * 8;
 568	surf.nby = ((slice + 1) * 64) / surf.nbx;
 569	surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
 570	surf.format = G_028044_FORMAT(track->db_s_info);
 571	surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
 572	surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
 573	surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
 574	surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
 575	surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
 576	surf.nsamples = 1;
 577
 578	if (surf.format != 1) {
 579		dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
 580			 __func__, __LINE__, surf.format);
 581		return -EINVAL;
 582	}
 583	/* replace by color format so we can use same code */
 584	surf.format = V_028C70_COLOR_8;
 585
 586	r = evergreen_surface_value_conv_check(p, &surf, "stencil");
 587	if (r) {
 588		return r;
 589	}
 590
 591	r = evergreen_surface_check(p, &surf, NULL);
 592	if (r) {
 593		/* old userspace doesn't compute proper depth/stencil alignment
 594		 * check that alignment against a bigger byte per elements and
 595		 * only report if that alignment is wrong too.
 596		 */
 597		surf.format = V_028C70_COLOR_8_8_8_8;
 598		r = evergreen_surface_check(p, &surf, "stencil");
 599		if (r) {
 600			dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 601				 __func__, __LINE__, track->db_depth_size,
 602				 track->db_depth_slice, track->db_s_info, track->db_z_info);
 603		}
 604		return r;
 605	}
 606
 607	offset = track->db_s_read_offset << 8;
 608	if (offset & (surf.base_align - 1)) {
 609		dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
 610			 __func__, __LINE__, offset, surf.base_align);
 611		return -EINVAL;
 612	}
 613	offset += surf.layer_size * mslice;
 614	if (offset > radeon_bo_size(track->db_s_read_bo)) {
 615		dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
 616			 "offset %ld, max layer %d, bo size %ld)\n",
 617			 __func__, __LINE__, surf.layer_size,
 618			(unsigned long)track->db_s_read_offset << 8, mslice,
 619			radeon_bo_size(track->db_s_read_bo));
 620		dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 621			 __func__, __LINE__, track->db_depth_size,
 622			 track->db_depth_slice, track->db_s_info, track->db_z_info);
 623		return -EINVAL;
 624	}
 625
 626	offset = track->db_s_write_offset << 8;
 627	if (offset & (surf.base_align - 1)) {
 628		dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
 629			 __func__, __LINE__, offset, surf.base_align);
 630		return -EINVAL;
 631	}
 632	offset += surf.layer_size * mslice;
 633	if (offset > radeon_bo_size(track->db_s_write_bo)) {
 634		dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
 635			 "offset %ld, max layer %d, bo size %ld)\n",
 636			 __func__, __LINE__, surf.layer_size,
 637			(unsigned long)track->db_s_write_offset << 8, mslice,
 638			radeon_bo_size(track->db_s_write_bo));
 639		return -EINVAL;
 640	}
 641
 642	/* hyperz */
 643	if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
 644		r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
 645		if (r) {
 646			return r;
 647		}
 648	}
 649
 650	return 0;
 651}
 652
 653static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
 654{
 655	struct evergreen_cs_track *track = p->track;
 656	struct eg_surface surf;
 657	unsigned pitch, slice, mslice;
 658	unsigned long offset;
 659	int r;
 660
 661	mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
 662	pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
 663	slice = track->db_depth_slice;
 664	surf.nbx = (pitch + 1) * 8;
 665	surf.nby = ((slice + 1) * 64) / surf.nbx;
 666	surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
 667	surf.format = G_028040_FORMAT(track->db_z_info);
 668	surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
 669	surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
 670	surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
 671	surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
 672	surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
 673	surf.nsamples = 1;
 674
 675	switch (surf.format) {
 676	case V_028040_Z_16:
 677		surf.format = V_028C70_COLOR_16;
 678		break;
 679	case V_028040_Z_24:
 680	case V_028040_Z_32_FLOAT:
 681		surf.format = V_028C70_COLOR_8_8_8_8;
 682		break;
 683	default:
 684		dev_warn(p->dev, "%s:%d depth invalid format %d\n",
 685			 __func__, __LINE__, surf.format);
 686		return -EINVAL;
 687	}
 688
 689	r = evergreen_surface_value_conv_check(p, &surf, "depth");
 690	if (r) {
 691		dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
 692			 __func__, __LINE__, track->db_depth_size,
 693			 track->db_depth_slice, track->db_z_info);
 694		return r;
 695	}
 696
 697	r = evergreen_surface_check(p, &surf, "depth");
 698	if (r) {
 699		dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
 700			 __func__, __LINE__, track->db_depth_size,
 701			 track->db_depth_slice, track->db_z_info);
 702		return r;
 703	}
 704
 705	offset = track->db_z_read_offset << 8;
 706	if (offset & (surf.base_align - 1)) {
 707		dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
 708			 __func__, __LINE__, offset, surf.base_align);
 709		return -EINVAL;
 710	}
 711	offset += surf.layer_size * mslice;
 712	if (offset > radeon_bo_size(track->db_z_read_bo)) {
 713		dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
 714			 "offset %ld, max layer %d, bo size %ld)\n",
 715			 __func__, __LINE__, surf.layer_size,
 716			(unsigned long)track->db_z_read_offset << 8, mslice,
 717			radeon_bo_size(track->db_z_read_bo));
 718		return -EINVAL;
 719	}
 720
 721	offset = track->db_z_write_offset << 8;
 722	if (offset & (surf.base_align - 1)) {
 723		dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
 724			 __func__, __LINE__, offset, surf.base_align);
 725		return -EINVAL;
 726	}
 727	offset += surf.layer_size * mslice;
 728	if (offset > radeon_bo_size(track->db_z_write_bo)) {
 729		dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
 730			 "offset %ld, max layer %d, bo size %ld)\n",
 731			 __func__, __LINE__, surf.layer_size,
 732			(unsigned long)track->db_z_write_offset << 8, mslice,
 733			radeon_bo_size(track->db_z_write_bo));
 734		return -EINVAL;
 735	}
 736
 737	/* hyperz */
 738	if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
 739		r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
 740		if (r) {
 741			return r;
 742		}
 743	}
 744
 745	return 0;
 746}
 747
 748static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
 749					       struct radeon_bo *texture,
 750					       struct radeon_bo *mipmap,
 751					       unsigned idx)
 752{
 753	struct eg_surface surf;
 754	unsigned long toffset, moffset;
 755	unsigned dim, llevel, mslice, width, height, depth, i;
 756	u32 texdw[8];
 757	int r;
 758
 759	texdw[0] = radeon_get_ib_value(p, idx + 0);
 760	texdw[1] = radeon_get_ib_value(p, idx + 1);
 761	texdw[2] = radeon_get_ib_value(p, idx + 2);
 762	texdw[3] = radeon_get_ib_value(p, idx + 3);
 763	texdw[4] = radeon_get_ib_value(p, idx + 4);
 764	texdw[5] = radeon_get_ib_value(p, idx + 5);
 765	texdw[6] = radeon_get_ib_value(p, idx + 6);
 766	texdw[7] = radeon_get_ib_value(p, idx + 7);
 767	dim = G_030000_DIM(texdw[0]);
 768	llevel = G_030014_LAST_LEVEL(texdw[5]);
 769	mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
 770	width = G_030000_TEX_WIDTH(texdw[0]) + 1;
 771	height =  G_030004_TEX_HEIGHT(texdw[1]) + 1;
 772	depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
 773	surf.format = G_03001C_DATA_FORMAT(texdw[7]);
 774	surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
 775	surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
 776	surf.nby = r600_fmt_get_nblocksy(surf.format, height);
 777	surf.mode = G_030004_ARRAY_MODE(texdw[1]);
 778	surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
 779	surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
 780	surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
 781	surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
 782	surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
 783	surf.nsamples = 1;
 784	toffset = texdw[2] << 8;
 785	moffset = texdw[3] << 8;
 786
 787	if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
 788		dev_warn(p->dev, "%s:%d texture invalid format %d\n",
 789			 __func__, __LINE__, surf.format);
 790		return -EINVAL;
 791	}
 792	switch (dim) {
 793	case V_030000_SQ_TEX_DIM_1D:
 794	case V_030000_SQ_TEX_DIM_2D:
 795	case V_030000_SQ_TEX_DIM_CUBEMAP:
 796	case V_030000_SQ_TEX_DIM_1D_ARRAY:
 797	case V_030000_SQ_TEX_DIM_2D_ARRAY:
 798		depth = 1;
 799		break;
 800	case V_030000_SQ_TEX_DIM_2D_MSAA:
 801	case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
 802		surf.nsamples = 1 << llevel;
 803		llevel = 0;
 804		depth = 1;
 805		break;
 806	case V_030000_SQ_TEX_DIM_3D:
 807		break;
 808	default:
 809		dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
 810			 __func__, __LINE__, dim);
 811		return -EINVAL;
 812	}
 813
 814	r = evergreen_surface_value_conv_check(p, &surf, "texture");
 815	if (r) {
 816		return r;
 817	}
 818
 819	/* align height */
 820	evergreen_surface_check(p, &surf, NULL);
 821	surf.nby = ALIGN(surf.nby, surf.halign);
 822
 823	r = evergreen_surface_check(p, &surf, "texture");
 824	if (r) {
 825		dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 826			 __func__, __LINE__, texdw[0], texdw[1], texdw[4],
 827			 texdw[5], texdw[6], texdw[7]);
 828		return r;
 829	}
 830
 831	/* check texture size */
 832	if (toffset & (surf.base_align - 1)) {
 833		dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
 834			 __func__, __LINE__, toffset, surf.base_align);
 835		return -EINVAL;
 836	}
 837	if (surf.nsamples <= 1 && moffset & (surf.base_align - 1)) {
 838		dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
 839			 __func__, __LINE__, moffset, surf.base_align);
 840		return -EINVAL;
 841	}
 842	if (dim == SQ_TEX_DIM_3D) {
 843		toffset += surf.layer_size * depth;
 844	} else {
 845		toffset += surf.layer_size * mslice;
 846	}
 847	if (toffset > radeon_bo_size(texture)) {
 848		dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
 849			 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
 850			 __func__, __LINE__, surf.layer_size,
 851			(unsigned long)texdw[2] << 8, mslice,
 852			depth, radeon_bo_size(texture),
 853			surf.nbx, surf.nby);
 854		return -EINVAL;
 855	}
 856
 857	if (!mipmap) {
 858		if (llevel) {
 859			dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n",
 860				 __func__, __LINE__);
 861			return -EINVAL;
 862		} else {
 863			return 0; /* everything's ok */
 864		}
 865	}
 866
 867	/* check mipmap size */
 868	for (i = 1; i <= llevel; i++) {
 869		unsigned w, h, d;
 870
 871		w = r600_mip_minify(width, i);
 872		h = r600_mip_minify(height, i);
 873		d = r600_mip_minify(depth, i);
 874		surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
 875		surf.nby = r600_fmt_get_nblocksy(surf.format, h);
 876
 877		switch (surf.mode) {
 878		case ARRAY_2D_TILED_THIN1:
 879			if (surf.nbx < surf.palign || surf.nby < surf.halign) {
 880				surf.mode = ARRAY_1D_TILED_THIN1;
 881			}
 882			/* recompute alignment */
 883			evergreen_surface_check(p, &surf, NULL);
 884			break;
 885		case ARRAY_LINEAR_GENERAL:
 886		case ARRAY_LINEAR_ALIGNED:
 887		case ARRAY_1D_TILED_THIN1:
 888			break;
 889		default:
 890			dev_warn(p->dev, "%s:%d invalid array mode %d\n",
 891				 __func__, __LINE__, surf.mode);
 892			return -EINVAL;
 893		}
 894		surf.nbx = ALIGN(surf.nbx, surf.palign);
 895		surf.nby = ALIGN(surf.nby, surf.halign);
 896
 897		r = evergreen_surface_check(p, &surf, "mipmap");
 898		if (r) {
 899			return r;
 900		}
 901
 902		if (dim == SQ_TEX_DIM_3D) {
 903			moffset += surf.layer_size * d;
 904		} else {
 905			moffset += surf.layer_size * mslice;
 906		}
 907		if (moffset > radeon_bo_size(mipmap)) {
 908			dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
 909					"offset %ld, coffset %ld, max layer %d, depth %d, "
 910					"bo size %ld) level0 (%d %d %d)\n",
 911					__func__, __LINE__, i, surf.layer_size,
 912					(unsigned long)texdw[3] << 8, moffset, mslice,
 913					d, radeon_bo_size(mipmap),
 914					width, height, depth);
 915			dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
 916				 __func__, __LINE__, surf.nbx, surf.nby,
 917				surf.mode, surf.bpe, surf.nsamples,
 918				surf.bankw, surf.bankh,
 919				surf.tsplit, surf.mtilea);
 920			return -EINVAL;
 921		}
 922	}
 923
 924	return 0;
 925}
 926
 927static int evergreen_cs_track_check(struct radeon_cs_parser *p)
 928{
 929	struct evergreen_cs_track *track = p->track;
 930	unsigned tmp, i;
 931	int r;
 932	unsigned buffer_mask = 0;
 933
 934	/* check streamout */
 935	if (track->streamout_dirty && track->vgt_strmout_config) {
 936		for (i = 0; i < 4; i++) {
 937			if (track->vgt_strmout_config & (1 << i)) {
 938				buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
 939			}
 940		}
 941
 942		for (i = 0; i < 4; i++) {
 943			if (buffer_mask & (1 << i)) {
 944				if (track->vgt_strmout_bo[i]) {
 945					u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
 946							(u64)track->vgt_strmout_size[i];
 947					if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
 948						DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
 949							  i, offset,
 950							  radeon_bo_size(track->vgt_strmout_bo[i]));
 951						return -EINVAL;
 952					}
 953				} else {
 954					dev_warn(p->dev, "No buffer for streamout %d\n", i);
 955					return -EINVAL;
 956				}
 957			}
 958		}
 959		track->streamout_dirty = false;
 960	}
 961
 962	if (track->sx_misc_kill_all_prims)
 963		return 0;
 964
 965	/* check that we have a cb for each enabled target
 966	 */
 967	if (track->cb_dirty) {
 968		tmp = track->cb_target_mask;
 969		for (i = 0; i < 8; i++) {
 970			if ((tmp >> (i * 4)) & 0xF) {
 971				/* at least one component is enabled */
 972				if (track->cb_color_bo[i] == NULL) {
 973					dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 974						__func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 975					return -EINVAL;
 976				}
 977				/* check cb */
 978				r = evergreen_cs_track_validate_cb(p, i);
 979				if (r) {
 980					return r;
 981				}
 982			}
 983		}
 984		track->cb_dirty = false;
 985	}
 986
 987	if (track->db_dirty) {
 988		/* Check stencil buffer */
 989		if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
 990		    G_028800_STENCIL_ENABLE(track->db_depth_control)) {
 991			r = evergreen_cs_track_validate_stencil(p);
 992			if (r)
 993				return r;
 994		}
 995		/* Check depth buffer */
 996		if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
 997		    G_028800_Z_ENABLE(track->db_depth_control)) {
 998			r = evergreen_cs_track_validate_depth(p);
 999			if (r)
1000				return r;
1001		}
1002		track->db_dirty = false;
1003	}
1004
1005	return 0;
1006}
1007
1008/**
1009 * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet
1010 * @parser:		parser structure holding parsing context.
1011 *
1012 * This is an Evergreen(+)-specific function for parsing VLINE packets.
1013 * Real work is done by r600_cs_common_vline_parse function.
1014 * Here we just set up ASIC-specific register table and call
1015 * the common implementation function.
1016 */
1017static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1018{
1019
1020	static uint32_t vline_start_end[6] = {
1021		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,
1022		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET,
1023		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET,
1024		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET,
1025		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,
1026		EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET
1027	};
1028	static uint32_t vline_status[6] = {
1029		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1030		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1031		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1032		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1033		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1034		EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET
1035	};
1036
1037	return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
1038}
1039
1040static int evergreen_packet0_check(struct radeon_cs_parser *p,
1041				   struct radeon_cs_packet *pkt,
1042				   unsigned idx, unsigned reg)
1043{
1044	int r;
1045
1046	switch (reg) {
1047	case EVERGREEN_VLINE_START_END:
1048		r = evergreen_cs_packet_parse_vline(p);
1049		if (r) {
1050			DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1051					idx, reg);
1052			return r;
1053		}
1054		break;
1055	default:
1056		printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1057		       reg, idx);
1058		return -EINVAL;
1059	}
1060	return 0;
1061}
1062
1063static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1064				      struct radeon_cs_packet *pkt)
1065{
1066	unsigned reg, i;
1067	unsigned idx;
1068	int r;
1069
1070	idx = pkt->idx + 1;
1071	reg = pkt->reg;
1072	for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1073		r = evergreen_packet0_check(p, pkt, idx, reg);
1074		if (r) {
1075			return r;
1076		}
1077	}
1078	return 0;
1079}
1080
1081/**
1082 * evergreen_cs_check_reg() - check if register is authorized or not
1083 * @parser: parser structure holding parsing context
1084 * @reg: register we are testing
1085 * @idx: index into the cs buffer
1086 *
1087 * This function will test against evergreen_reg_safe_bm and return 0
1088 * if register is safe. If register is not flag as safe this function
1089 * will test it against a list of register needind special handling.
1090 */
1091static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1092{
1093	struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1094	struct radeon_cs_reloc *reloc;
1095	u32 last_reg;
1096	u32 m, i, tmp, *ib;
1097	int r;
1098
1099	if (p->rdev->family >= CHIP_CAYMAN)
1100		last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1101	else
1102		last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1103
1104	i = (reg >> 7);
1105	if (i >= last_reg) {
1106		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1107		return -EINVAL;
1108	}
1109	m = 1 << ((reg >> 2) & 31);
1110	if (p->rdev->family >= CHIP_CAYMAN) {
1111		if (!(cayman_reg_safe_bm[i] & m))
1112			return 0;
1113	} else {
1114		if (!(evergreen_reg_safe_bm[i] & m))
1115			return 0;
1116	}
1117	ib = p->ib.ptr;
1118	switch (reg) {
1119	/* force following reg to 0 in an attempt to disable out buffer
1120	 * which will need us to better understand how it works to perform
1121	 * security check on it (Jerome)
1122	 */
1123	case SQ_ESGS_RING_SIZE:
1124	case SQ_GSVS_RING_SIZE:
1125	case SQ_ESTMP_RING_SIZE:
1126	case SQ_GSTMP_RING_SIZE:
1127	case SQ_HSTMP_RING_SIZE:
1128	case SQ_LSTMP_RING_SIZE:
1129	case SQ_PSTMP_RING_SIZE:
1130	case SQ_VSTMP_RING_SIZE:
1131	case SQ_ESGS_RING_ITEMSIZE:
1132	case SQ_ESTMP_RING_ITEMSIZE:
1133	case SQ_GSTMP_RING_ITEMSIZE:
1134	case SQ_GSVS_RING_ITEMSIZE:
1135	case SQ_GS_VERT_ITEMSIZE:
1136	case SQ_GS_VERT_ITEMSIZE_1:
1137	case SQ_GS_VERT_ITEMSIZE_2:
1138	case SQ_GS_VERT_ITEMSIZE_3:
1139	case SQ_GSVS_RING_OFFSET_1:
1140	case SQ_GSVS_RING_OFFSET_2:
1141	case SQ_GSVS_RING_OFFSET_3:
1142	case SQ_HSTMP_RING_ITEMSIZE:
1143	case SQ_LSTMP_RING_ITEMSIZE:
1144	case SQ_PSTMP_RING_ITEMSIZE:
1145	case SQ_VSTMP_RING_ITEMSIZE:
1146	case VGT_TF_RING_SIZE:
1147		/* get value to populate the IB don't remove */
1148		/*tmp =radeon_get_ib_value(p, idx);
1149		  ib[idx] = 0;*/
1150		break;
1151	case SQ_ESGS_RING_BASE:
1152	case SQ_GSVS_RING_BASE:
1153	case SQ_ESTMP_RING_BASE:
1154	case SQ_GSTMP_RING_BASE:
1155	case SQ_HSTMP_RING_BASE:
1156	case SQ_LSTMP_RING_BASE:
1157	case SQ_PSTMP_RING_BASE:
1158	case SQ_VSTMP_RING_BASE:
1159		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1160		if (r) {
1161			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1162					"0x%04X\n", reg);
1163			return -EINVAL;
1164		}
1165		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1166		break;
1167	case DB_DEPTH_CONTROL:
1168		track->db_depth_control = radeon_get_ib_value(p, idx);
1169		track->db_dirty = true;
1170		break;
1171	case CAYMAN_DB_EQAA:
1172		if (p->rdev->family < CHIP_CAYMAN) {
1173			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1174				 "0x%04X\n", reg);
1175			return -EINVAL;
1176		}
1177		break;
1178	case CAYMAN_DB_DEPTH_INFO:
1179		if (p->rdev->family < CHIP_CAYMAN) {
1180			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1181				 "0x%04X\n", reg);
1182			return -EINVAL;
1183		}
1184		break;
1185	case DB_Z_INFO:
1186		track->db_z_info = radeon_get_ib_value(p, idx);
1187		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1188			r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1189			if (r) {
1190				dev_warn(p->dev, "bad SET_CONTEXT_REG "
1191						"0x%04X\n", reg);
1192				return -EINVAL;
1193			}
1194			ib[idx] &= ~Z_ARRAY_MODE(0xf);
1195			track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1196			ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1197			track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1198			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1199				unsigned bankw, bankh, mtaspect, tile_split;
1200
1201				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1202							&bankw, &bankh, &mtaspect,
1203							&tile_split);
1204				ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1205				ib[idx] |= DB_TILE_SPLIT(tile_split) |
1206						DB_BANK_WIDTH(bankw) |
1207						DB_BANK_HEIGHT(bankh) |
1208						DB_MACRO_TILE_ASPECT(mtaspect);
1209			}
1210		}
1211		track->db_dirty = true;
1212		break;
1213	case DB_STENCIL_INFO:
1214		track->db_s_info = radeon_get_ib_value(p, idx);
1215		track->db_dirty = true;
1216		break;
1217	case DB_DEPTH_VIEW:
1218		track->db_depth_view = radeon_get_ib_value(p, idx);
1219		track->db_dirty = true;
1220		break;
1221	case DB_DEPTH_SIZE:
1222		track->db_depth_size = radeon_get_ib_value(p, idx);
1223		track->db_dirty = true;
1224		break;
1225	case R_02805C_DB_DEPTH_SLICE:
1226		track->db_depth_slice = radeon_get_ib_value(p, idx);
1227		track->db_dirty = true;
1228		break;
1229	case DB_Z_READ_BASE:
1230		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1231		if (r) {
1232			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1233					"0x%04X\n", reg);
1234			return -EINVAL;
1235		}
1236		track->db_z_read_offset = radeon_get_ib_value(p, idx);
1237		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1238		track->db_z_read_bo = reloc->robj;
1239		track->db_dirty = true;
1240		break;
1241	case DB_Z_WRITE_BASE:
1242		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1243		if (r) {
1244			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1245					"0x%04X\n", reg);
1246			return -EINVAL;
1247		}
1248		track->db_z_write_offset = radeon_get_ib_value(p, idx);
1249		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1250		track->db_z_write_bo = reloc->robj;
1251		track->db_dirty = true;
1252		break;
1253	case DB_STENCIL_READ_BASE:
1254		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1255		if (r) {
1256			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1257					"0x%04X\n", reg);
1258			return -EINVAL;
1259		}
1260		track->db_s_read_offset = radeon_get_ib_value(p, idx);
1261		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1262		track->db_s_read_bo = reloc->robj;
1263		track->db_dirty = true;
1264		break;
1265	case DB_STENCIL_WRITE_BASE:
1266		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1267		if (r) {
1268			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1269					"0x%04X\n", reg);
1270			return -EINVAL;
1271		}
1272		track->db_s_write_offset = radeon_get_ib_value(p, idx);
1273		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1274		track->db_s_write_bo = reloc->robj;
1275		track->db_dirty = true;
1276		break;
1277	case VGT_STRMOUT_CONFIG:
1278		track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1279		track->streamout_dirty = true;
1280		break;
1281	case VGT_STRMOUT_BUFFER_CONFIG:
1282		track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1283		track->streamout_dirty = true;
1284		break;
1285	case VGT_STRMOUT_BUFFER_BASE_0:
1286	case VGT_STRMOUT_BUFFER_BASE_1:
1287	case VGT_STRMOUT_BUFFER_BASE_2:
1288	case VGT_STRMOUT_BUFFER_BASE_3:
1289		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1290		if (r) {
1291			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1292					"0x%04X\n", reg);
1293			return -EINVAL;
1294		}
1295		tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1296		track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1297		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1298		track->vgt_strmout_bo[tmp] = reloc->robj;
1299		track->streamout_dirty = true;
1300		break;
1301	case VGT_STRMOUT_BUFFER_SIZE_0:
1302	case VGT_STRMOUT_BUFFER_SIZE_1:
1303	case VGT_STRMOUT_BUFFER_SIZE_2:
1304	case VGT_STRMOUT_BUFFER_SIZE_3:
1305		tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1306		/* size in register is DWs, convert to bytes */
1307		track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1308		track->streamout_dirty = true;
1309		break;
1310	case CP_COHER_BASE:
1311		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1312		if (r) {
1313			dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1314					"0x%04X\n", reg);
1315			return -EINVAL;
1316		}
1317		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1318	case CB_TARGET_MASK:
1319		track->cb_target_mask = radeon_get_ib_value(p, idx);
1320		track->cb_dirty = true;
1321		break;
1322	case CB_SHADER_MASK:
1323		track->cb_shader_mask = radeon_get_ib_value(p, idx);
1324		track->cb_dirty = true;
1325		break;
1326	case PA_SC_AA_CONFIG:
1327		if (p->rdev->family >= CHIP_CAYMAN) {
1328			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1329				 "0x%04X\n", reg);
1330			return -EINVAL;
1331		}
1332		tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1333		track->nsamples = 1 << tmp;
1334		break;
1335	case CAYMAN_PA_SC_AA_CONFIG:
1336		if (p->rdev->family < CHIP_CAYMAN) {
1337			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1338				 "0x%04X\n", reg);
1339			return -EINVAL;
1340		}
1341		tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1342		track->nsamples = 1 << tmp;
1343		break;
1344	case CB_COLOR0_VIEW:
1345	case CB_COLOR1_VIEW:
1346	case CB_COLOR2_VIEW:
1347	case CB_COLOR3_VIEW:
1348	case CB_COLOR4_VIEW:
1349	case CB_COLOR5_VIEW:
1350	case CB_COLOR6_VIEW:
1351	case CB_COLOR7_VIEW:
1352		tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1353		track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1354		track->cb_dirty = true;
1355		break;
1356	case CB_COLOR8_VIEW:
1357	case CB_COLOR9_VIEW:
1358	case CB_COLOR10_VIEW:
1359	case CB_COLOR11_VIEW:
1360		tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1361		track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1362		track->cb_dirty = true;
1363		break;
1364	case CB_COLOR0_INFO:
1365	case CB_COLOR1_INFO:
1366	case CB_COLOR2_INFO:
1367	case CB_COLOR3_INFO:
1368	case CB_COLOR4_INFO:
1369	case CB_COLOR5_INFO:
1370	case CB_COLOR6_INFO:
1371	case CB_COLOR7_INFO:
1372		tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1373		track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1374		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1375			r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1376			if (r) {
1377				dev_warn(p->dev, "bad SET_CONTEXT_REG "
1378						"0x%04X\n", reg);
1379				return -EINVAL;
1380			}
1381			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1382			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1383		}
1384		track->cb_dirty = true;
1385		break;
1386	case CB_COLOR8_INFO:
1387	case CB_COLOR9_INFO:
1388	case CB_COLOR10_INFO:
1389	case CB_COLOR11_INFO:
1390		tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1391		track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1392		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1393			r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1394			if (r) {
1395				dev_warn(p->dev, "bad SET_CONTEXT_REG "
1396						"0x%04X\n", reg);
1397				return -EINVAL;
1398			}
1399			ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1400			track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1401		}
1402		track->cb_dirty = true;
1403		break;
1404	case CB_COLOR0_PITCH:
1405	case CB_COLOR1_PITCH:
1406	case CB_COLOR2_PITCH:
1407	case CB_COLOR3_PITCH:
1408	case CB_COLOR4_PITCH:
1409	case CB_COLOR5_PITCH:
1410	case CB_COLOR6_PITCH:
1411	case CB_COLOR7_PITCH:
1412		tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1413		track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1414		track->cb_dirty = true;
1415		break;
1416	case CB_COLOR8_PITCH:
1417	case CB_COLOR9_PITCH:
1418	case CB_COLOR10_PITCH:
1419	case CB_COLOR11_PITCH:
1420		tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1421		track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1422		track->cb_dirty = true;
1423		break;
1424	case CB_COLOR0_SLICE:
1425	case CB_COLOR1_SLICE:
1426	case CB_COLOR2_SLICE:
1427	case CB_COLOR3_SLICE:
1428	case CB_COLOR4_SLICE:
1429	case CB_COLOR5_SLICE:
1430	case CB_COLOR6_SLICE:
1431	case CB_COLOR7_SLICE:
1432		tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1433		track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1434		track->cb_color_slice_idx[tmp] = idx;
1435		track->cb_dirty = true;
1436		break;
1437	case CB_COLOR8_SLICE:
1438	case CB_COLOR9_SLICE:
1439	case CB_COLOR10_SLICE:
1440	case CB_COLOR11_SLICE:
1441		tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1442		track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1443		track->cb_color_slice_idx[tmp] = idx;
1444		track->cb_dirty = true;
1445		break;
1446	case CB_COLOR0_ATTRIB:
1447	case CB_COLOR1_ATTRIB:
1448	case CB_COLOR2_ATTRIB:
1449	case CB_COLOR3_ATTRIB:
1450	case CB_COLOR4_ATTRIB:
1451	case CB_COLOR5_ATTRIB:
1452	case CB_COLOR6_ATTRIB:
1453	case CB_COLOR7_ATTRIB:
1454		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1455		if (r) {
1456			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1457					"0x%04X\n", reg);
1458			return -EINVAL;
1459		}
1460		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1461			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1462				unsigned bankw, bankh, mtaspect, tile_split;
1463
1464				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1465							&bankw, &bankh, &mtaspect,
1466							&tile_split);
1467				ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1468				ib[idx] |= CB_TILE_SPLIT(tile_split) |
1469					   CB_BANK_WIDTH(bankw) |
1470					   CB_BANK_HEIGHT(bankh) |
1471					   CB_MACRO_TILE_ASPECT(mtaspect);
1472			}
1473		}
1474		tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1475		track->cb_color_attrib[tmp] = ib[idx];
1476		track->cb_dirty = true;
1477		break;
1478	case CB_COLOR8_ATTRIB:
1479	case CB_COLOR9_ATTRIB:
1480	case CB_COLOR10_ATTRIB:
1481	case CB_COLOR11_ATTRIB:
1482		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1483		if (r) {
1484			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1485					"0x%04X\n", reg);
1486			return -EINVAL;
1487		}
1488		if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1489			if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1490				unsigned bankw, bankh, mtaspect, tile_split;
1491
1492				evergreen_tiling_fields(reloc->lobj.tiling_flags,
1493							&bankw, &bankh, &mtaspect,
1494							&tile_split);
1495				ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1496				ib[idx] |= CB_TILE_SPLIT(tile_split) |
1497					   CB_BANK_WIDTH(bankw) |
1498					   CB_BANK_HEIGHT(bankh) |
1499					   CB_MACRO_TILE_ASPECT(mtaspect);
1500			}
1501		}
1502		tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1503		track->cb_color_attrib[tmp] = ib[idx];
1504		track->cb_dirty = true;
1505		break;
1506	case CB_COLOR0_FMASK:
1507	case CB_COLOR1_FMASK:
1508	case CB_COLOR2_FMASK:
1509	case CB_COLOR3_FMASK:
1510	case CB_COLOR4_FMASK:
1511	case CB_COLOR5_FMASK:
1512	case CB_COLOR6_FMASK:
1513	case CB_COLOR7_FMASK:
1514		tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1515		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1516		if (r) {
1517			dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1518			return -EINVAL;
1519		}
1520		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1521		track->cb_color_fmask_bo[tmp] = reloc->robj;
1522		break;
1523	case CB_COLOR0_CMASK:
1524	case CB_COLOR1_CMASK:
1525	case CB_COLOR2_CMASK:
1526	case CB_COLOR3_CMASK:
1527	case CB_COLOR4_CMASK:
1528	case CB_COLOR5_CMASK:
1529	case CB_COLOR6_CMASK:
1530	case CB_COLOR7_CMASK:
1531		tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1532		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1533		if (r) {
1534			dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1535			return -EINVAL;
1536		}
1537		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1538		track->cb_color_cmask_bo[tmp] = reloc->robj;
1539		break;
1540	case CB_COLOR0_FMASK_SLICE:
1541	case CB_COLOR1_FMASK_SLICE:
1542	case CB_COLOR2_FMASK_SLICE:
1543	case CB_COLOR3_FMASK_SLICE:
1544	case CB_COLOR4_FMASK_SLICE:
1545	case CB_COLOR5_FMASK_SLICE:
1546	case CB_COLOR6_FMASK_SLICE:
1547	case CB_COLOR7_FMASK_SLICE:
1548		tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1549		track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1550		break;
1551	case CB_COLOR0_CMASK_SLICE:
1552	case CB_COLOR1_CMASK_SLICE:
1553	case CB_COLOR2_CMASK_SLICE:
1554	case CB_COLOR3_CMASK_SLICE:
1555	case CB_COLOR4_CMASK_SLICE:
1556	case CB_COLOR5_CMASK_SLICE:
1557	case CB_COLOR6_CMASK_SLICE:
1558	case CB_COLOR7_CMASK_SLICE:
1559		tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1560		track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1561		break;
1562	case CB_COLOR0_BASE:
1563	case CB_COLOR1_BASE:
1564	case CB_COLOR2_BASE:
1565	case CB_COLOR3_BASE:
1566	case CB_COLOR4_BASE:
1567	case CB_COLOR5_BASE:
1568	case CB_COLOR6_BASE:
1569	case CB_COLOR7_BASE:
1570		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1571		if (r) {
1572			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1573					"0x%04X\n", reg);
1574			return -EINVAL;
1575		}
1576		tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1577		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1578		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1579		track->cb_color_bo[tmp] = reloc->robj;
1580		track->cb_dirty = true;
1581		break;
1582	case CB_COLOR8_BASE:
1583	case CB_COLOR9_BASE:
1584	case CB_COLOR10_BASE:
1585	case CB_COLOR11_BASE:
1586		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1587		if (r) {
1588			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1589					"0x%04X\n", reg);
1590			return -EINVAL;
1591		}
1592		tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1593		track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1594		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1595		track->cb_color_bo[tmp] = reloc->robj;
1596		track->cb_dirty = true;
1597		break;
1598	case DB_HTILE_DATA_BASE:
1599		r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1600		if (r) {
1601			dev_warn(p->dev, "bad SET_CONTEXT_REG "
1602					"0x%04X\n", reg);
1603			return -EINVAL;
1604		}
1605		track->htile_offset = radeon_get_ib_value(p, idx);
1606		ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1607		track->htile_bo = reloc->robj;
1608		track->db_dirty = true;
1609		break;
1610	case DB_HTILE_SURFACE:
1611		/* 8x8 only */
1612		track->htile_surface = radeon_get_ib_value(p, idx);
1613		/* force 8x8 htile width and height */
1614		ib[idx] |= 3;
1615		track->db_dirty = true;
1616		break;
1617	case CB_IMMED0_BASE:
1618	case CB_IMMED1_BASE:
1619	case CB_IMMED2_BASE:
1620	case CB_IMMED3_BASE:
1621	case CB_IMMED4_BASE:
1622	case CB_IMMED5_BASE:
1623	case CB_IMMED6_BASE:
1624	case CB_IMMED7_BASE:
1625	case CB_IMMED8_BASE:
1626	case CB_IMMED9_BASE:
1627	case CB_IMMED10_BASE:
1628	case CB_IMMED11_BASE:
1629	case SQ_PGM_START_FS:
1630	case SQ_PGM_START_ES:
1631	case SQ_PGM_START_VS:
1632	case SQ_PGM_START_GS:
1633	case SQ_PGM_START_PS:
1634	case SQ_PGM_START_HS:
1635	case SQ_PGM_START_LS:
1636	case SQ_CONST_MEM_BASE:
1637	case SQ_ALU_CONST_CACHE_GS_0:
1638	case SQ_ALU_CONST_CACHE_GS_1:
1639	case SQ_ALU_CONST_CACHE_GS_2:
1640	case SQ_ALU_CONST_CACHE_GS_3:
1641	case SQ_ALU_CONST_CACHE_GS_4:
1642	case SQ_ALU_CONST_CACHE_GS_5:
1643	case SQ_ALU_CONST_CACHE_GS_6:
1644	case SQ_ALU_CONST_CACHE_GS_7:
1645	case SQ_ALU_CONST_CACHE_GS_8:
1646	case SQ_ALU_CONST_CACHE_GS_9:
1647	case SQ_ALU_CONST_CACHE_GS_10:
1648	case SQ_ALU_CONST_CACHE_GS_11:
1649	case SQ_ALU_CONST_CACHE_GS_12:
1650	case SQ_ALU_CONST_CACHE_GS_13:
1651	case SQ_ALU_CONST_CACHE_GS_14:
1652	case SQ_ALU_CONST_CACHE_GS_15:
1653	case SQ_ALU_CONST_CACHE_PS_0:
1654	case SQ_ALU_CONST_CACHE_PS_1:
1655	case SQ_ALU_CONST_CACHE_PS_2:
1656	case SQ_ALU_CONST_CACHE_PS_3:
1657	case SQ_ALU_CONST_CACHE_PS_4:
1658	case SQ_ALU_CONST_CACHE_PS_5:
1659	case SQ_ALU_CONST_CACHE_PS_6:
1660	case SQ_ALU_CONST_CACHE_PS_7:
1661	case SQ_ALU_CONST_CACHE_PS_8:
1662	case SQ_ALU_CONST_CACHE_PS_9:
1663	case SQ_ALU_CONST_CACHE_PS_10:
1664	case SQ_ALU_CONST_CACHE_PS_11:
1665	case SQ_ALU_CONST_CACHE_PS_12:
1666	case SQ_ALU_CONST_CACHE_PS_13:
1667	case SQ_ALU_CONST_CACHE_PS_14:
1668	case SQ_ALU_CONST_CACHE_PS_15:
1669	case SQ_ALU_CONST_CACHE_VS_0:
1670	case SQ_ALU_CONST_CACHE_VS_1:
1671	case SQ_ALU_CONST_CACHE_VS_2:
1672	case SQ_ALU_CONST_CACHE_VS_3:
1673	case SQ_ALU_CONST_CACHE_VS_4:
1674	case SQ_ALU_CONST_CACHE_VS_5:
1675	case SQ_ALU_CONST_CACHE_VS_6:
1676	case SQ_ALU_CONST_CACHE_VS_7:
1677	case SQ_ALU_CONST_CACHE_VS_8:
1678	case SQ_ALU_CONST_CACHE_VS_9:
1679	case SQ_ALU_CONST_CACHE_VS_10:
1680	case SQ_ALU_CONST_CACHE_VS_11:
1681	case SQ_A

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