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/include/configs/omap3_zoom1.h

https://gitlab.com/ubuntu-omap/u-boot-omap5
C Header | 285 lines | 155 code | 43 blank | 87 comment | 0 complexity | 02675c5214c3e070f38c28d8d8578d3f MD5 | raw file
  1/*
  2 * (C) Copyright 2006-2008
  3 * Texas Instruments.
  4 * Richard Woodruff <r-woodruff2@ti.com>
  5 * Syed Mohammed Khasim <x0khasim@ti.com>
  6 * Nishanth Menon <nm@ti.com>
  7 *
  8 * Configuration settings for the TI OMAP3430 Zoom MDK board.
  9 *
 10 * See file CREDITS for list of people who contributed to this
 11 * project.
 12 *
 13 * This program is free software; you can redistribute it and/or
 14 * modify it under the terms of the GNU General Public License as
 15 * published by the Free Software Foundation; either version 2 of
 16 * the License, or (at your option) any later version.
 17 *
 18 * This program is distributed in the hope that it will be useful,
 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 21 * GNU General Public License for more details.
 22 *
 23 * You should have received a copy of the GNU General Public License
 24 * along with this program; if not, write to the Free Software
 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 26 * MA 02111-1307 USA
 27 */
 28
 29#ifndef __CONFIG_H
 30#define __CONFIG_H
 31
 32/*
 33 * High Level Configuration Options
 34 */
 35#define CONFIG_OMAP		1	/* in a TI OMAP core */
 36#define CONFIG_OMAP34XX		1	/* which is a 34XX */
 37#define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
 38
 39#define CONFIG_SDRC	/* The chip has SDRC controller */
 40
 41#include <asm/arch/cpu.h>		/* get chip and board defs */
 42#include <asm/arch/omap3.h>
 43
 44/*
 45 * Display CPU and Board information
 46 */
 47#define CONFIG_DISPLAY_CPUINFO		1
 48#define CONFIG_DISPLAY_BOARDINFO	1
 49
 50/* Clock Defines */
 51#define V_OSCK			26000000	/* Clock output from T2 */
 52#define V_SCLK			(V_OSCK >> 1)
 53
 54#define CONFIG_MISC_INIT_R
 55
 56#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
 57#define CONFIG_SETUP_MEMORY_TAGS	1
 58#define CONFIG_INITRD_TAG		1
 59#define CONFIG_REVISION_TAG		1
 60
 61#define CONFIG_OF_LIBFDT		1
 62
 63/*
 64 * Size of malloc() pool
 65 */
 66#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 67						/* Sector */
 68#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 69
 70/*
 71 * Hardware drivers
 72 */
 73
 74/*
 75 * NS16550 Configuration
 76 */
 77#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
 78
 79#define CONFIG_SYS_NS16550
 80#define CONFIG_SYS_NS16550_SERIAL
 81#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 82#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
 83
 84/*
 85 * select serial console configuration
 86 */
 87#define CONFIG_CONS_INDEX		3
 88#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
 89#define CONFIG_SERIAL3			3	/* UART3 */
 90
 91/* allow to overwrite serial and ethaddr */
 92#define CONFIG_ENV_OVERWRITE
 93#define CONFIG_BAUDRATE			115200
 94#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 95					115200}
 96#define CONFIG_GENERIC_MMC		1
 97#define CONFIG_MMC			1
 98#define CONFIG_OMAP_HSMMC		1
 99#define CONFIG_DOS_PARTITION		1
100
101/* USB */
102#define CONFIG_MUSB_UDC			1
103#define CONFIG_USB_OMAP3		1
104#define CONFIG_TWL4030_USB		1
105
106/* USB device configuration */
107#define CONFIG_USB_DEVICE		1
108#define CONFIG_USB_TTY			1
109#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
110/* Change these to suit your needs */
111#define CONFIG_USBD_VENDORID		0x0451
112#define CONFIG_USBD_PRODUCTID		0x5678
113#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
114#define CONFIG_USBD_PRODUCT_NAME	"Zoom1"
115
116/* commands to include */
117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
120#define CONFIG_CMD_FAT		/* FAT support			*/
121#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
122
123#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
124#define CONFIG_CMD_MMC		/* MMC support			*/
125#define CONFIG_CMD_NAND		/* NAND support			*/
126#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
127
128#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
129#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
130#undef CONFIG_CMD_IMI		/* iminfo			*/
131#undef CONFIG_CMD_IMLS		/* List all found images	*/
132#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
133#undef CONFIG_CMD_NFS		/* NFS support			*/
134
135#define CONFIG_SYS_NO_FLASH
136#define CONFIG_HARD_I2C			1
137#define CONFIG_SYS_I2C_SPEED		100000
138#define CONFIG_SYS_I2C_SLAVE		1
139#define CONFIG_DRIVER_OMAP34XX_I2C	1
140
141/*
142 * TWL4030
143 */
144#define CONFIG_TWL4030_POWER		1
145#define CONFIG_TWL4030_LED		1
146
147/*
148 * Board NAND Info.
149 */
150#define CONFIG_NAND_OMAP_GPMC
151#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
152							/* to access nand */
153#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
154							/* to access nand at */
155							/* CS0 */
156#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
157
158#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
159							/* devices */
160#define CONFIG_JFFS2_NAND
161/* nand device jffs2 lives on */
162#define CONFIG_JFFS2_DEV		"nand0"
163/* start of jffs2 partition */
164#define CONFIG_JFFS2_PART_OFFSET	0x680000
165#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
166							/* partition */
167
168/* Environment information */
169#define CONFIG_BOOTDELAY		10
170
171#define CONFIG_EXTRA_ENV_SETTINGS \
172	"loadaddr=0x82000000\0" \
173	"usbtty=cdc_acm\0" \
174	"console=ttyS2,115200n8\0" \
175	"mmcdev=0\0" \
176	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
177	"videospec=omapfb:vram:2M,vram:4M\0" \
178	"mmcargs=setenv bootargs console=${console} " \
179		"video=${videospec},mode:${videomode} " \
180		"root=/dev/mmcblk0p2 rw " \
181		"rootfstype=ext3 rootwait\0" \
182	"nandargs=setenv bootargs console=${console} " \
183		"video=${videospec},mode:${videomode} " \
184		"root=/dev/mtdblock4 rw " \
185		"rootfstype=jffs2\0" \
186	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
187	"bootscript=echo Running bootscript from mmc ...; " \
188		"source ${loadaddr}\0" \
189	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
190	"mmcboot=echo Booting from mmc ...; " \
191		"run mmcargs; " \
192		"bootm ${loadaddr}\0" \
193	"nandboot=echo Booting from nand ...; " \
194		"run nandargs; " \
195		"nand read ${loadaddr} 280000 400000; " \
196		"bootm ${loadaddr}\0" \
197
198#define CONFIG_BOOTCOMMAND \
199	"mmc dev ${mmcdev}; if mmc rescan; then " \
200		"if run loadbootscript; then " \
201			"run bootscript; " \
202		"else " \
203			"if run loaduimage; then " \
204				"run mmcboot; " \
205			"else run nandboot; " \
206			"fi; " \
207		"fi; " \
208	"else run nandboot; fi"
209
210#define CONFIG_AUTO_COMPLETE		1
211/*
212 * Miscellaneous configurable options
213 */
214#define CONFIG_SYS_LONGHELP		/* undef to save memory */
215#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
216#define CONFIG_SYS_PROMPT		"OMAP3 Zoom1 # "
217#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
218/* Print Buffer Size */
219#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
220					sizeof(CONFIG_SYS_PROMPT) + 16)
221#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
222/* Boot Argument Buffer Size */
223#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
224
225#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
226								/* works on */
227#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
228					0x01F00000) /* 31MB */
229
230#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
231							/* load address */
232
233#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
234#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
235#define CONFIG_SYS_INIT_RAM_SIZE	0x800
236#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
237					 CONFIG_SYS_INIT_RAM_SIZE - \
238					 GENERATED_GBL_DATA_SIZE)
239/*
240 * OMAP3 has 12 GP timers, they can be driven by the system clock
241 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
242 * This rate is divided by a local divisor.
243 */
244#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
245#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
246#define CONFIG_SYS_HZ			1000
247
248/*-----------------------------------------------------------------------
249 * Physical Memory Map
250 */
251#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
252#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
253#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
254
255/*-----------------------------------------------------------------------
256 * FLASH and environment organization
257 */
258
259/* **** PISMO SUPPORT *** */
260
261/* Configure the PISMO */
262#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
263#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
264
265#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
266
267#if defined(CONFIG_CMD_NAND)
268#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
269#endif
270
271/* Monitor at start of flash */
272#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
273#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
274
275#define CONFIG_ENV_IS_IN_NAND		1
276#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
277#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
278
279#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
280#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
281#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
282
283#define CONFIG_SYS_CACHELINE_SIZE	64
284
285#endif				/* __CONFIG_H */