PageRenderTime 76ms CodeModel.GetById 22ms app.highlight 44ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/x86/kernel/smpboot.c

https://gitlab.com/Team-OSE-old/SimpleKernel
C | 1429 lines | 833 code | 219 blank | 377 comment | 144 complexity | e8b2bc7a9c9739bf288b7bb1a6273352 MD5 | raw file
   1/*
   2 *	x86 SMP booting functions
   3 *
   4 *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
   5 *	(c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
   6 *	Copyright 2001 Andi Kleen, SuSE Labs.
   7 *
   8 *	Much of the core SMP work is based on previous work by Thomas Radke, to
   9 *	whom a great many thanks are extended.
  10 *
  11 *	Thanks to Intel for making available several different Pentium,
  12 *	Pentium Pro and Pentium-II/Xeon MP machines.
  13 *	Original development of Linux SMP code supported by Caldera.
  14 *
  15 *	This code is released under the GNU General Public License version 2 or
  16 *	later.
  17 *
  18 *	Fixes
  19 *		Felix Koop	:	NR_CPUS used properly
  20 *		Jose Renau	:	Handle single CPU case.
  21 *		Alan Cox	:	By repeated request 8) - Total BogoMIPS report.
  22 *		Greg Wright	:	Fix for kernel stacks panic.
  23 *		Erich Boleyn	:	MP v1.4 and additional changes.
  24 *	Matthias Sattler	:	Changes for 2.1 kernel map.
  25 *	Michel Lespinasse	:	Changes for 2.1 kernel map.
  26 *	Michael Chastain	:	Change trampoline.S to gnu as.
  27 *		Alan Cox	:	Dumb bug: 'B' step PPro's are fine
  28 *		Ingo Molnar	:	Added APIC timers, based on code
  29 *					from Jose Renau
  30 *		Ingo Molnar	:	various cleanups and rewrites
  31 *		Tigran Aivazian	:	fixed "0.00 in /proc/uptime on SMP" bug.
  32 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs
  33 *	Andi Kleen		:	Changed for SMP boot into long mode.
  34 *		Martin J. Bligh	: 	Added support for multi-quad systems
  35 *		Dave Jones	:	Report invalid combinations of Athlon CPUs.
  36 *		Rusty Russell	:	Hacked into shape for new "hotplug" boot process.
  37 *      Andi Kleen              :       Converted to new state machine.
  38 *	Ashok Raj		: 	CPU hotplug support
  39 *	Glauber Costa		:	i386 and x86_64 integration
  40 */
  41
  42#include <linux/init.h>
  43#include <linux/smp.h>
  44#include <linux/module.h>
  45#include <linux/sched.h>
  46#include <linux/percpu.h>
  47#include <linux/bootmem.h>
  48#include <linux/err.h>
  49#include <linux/nmi.h>
  50#include <linux/tboot.h>
  51#include <linux/stackprotector.h>
  52#include <linux/gfp.h>
  53#include <linux/cpuidle.h>
  54
  55#include <asm/acpi.h>
  56#include <asm/desc.h>
  57#include <asm/nmi.h>
  58#include <asm/irq.h>
  59#include <asm/idle.h>
  60#include <asm/trampoline.h>
  61#include <asm/cpu.h>
  62#include <asm/numa.h>
  63#include <asm/pgtable.h>
  64#include <asm/tlbflush.h>
  65#include <asm/mtrr.h>
  66#include <asm/mwait.h>
  67#include <asm/apic.h>
  68#include <asm/io_apic.h>
  69#include <asm/setup.h>
  70#include <asm/uv/uv.h>
  71#include <linux/mc146818rtc.h>
  72
  73#include <asm/smpboot_hooks.h>
  74#include <asm/i8259.h>
  75
  76/* State of each CPU */
  77DEFINE_PER_CPU(int, cpu_state) = { 0 };
  78
  79/* Store all idle threads, this can be reused instead of creating
  80* a new thread. Also avoids complicated thread destroy functionality
  81* for idle threads.
  82*/
  83#ifdef CONFIG_HOTPLUG_CPU
  84/*
  85 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
  86 * removed after init for !CONFIG_HOTPLUG_CPU.
  87 */
  88static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
  89#define get_idle_for_cpu(x)      (per_cpu(idle_thread_array, x))
  90#define set_idle_for_cpu(x, p)   (per_cpu(idle_thread_array, x) = (p))
  91
  92/*
  93 * We need this for trampoline_base protection from concurrent accesses when
  94 * off- and onlining cores wildly.
  95 */
  96static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
  97
  98void cpu_hotplug_driver_lock(void)
  99{
 100        mutex_lock(&x86_cpu_hotplug_driver_mutex);
 101}
 102
 103void cpu_hotplug_driver_unlock(void)
 104{
 105        mutex_unlock(&x86_cpu_hotplug_driver_mutex);
 106}
 107
 108ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
 109ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
 110#else
 111static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
 112#define get_idle_for_cpu(x)      (idle_thread_array[(x)])
 113#define set_idle_for_cpu(x, p)   (idle_thread_array[(x)] = (p))
 114#endif
 115
 116/* Number of siblings per CPU package */
 117int smp_num_siblings = 1;
 118EXPORT_SYMBOL(smp_num_siblings);
 119
 120/* Last level cache ID of each logical CPU */
 121DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
 122
 123/* representing HT siblings of each logical CPU */
 124DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
 125EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
 126
 127/* representing HT and core siblings of each logical CPU */
 128DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
 129EXPORT_PER_CPU_SYMBOL(cpu_core_map);
 130
 131DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
 132
 133/* Per CPU bogomips and other parameters */
 134DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 135EXPORT_PER_CPU_SYMBOL(cpu_info);
 136
 137atomic_t init_deasserted;
 138
 139/*
 140 * Report back to the Boot Processor.
 141 * Running on AP.
 142 */
 143static void __cpuinit smp_callin(void)
 144{
 145	int cpuid, phys_id;
 146	unsigned long timeout;
 147
 148	/*
 149	 * If waken up by an INIT in an 82489DX configuration
 150	 * we may get here before an INIT-deassert IPI reaches
 151	 * our local APIC.  We have to wait for the IPI or we'll
 152	 * lock up on an APIC access.
 153	 */
 154	if (apic->wait_for_init_deassert)
 155		apic->wait_for_init_deassert(&init_deasserted);
 156
 157	/*
 158	 * (This works even if the APIC is not enabled.)
 159	 */
 160	phys_id = read_apic_id();
 161	cpuid = smp_processor_id();
 162	if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
 163		panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
 164					phys_id, cpuid);
 165	}
 166	pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
 167
 168	/*
 169	 * STARTUP IPIs are fragile beasts as they might sometimes
 170	 * trigger some glue motherboard logic. Complete APIC bus
 171	 * silence for 1 second, this overestimates the time the
 172	 * boot CPU is spending to send the up to 2 STARTUP IPIs
 173	 * by a factor of two. This should be enough.
 174	 */
 175
 176	/*
 177	 * Waiting 2s total for startup (udelay is not yet working)
 178	 */
 179	timeout = jiffies + 2*HZ;
 180	while (time_before(jiffies, timeout)) {
 181		/*
 182		 * Has the boot CPU finished it's STARTUP sequence?
 183		 */
 184		if (cpumask_test_cpu(cpuid, cpu_callout_mask))
 185			break;
 186		cpu_relax();
 187	}
 188
 189	if (!time_before(jiffies, timeout)) {
 190		panic("%s: CPU%d started up but did not get a callout!\n",
 191		      __func__, cpuid);
 192	}
 193
 194	/*
 195	 * the boot CPU has finished the init stage and is spinning
 196	 * on callin_map until we finish. We are free to set up this
 197	 * CPU, first the APIC. (this is probably redundant on most
 198	 * boards)
 199	 */
 200
 201	pr_debug("CALLIN, before setup_local_APIC().\n");
 202	if (apic->smp_callin_clear_local_apic)
 203		apic->smp_callin_clear_local_apic();
 204	setup_local_APIC();
 205	end_local_APIC_setup();
 206
 207	/*
 208	 * Need to setup vector mappings before we enable interrupts.
 209	 */
 210	setup_vector_irq(smp_processor_id());
 211
 212	/*
 213	 * Save our processor parameters. Note: this information
 214	 * is needed for clock calibration.
 215	 */
 216	smp_store_cpu_info(cpuid);
 217
 218	/*
 219	 * Get our bogomips.
 220	 * Update loops_per_jiffy in cpu_data. Previous call to
 221	 * smp_store_cpu_info() stored a value that is close but not as
 222	 * accurate as the value just calculated.
 223	 */
 224	calibrate_delay();
 225	cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
 226	pr_debug("Stack at about %p\n", &cpuid);
 227
 228	/*
 229	 * This must be done before setting cpu_online_mask
 230	 * or calling notify_cpu_starting.
 231	 */
 232	set_cpu_sibling_map(raw_smp_processor_id());
 233	wmb();
 234
 235	notify_cpu_starting(cpuid);
 236
 237	/*
 238	 * Allow the master to continue.
 239	 */
 240	cpumask_set_cpu(cpuid, cpu_callin_mask);
 241}
 242
 243/*
 244 * Activate a secondary processor.
 245 */
 246notrace static void __cpuinit start_secondary(void *unused)
 247{
 248	/*
 249	 * Don't put *anything* before cpu_init(), SMP booting is too
 250	 * fragile that we want to limit the things done here to the
 251	 * most necessary things.
 252	 */
 253	cpu_init();
 254	x86_cpuinit.early_percpu_clock_init();
 255	preempt_disable();
 256	smp_callin();
 257
 258#ifdef CONFIG_X86_32
 259	/* switch away from the initial page table */
 260	load_cr3(swapper_pg_dir);
 261	__flush_tlb_all();
 262#endif
 263
 264	/* otherwise gcc will move up smp_processor_id before the cpu_init */
 265	barrier();
 266	/*
 267	 * Check TSC synchronization with the BP:
 268	 */
 269	check_tsc_sync_target();
 270
 271	/*
 272	 * We need to hold call_lock, so there is no inconsistency
 273	 * between the time smp_call_function() determines number of
 274	 * IPI recipients, and the time when the determination is made
 275	 * for which cpus receive the IPI. Holding this
 276	 * lock helps us to not include this cpu in a currently in progress
 277	 * smp_call_function().
 278	 *
 279	 * We need to hold vector_lock so there the set of online cpus
 280	 * does not change while we are assigning vectors to cpus.  Holding
 281	 * this lock ensures we don't half assign or remove an irq from a cpu.
 282	 */
 283	ipi_call_lock();
 284	lock_vector_lock();
 285	set_cpu_online(smp_processor_id(), true);
 286	unlock_vector_lock();
 287	ipi_call_unlock();
 288	per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
 289	x86_platform.nmi_init();
 290
 291	/* enable local interrupts */
 292	local_irq_enable();
 293
 294	/* to prevent fake stack check failure in clock setup */
 295	boot_init_stack_canary();
 296
 297	x86_cpuinit.setup_percpu_clockev();
 298
 299	wmb();
 300	cpu_idle();
 301}
 302
 303/*
 304 * The bootstrap kernel entry code has set these up. Save them for
 305 * a given CPU
 306 */
 307
 308void __cpuinit smp_store_cpu_info(int id)
 309{
 310	struct cpuinfo_x86 *c = &cpu_data(id);
 311
 312	*c = boot_cpu_data;
 313	c->cpu_index = id;
 314	if (id != 0)
 315		identify_secondary_cpu(c);
 316}
 317
 318static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
 319{
 320	cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
 321	cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
 322	cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
 323	cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
 324	cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
 325	cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
 326}
 327
 328
 329void __cpuinit set_cpu_sibling_map(int cpu)
 330{
 331	int i;
 332	struct cpuinfo_x86 *c = &cpu_data(cpu);
 333
 334	cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
 335
 336	if (smp_num_siblings > 1) {
 337		for_each_cpu(i, cpu_sibling_setup_mask) {
 338			struct cpuinfo_x86 *o = &cpu_data(i);
 339
 340			if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
 341				if (c->phys_proc_id == o->phys_proc_id &&
 342				    per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
 343				    c->compute_unit_id == o->compute_unit_id)
 344					link_thread_siblings(cpu, i);
 345			} else if (c->phys_proc_id == o->phys_proc_id &&
 346				   c->cpu_core_id == o->cpu_core_id) {
 347				link_thread_siblings(cpu, i);
 348			}
 349		}
 350	} else {
 351		cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
 352	}
 353
 354	cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
 355
 356	if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
 357		cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
 358		c->booted_cores = 1;
 359		return;
 360	}
 361
 362	for_each_cpu(i, cpu_sibling_setup_mask) {
 363		if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
 364		    per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
 365			cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
 366			cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
 367		}
 368		if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
 369			cpumask_set_cpu(i, cpu_core_mask(cpu));
 370			cpumask_set_cpu(cpu, cpu_core_mask(i));
 371			/*
 372			 *  Does this new cpu bringup a new core?
 373			 */
 374			if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
 375				/*
 376				 * for each core in package, increment
 377				 * the booted_cores for this new cpu
 378				 */
 379				if (cpumask_first(cpu_sibling_mask(i)) == i)
 380					c->booted_cores++;
 381				/*
 382				 * increment the core count for all
 383				 * the other cpus in this package
 384				 */
 385				if (i != cpu)
 386					cpu_data(i).booted_cores++;
 387			} else if (i != cpu && !c->booted_cores)
 388				c->booted_cores = cpu_data(i).booted_cores;
 389		}
 390	}
 391}
 392
 393/* maps the cpu to the sched domain representing multi-core */
 394const struct cpumask *cpu_coregroup_mask(int cpu)
 395{
 396	struct cpuinfo_x86 *c = &cpu_data(cpu);
 397	/*
 398	 * For perf, we return last level cache shared map.
 399	 * And for power savings, we return cpu_core_map
 400	 */
 401	if ((sched_mc_power_savings || sched_smt_power_savings) &&
 402	    !(cpu_has(c, X86_FEATURE_AMD_DCM)))
 403		return cpu_core_mask(cpu);
 404	else
 405		return cpu_llc_shared_mask(cpu);
 406}
 407
 408static void impress_friends(void)
 409{
 410	int cpu;
 411	unsigned long bogosum = 0;
 412	/*
 413	 * Allow the user to impress friends.
 414	 */
 415	pr_debug("Before bogomips.\n");
 416	for_each_possible_cpu(cpu)
 417		if (cpumask_test_cpu(cpu, cpu_callout_mask))
 418			bogosum += cpu_data(cpu).loops_per_jiffy;
 419	printk(KERN_INFO
 420		"Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
 421		num_online_cpus(),
 422		bogosum/(500000/HZ),
 423		(bogosum/(5000/HZ))%100);
 424
 425	pr_debug("Before bogocount - setting activated=1.\n");
 426}
 427
 428void __inquire_remote_apic(int apicid)
 429{
 430	unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
 431	const char * const names[] = { "ID", "VERSION", "SPIV" };
 432	int timeout;
 433	u32 status;
 434
 435	printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
 436
 437	for (i = 0; i < ARRAY_SIZE(regs); i++) {
 438		printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
 439
 440		/*
 441		 * Wait for idle.
 442		 */
 443		status = safe_apic_wait_icr_idle();
 444		if (status)
 445			printk(KERN_CONT
 446			       "a previous APIC delivery may have failed\n");
 447
 448		apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
 449
 450		timeout = 0;
 451		do {
 452			udelay(100);
 453			status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
 454		} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
 455
 456		switch (status) {
 457		case APIC_ICR_RR_VALID:
 458			status = apic_read(APIC_RRR);
 459			printk(KERN_CONT "%08x\n", status);
 460			break;
 461		default:
 462			printk(KERN_CONT "failed\n");
 463		}
 464	}
 465}
 466
 467/*
 468 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
 469 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
 470 * won't ... remember to clear down the APIC, etc later.
 471 */
 472int __cpuinit
 473wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
 474{
 475	unsigned long send_status, accept_status = 0;
 476	int maxlvt;
 477
 478	/* Target chip */
 479	/* Boot on the stack */
 480	/* Kick the second */
 481	apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
 482
 483	pr_debug("Waiting for send to finish...\n");
 484	send_status = safe_apic_wait_icr_idle();
 485
 486	/*
 487	 * Give the other CPU some time to accept the IPI.
 488	 */
 489	udelay(200);
 490	if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
 491		maxlvt = lapic_get_maxlvt();
 492		if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
 493			apic_write(APIC_ESR, 0);
 494		accept_status = (apic_read(APIC_ESR) & 0xEF);
 495	}
 496	pr_debug("NMI sent.\n");
 497
 498	if (send_status)
 499		printk(KERN_ERR "APIC never delivered???\n");
 500	if (accept_status)
 501		printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
 502
 503	return (send_status | accept_status);
 504}
 505
 506static int __cpuinit
 507wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
 508{
 509	unsigned long send_status, accept_status = 0;
 510	int maxlvt, num_starts, j;
 511
 512	maxlvt = lapic_get_maxlvt();
 513
 514	/*
 515	 * Be paranoid about clearing APIC errors.
 516	 */
 517	if (APIC_INTEGRATED(apic_version[phys_apicid])) {
 518		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
 519			apic_write(APIC_ESR, 0);
 520		apic_read(APIC_ESR);
 521	}
 522
 523	pr_debug("Asserting INIT.\n");
 524
 525	/*
 526	 * Turn INIT on target chip
 527	 */
 528	/*
 529	 * Send IPI
 530	 */
 531	apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
 532		       phys_apicid);
 533
 534	pr_debug("Waiting for send to finish...\n");
 535	send_status = safe_apic_wait_icr_idle();
 536
 537	mdelay(10);
 538
 539	pr_debug("Deasserting INIT.\n");
 540
 541	/* Target chip */
 542	/* Send IPI */
 543	apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
 544
 545	pr_debug("Waiting for send to finish...\n");
 546	send_status = safe_apic_wait_icr_idle();
 547
 548	mb();
 549	atomic_set(&init_deasserted, 1);
 550
 551	/*
 552	 * Should we send STARTUP IPIs ?
 553	 *
 554	 * Determine this based on the APIC version.
 555	 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
 556	 */
 557	if (APIC_INTEGRATED(apic_version[phys_apicid]))
 558		num_starts = 2;
 559	else
 560		num_starts = 0;
 561
 562	/*
 563	 * Paravirt / VMI wants a startup IPI hook here to set up the
 564	 * target processor state.
 565	 */
 566	startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
 567			 stack_start);
 568
 569	/*
 570	 * Run STARTUP IPI loop.
 571	 */
 572	pr_debug("#startup loops: %d.\n", num_starts);
 573
 574	for (j = 1; j <= num_starts; j++) {
 575		pr_debug("Sending STARTUP #%d.\n", j);
 576		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
 577			apic_write(APIC_ESR, 0);
 578		apic_read(APIC_ESR);
 579		pr_debug("After apic_write.\n");
 580
 581		/*
 582		 * STARTUP IPI
 583		 */
 584
 585		/* Target chip */
 586		/* Boot on the stack */
 587		/* Kick the second */
 588		apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
 589			       phys_apicid);
 590
 591		/*
 592		 * Give the other CPU some time to accept the IPI.
 593		 */
 594		udelay(300);
 595
 596		pr_debug("Startup point 1.\n");
 597
 598		pr_debug("Waiting for send to finish...\n");
 599		send_status = safe_apic_wait_icr_idle();
 600
 601		/*
 602		 * Give the other CPU some time to accept the IPI.
 603		 */
 604		udelay(200);
 605		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
 606			apic_write(APIC_ESR, 0);
 607		accept_status = (apic_read(APIC_ESR) & 0xEF);
 608		if (send_status || accept_status)
 609			break;
 610	}
 611	pr_debug("After Startup.\n");
 612
 613	if (send_status)
 614		printk(KERN_ERR "APIC never delivered???\n");
 615	if (accept_status)
 616		printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
 617
 618	return (send_status | accept_status);
 619}
 620
 621struct create_idle {
 622	struct work_struct work;
 623	struct task_struct *idle;
 624	struct completion done;
 625	int cpu;
 626};
 627
 628static void __cpuinit do_fork_idle(struct work_struct *work)
 629{
 630	struct create_idle *c_idle =
 631		container_of(work, struct create_idle, work);
 632
 633	c_idle->idle = fork_idle(c_idle->cpu);
 634	complete(&c_idle->done);
 635}
 636
 637/* reduce the number of lines printed when booting a large cpu count system */
 638static void __cpuinit announce_cpu(int cpu, int apicid)
 639{
 640	static int current_node = -1;
 641	int node = early_cpu_to_node(cpu);
 642
 643	if (system_state == SYSTEM_BOOTING) {
 644		if (node != current_node) {
 645			if (current_node > (-1))
 646				pr_cont(" Ok.\n");
 647			current_node = node;
 648			pr_info("Booting Node %3d, Processors ", node);
 649		}
 650		pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
 651		return;
 652	} else
 653		pr_info("Booting Node %d Processor %d APIC 0x%x\n",
 654			node, cpu, apicid);
 655}
 656
 657/*
 658 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
 659 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
 660 * Returns zero if CPU booted OK, else error code from
 661 * ->wakeup_secondary_cpu.
 662 */
 663static int __cpuinit do_boot_cpu(int apicid, int cpu)
 664{
 665	unsigned long boot_error = 0;
 666	unsigned long start_ip;
 667	int timeout;
 668	struct create_idle c_idle = {
 669		.cpu	= cpu,
 670		.done	= COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
 671	};
 672
 673	INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
 674
 675	alternatives_smp_switch(1);
 676
 677	c_idle.idle = get_idle_for_cpu(cpu);
 678
 679	/*
 680	 * We can't use kernel_thread since we must avoid to
 681	 * reschedule the child.
 682	 */
 683	if (c_idle.idle) {
 684		c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
 685			(THREAD_SIZE +  task_stack_page(c_idle.idle))) - 1);
 686		init_idle(c_idle.idle, cpu);
 687		goto do_rest;
 688	}
 689
 690	schedule_work(&c_idle.work);
 691	wait_for_completion(&c_idle.done);
 692
 693	if (IS_ERR(c_idle.idle)) {
 694		printk("failed fork for CPU %d\n", cpu);
 695		destroy_work_on_stack(&c_idle.work);
 696		return PTR_ERR(c_idle.idle);
 697	}
 698
 699	set_idle_for_cpu(cpu, c_idle.idle);
 700do_rest:
 701	per_cpu(current_task, cpu) = c_idle.idle;
 702#ifdef CONFIG_X86_32
 703	/* Stack for startup_32 can be just as for start_secondary onwards */
 704	irq_ctx_init(cpu);
 705#else
 706	clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
 707	initial_gs = per_cpu_offset(cpu);
 708	per_cpu(kernel_stack, cpu) =
 709		(unsigned long)task_stack_page(c_idle.idle) -
 710		KERNEL_STACK_OFFSET + THREAD_SIZE;
 711#endif
 712	early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
 713	initial_code = (unsigned long)start_secondary;
 714	stack_start  = c_idle.idle->thread.sp;
 715
 716	/* start_ip had better be page-aligned! */
 717	start_ip = trampoline_address();
 718
 719	/* So we see what's up */
 720	announce_cpu(cpu, apicid);
 721
 722	/*
 723	 * This grunge runs the startup process for
 724	 * the targeted processor.
 725	 */
 726
 727	atomic_set(&init_deasserted, 0);
 728
 729	if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
 730
 731		pr_debug("Setting warm reset code and vector.\n");
 732
 733		smpboot_setup_warm_reset_vector(start_ip);
 734		/*
 735		 * Be paranoid about clearing APIC errors.
 736		*/
 737		if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
 738			apic_write(APIC_ESR, 0);
 739			apic_read(APIC_ESR);
 740		}
 741	}
 742
 743	/*
 744	 * Kick the secondary CPU. Use the method in the APIC driver
 745	 * if it's defined - or use an INIT boot APIC message otherwise:
 746	 */
 747	if (apic->wakeup_secondary_cpu)
 748		boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
 749	else
 750		boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
 751
 752	if (!boot_error) {
 753		/*
 754		 * allow APs to start initializing.
 755		 */
 756		pr_debug("Before Callout %d.\n", cpu);
 757		cpumask_set_cpu(cpu, cpu_callout_mask);
 758		pr_debug("After Callout %d.\n", cpu);
 759
 760		/*
 761		 * Wait 5s total for a response
 762		 */
 763		for (timeout = 0; timeout < 50000; timeout++) {
 764			if (cpumask_test_cpu(cpu, cpu_callin_mask))
 765				break;	/* It has booted */
 766			udelay(100);
 767			/*
 768			 * Allow other tasks to run while we wait for the
 769			 * AP to come online. This also gives a chance
 770			 * for the MTRR work(triggered by the AP coming online)
 771			 * to be completed in the stop machine context.
 772			 */
 773			schedule();
 774		}
 775
 776		if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
 777			print_cpu_msr(&cpu_data(cpu));
 778			pr_debug("CPU%d: has booted.\n", cpu);
 779		} else {
 780			boot_error = 1;
 781			if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
 782			    == 0xA5A5A5A5)
 783				/* trampoline started but...? */
 784				pr_err("CPU%d: Stuck ??\n", cpu);
 785			else
 786				/* trampoline code not run */
 787				pr_err("CPU%d: Not responding.\n", cpu);
 788			if (apic->inquire_remote_apic)
 789				apic->inquire_remote_apic(apicid);
 790		}
 791	}
 792
 793	if (boot_error) {
 794		/* Try to put things back the way they were before ... */
 795		numa_remove_cpu(cpu); /* was set by numa_add_cpu */
 796
 797		/* was set by do_boot_cpu() */
 798		cpumask_clear_cpu(cpu, cpu_callout_mask);
 799
 800		/* was set by cpu_init() */
 801		cpumask_clear_cpu(cpu, cpu_initialized_mask);
 802
 803		set_cpu_present(cpu, false);
 804		per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
 805	}
 806
 807	/* mark "stuck" area as not stuck */
 808	*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
 809
 810	if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
 811		/*
 812		 * Cleanup possible dangling ends...
 813		 */
 814		smpboot_restore_warm_reset_vector();
 815	}
 816
 817	destroy_work_on_stack(&c_idle.work);
 818	return boot_error;
 819}
 820
 821int __cpuinit native_cpu_up(unsigned int cpu)
 822{
 823	int apicid = apic->cpu_present_to_apicid(cpu);
 824	unsigned long flags;
 825	int err;
 826
 827	WARN_ON(irqs_disabled());
 828
 829	pr_debug("++++++++++++++++++++=_---CPU UP  %u\n", cpu);
 830
 831	if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
 832	    !physid_isset(apicid, phys_cpu_present_map) ||
 833	    !apic->apic_id_valid(apicid)) {
 834		printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
 835		return -EINVAL;
 836	}
 837
 838	/*
 839	 * Already booted CPU?
 840	 */
 841	if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
 842		pr_debug("do_boot_cpu %d Already started\n", cpu);
 843		return -ENOSYS;
 844	}
 845
 846	/*
 847	 * Save current MTRR state in case it was changed since early boot
 848	 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
 849	 */
 850	mtrr_save_state();
 851
 852	per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
 853
 854	err = do_boot_cpu(apicid, cpu);
 855	if (err) {
 856		pr_debug("do_boot_cpu failed %d\n", err);
 857		return -EIO;
 858	}
 859
 860	/*
 861	 * Check TSC synchronization with the AP (keep irqs disabled
 862	 * while doing so):
 863	 */
 864	local_irq_save(flags);
 865	check_tsc_sync_source(cpu);
 866	local_irq_restore(flags);
 867
 868	while (!cpu_online(cpu)) {
 869		cpu_relax();
 870		touch_nmi_watchdog();
 871	}
 872
 873	return 0;
 874}
 875
 876/**
 877 * arch_disable_smp_support() - disables SMP support for x86 at runtime
 878 */
 879void arch_disable_smp_support(void)
 880{
 881	disable_ioapic_support();
 882}
 883
 884/*
 885 * Fall back to non SMP mode after errors.
 886 *
 887 * RED-PEN audit/test this more. I bet there is more state messed up here.
 888 */
 889static __init void disable_smp(void)
 890{
 891	init_cpu_present(cpumask_of(0));
 892	init_cpu_possible(cpumask_of(0));
 893	smpboot_clear_io_apic_irqs();
 894
 895	if (smp_found_config)
 896		physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
 897	else
 898		physid_set_mask_of_physid(0, &phys_cpu_present_map);
 899	cpumask_set_cpu(0, cpu_sibling_mask(0));
 900	cpumask_set_cpu(0, cpu_core_mask(0));
 901}
 902
 903/*
 904 * Various sanity checks.
 905 */
 906static int __init smp_sanity_check(unsigned max_cpus)
 907{
 908	preempt_disable();
 909
 910#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
 911	if (def_to_bigsmp && nr_cpu_ids > 8) {
 912		unsigned int cpu;
 913		unsigned nr;
 914
 915		printk(KERN_WARNING
 916		       "More than 8 CPUs detected - skipping them.\n"
 917		       "Use CONFIG_X86_BIGSMP.\n");
 918
 919		nr = 0;
 920		for_each_present_cpu(cpu) {
 921			if (nr >= 8)
 922				set_cpu_present(cpu, false);
 923			nr++;
 924		}
 925
 926		nr = 0;
 927		for_each_possible_cpu(cpu) {
 928			if (nr >= 8)
 929				set_cpu_possible(cpu, false);
 930			nr++;
 931		}
 932
 933		nr_cpu_ids = 8;
 934	}
 935#endif
 936
 937	if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
 938		printk(KERN_WARNING
 939			"weird, boot CPU (#%d) not listed by the BIOS.\n",
 940			hard_smp_processor_id());
 941
 942		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
 943	}
 944
 945	/*
 946	 * If we couldn't find an SMP configuration at boot time,
 947	 * get out of here now!
 948	 */
 949	if (!smp_found_config && !acpi_lapic) {
 950		preempt_enable();
 951		printk(KERN_NOTICE "SMP motherboard not detected.\n");
 952		disable_smp();
 953		if (APIC_init_uniprocessor())
 954			printk(KERN_NOTICE "Local APIC not detected."
 955					   " Using dummy APIC emulation.\n");
 956		return -1;
 957	}
 958
 959	/*
 960	 * Should not be necessary because the MP table should list the boot
 961	 * CPU too, but we do it for the sake of robustness anyway.
 962	 */
 963	if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
 964		printk(KERN_NOTICE
 965			"weird, boot CPU (#%d) not listed by the BIOS.\n",
 966			boot_cpu_physical_apicid);
 967		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
 968	}
 969	preempt_enable();
 970
 971	/*
 972	 * If we couldn't find a local APIC, then get out of here now!
 973	 */
 974	if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
 975	    !cpu_has_apic) {
 976		if (!disable_apic) {
 977			pr_err("BIOS bug, local APIC #%d not detected!...\n",
 978				boot_cpu_physical_apicid);
 979			pr_err("... forcing use of dummy APIC emulation."
 980				"(tell your hw vendor)\n");
 981		}
 982		smpboot_clear_io_apic();
 983		disable_ioapic_support();
 984		return -1;
 985	}
 986
 987	verify_local_APIC();
 988
 989	/*
 990	 * If SMP should be disabled, then really disable it!
 991	 */
 992	if (!max_cpus) {
 993		printk(KERN_INFO "SMP mode deactivated.\n");
 994		smpboot_clear_io_apic();
 995
 996		connect_bsp_APIC();
 997		setup_local_APIC();
 998		bsp_end_local_APIC_setup();
 999		return -1;
1000	}
1001
1002	return 0;
1003}
1004
1005static void __init smp_cpu_index_default(void)
1006{
1007	int i;
1008	struct cpuinfo_x86 *c;
1009
1010	for_each_possible_cpu(i) {
1011		c = &cpu_data(i);
1012		/* mark all to hotplug */
1013		c->cpu_index = nr_cpu_ids;
1014	}
1015}
1016
1017/*
1018 * Prepare for SMP bootup.  The MP table or ACPI has been read
1019 * earlier.  Just do some sanity checking here and enable APIC mode.
1020 */
1021void __init native_smp_prepare_cpus(unsigned int max_cpus)
1022{
1023	unsigned int i;
1024
1025	preempt_disable();
1026	smp_cpu_index_default();
1027
1028	/*
1029	 * Setup boot CPU information
1030	 */
1031	smp_store_cpu_info(0); /* Final full version of the data */
1032	cpumask_copy(cpu_callin_mask, cpumask_of(0));
1033	mb();
1034
1035	current_thread_info()->cpu = 0;  /* needed? */
1036	for_each_possible_cpu(i) {
1037		zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1038		zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1039		zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1040	}
1041	set_cpu_sibling_map(0);
1042
1043
1044	if (smp_sanity_check(max_cpus) < 0) {
1045		printk(KERN_INFO "SMP disabled\n");
1046		disable_smp();
1047		goto out;
1048	}
1049
1050	default_setup_apic_routing();
1051
1052	preempt_disable();
1053	if (read_apic_id() != boot_cpu_physical_apicid) {
1054		panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1055		     read_apic_id(), boot_cpu_physical_apicid);
1056		/* Or can we switch back to PIC here? */
1057	}
1058	preempt_enable();
1059
1060	connect_bsp_APIC();
1061
1062	/*
1063	 * Switch from PIC to APIC mode.
1064	 */
1065	setup_local_APIC();
1066
1067	/*
1068	 * Enable IO APIC before setting up error vector
1069	 */
1070	if (!skip_ioapic_setup && nr_ioapics)
1071		enable_IO_APIC();
1072
1073	bsp_end_local_APIC_setup();
1074
1075	if (apic->setup_portio_remap)
1076		apic->setup_portio_remap();
1077
1078	smpboot_setup_io_apic();
1079	/*
1080	 * Set up local APIC timer on boot CPU.
1081	 */
1082
1083	printk(KERN_INFO "CPU%d: ", 0);
1084	print_cpu_info(&cpu_data(0));
1085	x86_init.timers.setup_percpu_clockev();
1086
1087	if (is_uv_system())
1088		uv_system_init();
1089
1090	set_mtrr_aps_delayed_init();
1091out:
1092	preempt_enable();
1093}
1094
1095void arch_disable_nonboot_cpus_begin(void)
1096{
1097	/*
1098	 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1099	 * In the suspend path, we will be back in the SMP mode shortly anyways.
1100	 */
1101	skip_smp_alternatives = true;
1102}
1103
1104void arch_disable_nonboot_cpus_end(void)
1105{
1106	skip_smp_alternatives = false;
1107}
1108
1109void arch_enable_nonboot_cpus_begin(void)
1110{
1111	set_mtrr_aps_delayed_init();
1112}
1113
1114void arch_enable_nonboot_cpus_end(void)
1115{
1116	mtrr_aps_init();
1117}
1118
1119/*
1120 * Early setup to make printk work.
1121 */
1122void __init native_smp_prepare_boot_cpu(void)
1123{
1124	int me = smp_processor_id();
1125	switch_to_new_gdt(me);
1126	/* already set me in cpu_online_mask in boot_cpu_init() */
1127	cpumask_set_cpu(me, cpu_callout_mask);
1128	per_cpu(cpu_state, me) = CPU_ONLINE;
1129}
1130
1131void __init native_smp_cpus_done(unsigned int max_cpus)
1132{
1133	pr_debug("Boot done.\n");
1134
1135	nmi_selftest();
1136	impress_friends();
1137#ifdef CONFIG_X86_IO_APIC
1138	setup_ioapic_dest();
1139#endif
1140	mtrr_aps_init();
1141}
1142
1143static int __initdata setup_possible_cpus = -1;
1144static int __init _setup_possible_cpus(char *str)
1145{
1146	get_option(&str, &setup_possible_cpus);
1147	return 0;
1148}
1149early_param("possible_cpus", _setup_possible_cpus);
1150
1151
1152/*
1153 * cpu_possible_mask should be static, it cannot change as cpu's
1154 * are onlined, or offlined. The reason is per-cpu data-structures
1155 * are allocated by some modules at init time, and dont expect to
1156 * do this dynamically on cpu arrival/departure.
1157 * cpu_present_mask on the other hand can change dynamically.
1158 * In case when cpu_hotplug is not compiled, then we resort to current
1159 * behaviour, which is cpu_possible == cpu_present.
1160 * - Ashok Raj
1161 *
1162 * Three ways to find out the number of additional hotplug CPUs:
1163 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1164 * - The user can overwrite it with possible_cpus=NUM
1165 * - Otherwise don't reserve additional CPUs.
1166 * We do this because additional CPUs waste a lot of memory.
1167 * -AK
1168 */
1169__init void prefill_possible_map(void)
1170{
1171	int i, possible;
1172
1173	/* no processor from mptable or madt */
1174	if (!num_processors)
1175		num_processors = 1;
1176
1177	i = setup_max_cpus ?: 1;
1178	if (setup_possible_cpus == -1) {
1179		possible = num_processors;
1180#ifdef CONFIG_HOTPLUG_CPU
1181		if (setup_max_cpus)
1182			possible += disabled_cpus;
1183#else
1184		if (possible > i)
1185			possible = i;
1186#endif
1187	} else
1188		possible = setup_possible_cpus;
1189
1190	total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1191
1192	/* nr_cpu_ids could be reduced via nr_cpus= */
1193	if (possible > nr_cpu_ids) {
1194		printk(KERN_WARNING
1195			"%d Processors exceeds NR_CPUS limit of %d\n",
1196			possible, nr_cpu_ids);
1197		possible = nr_cpu_ids;
1198	}
1199
1200#ifdef CONFIG_HOTPLUG_CPU
1201	if (!setup_max_cpus)
1202#endif
1203	if (possible > i) {
1204		printk(KERN_WARNING
1205			"%d Processors exceeds max_cpus limit of %u\n",
1206			possible, setup_max_cpus);
1207		possible = i;
1208	}
1209
1210	printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1211		possible, max_t(int, possible - num_processors, 0));
1212
1213	for (i = 0; i < possible; i++)
1214		set_cpu_possible(i, true);
1215	for (; i < NR_CPUS; i++)
1216		set_cpu_possible(i, false);
1217
1218	nr_cpu_ids = possible;
1219}
1220
1221#ifdef CONFIG_HOTPLUG_CPU
1222
1223static void remove_siblinginfo(int cpu)
1224{
1225	int sibling;
1226	struct cpuinfo_x86 *c = &cpu_data(cpu);
1227
1228	for_each_cpu(sibling, cpu_core_mask(cpu)) {
1229		cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1230		/*/
1231		 * last thread sibling in this cpu core going down
1232		 */
1233		if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1234			cpu_data(sibling).booted_cores--;
1235	}
1236
1237	for_each_cpu(sibling, cpu_sibling_mask(cpu))
1238		cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1239	cpumask_clear(cpu_sibling_mask(cpu));
1240	cpumask_clear(cpu_core_mask(cpu));
1241	c->phys_proc_id = 0;
1242	c->cpu_core_id = 0;
1243	cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1244}
1245
1246static void __ref remove_cpu_from_maps(int cpu)
1247{
1248	set_cpu_online(cpu, false);
1249	cpumask_clear_cpu(cpu, cpu_callout_mask);
1250	cpumask_clear_cpu(cpu, cpu_callin_mask);
1251	/* was set by cpu_init() */
1252	cpumask_clear_cpu(cpu, cpu_initialized_mask);
1253	numa_remove_cpu(cpu);
1254}
1255
1256void cpu_disable_common(void)
1257{
1258	int cpu = smp_processor_id();
1259
1260	remove_siblinginfo(cpu);
1261
1262	/* It's now safe to remove this processor from the online map */
1263	lock_vector_lock();
1264	remove_cpu_from_maps(cpu);
1265	unlock_vector_lock();
1266	fixup_irqs();
1267}
1268
1269int native_cpu_disable(void)
1270{
1271	int cpu = smp_processor_id();
1272
1273	/*
1274	 * Perhaps use cpufreq to drop frequency, but that could go
1275	 * into generic code.
1276	 *
1277	 * We won't take down the boot processor on i386 due to some
1278	 * interrupts only being able to be serviced by the BSP.
1279	 * Especially so if we're not using an IOAPIC	-zwane
1280	 */
1281	if (cpu == 0)
1282		return -EBUSY;
1283
1284	clear_local_APIC();
1285
1286	cpu_disable_common();
1287	return 0;
1288}
1289
1290void native_cpu_die(unsigned int cpu)
1291{
1292	/* We don't do anything here: idle task is faking death itself. */
1293	unsigned int i;
1294
1295	for (i = 0; i < 10; i++) {
1296		/* They ack this in play_dead by setting CPU_DEAD */
1297		if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1298			if (system_state == SYSTEM_RUNNING)
1299				pr_info("CPU %u is now offline\n", cpu);
1300
1301			if (1 == num_online_cpus())
1302				alternatives_smp_switch(0);
1303			return;
1304		}
1305		msleep(100);
1306	}
1307	pr_err("CPU %u didn't die...\n", cpu);
1308}
1309
1310void play_dead_common(void)
1311{
1312	idle_task_exit();
1313	reset_lazy_tlbstate();
1314	amd_e400_remove_cpu(raw_smp_processor_id());
1315
1316	mb();
1317	/* Ack it */
1318	__this_cpu_write(cpu_state, CPU_DEAD);
1319
1320	/*
1321	 * With physical CPU hotplug, we should halt the cpu
1322	 */
1323	local_irq_disable();
1324}
1325
1326/*
1327 * We need to flush the caches before going to sleep, lest we have
1328 * dirty data in our caches when we come back up.
1329 */
1330static inline void mwait_play_dead(void)
1331{
1332	unsigned int eax, ebx, ecx, edx;
1333	unsigned int highest_cstate = 0;
1334	unsigned int highest_subcstate = 0;
1335	int i;
1336	void *mwait_ptr;
1337	struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1338
1339	if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1340		return;
1341	if (!this_cpu_has(X86_FEATURE_CLFLSH))
1342		return;
1343	if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1344		return;
1345
1346	eax = CPUID_MWAIT_LEAF;
1347	ecx = 0;
1348	native_cpuid(&eax, &ebx, &ecx, &edx);
1349
1350	/*
1351	 * eax will be 0 if EDX enumeration is not valid.
1352	 * Initialized below to cstate, sub_cstate value when EDX is valid.
1353	 */
1354	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1355		eax = 0;
1356	} else {
1357		edx >>= MWAIT_SUBSTATE_SIZE;
1358		for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1359			if (edx & MWAIT_SUBSTATE_MASK) {
1360				highest_cstate = i;
1361				highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1362			}
1363		}
1364		eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1365			(highest_subcstate - 1);
1366	}
1367
1368	/*
1369	 * This should be a memory location in a cache line which is
1370	 * unlikely to be touched by other processors.  The actual
1371	 * content is immaterial as it is not actually modified in any way.
1372	 */
1373	mwait_ptr = &current_thread_info()->flags;
1374
1375	wbinvd();
1376
1377	while (1) {
1378		/*
1379		 * The CLFLUSH is a workaround for erratum AAI65 for
1380		 * the Xeon 7400 series.  It's not clear it is actually
1381		 * needed, but it should be harmless in either case.
1382		 * The WBINVD is insufficient due to the spurious-wakeup
1383		 * case where we return around the loop.
1384		 */
1385		clflush(mwait_ptr);
1386		__monitor(mwait_ptr, 0, 0);
1387		mb();
1388		__mwait(eax, 0);
1389	}
1390}
1391
1392static inline void hlt_play_dead(void)
1393{
1394	if (__this_cpu_read(cpu_info.x86) >= 4)
1395		wbinvd();
1396
1397	while (1) {
1398		native_halt();
1399	}
1400}
1401
1402void native_play_dead(void)
1403{
1404	play_dead_common();
1405	tboot_shutdown(TB_SHUTDOWN_WFS);
1406
1407	mwait_play_dead();	/* Only returns on failure */
1408	if (cpuidle_play_dead())
1409		hlt_play_dead();
1410}
1411
1412#else /* ... !CONFIG_HOTPLUG_CPU */
1413int native_cpu_disable(void)
1414{
1415	return -ENOSYS;
1416}
1417
1418void native_cpu_die(unsigned int cpu)
1419{
1420	/* We said "no" in __cpu_disable */
1421	BUG();
1422}
1423
1424void native_play_dead(void)
1425{
1426	BUG();
1427}
1428
1429#endif