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/drivers/net/can/flexcan.c

https://codeberg.org/ddevault/linux
C | 1778 lines | 1289 code | 298 blank | 191 comment | 150 complexity | c796b3e0fd09a1771412b88eeec6a903 MD5 | raw file
Possible License(s): GPL-2.0
  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // flexcan.c - FLEXCAN CAN controller driver
  4. //
  5. // Copyright (c) 2005-2006 Varma Electronics Oy
  6. // Copyright (c) 2009 Sascha Hauer, Pengutronix
  7. // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
  8. // Copyright (c) 2014 David Jander, Protonic Holland
  9. //
  10. // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11. #include <linux/netdevice.h>
  12. #include <linux/can.h>
  13. #include <linux/can/dev.h>
  14. #include <linux/can/error.h>
  15. #include <linux/can/led.h>
  16. #include <linux/can/rx-offload.h>
  17. #include <linux/clk.h>
  18. #include <linux/delay.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/mfd/syscon.h>
  22. #include <linux/module.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/regulator/consumer.h>
  28. #include <linux/regmap.h>
  29. #define DRV_NAME "flexcan"
  30. /* 8 for RX fifo and 2 error handling */
  31. #define FLEXCAN_NAPI_WEIGHT (8 + 2)
  32. /* FLEXCAN module configuration register (CANMCR) bits */
  33. #define FLEXCAN_MCR_MDIS BIT(31)
  34. #define FLEXCAN_MCR_FRZ BIT(30)
  35. #define FLEXCAN_MCR_FEN BIT(29)
  36. #define FLEXCAN_MCR_HALT BIT(28)
  37. #define FLEXCAN_MCR_NOT_RDY BIT(27)
  38. #define FLEXCAN_MCR_WAK_MSK BIT(26)
  39. #define FLEXCAN_MCR_SOFTRST BIT(25)
  40. #define FLEXCAN_MCR_FRZ_ACK BIT(24)
  41. #define FLEXCAN_MCR_SUPV BIT(23)
  42. #define FLEXCAN_MCR_SLF_WAK BIT(22)
  43. #define FLEXCAN_MCR_WRN_EN BIT(21)
  44. #define FLEXCAN_MCR_LPM_ACK BIT(20)
  45. #define FLEXCAN_MCR_WAK_SRC BIT(19)
  46. #define FLEXCAN_MCR_DOZE BIT(18)
  47. #define FLEXCAN_MCR_SRX_DIS BIT(17)
  48. #define FLEXCAN_MCR_IRMQ BIT(16)
  49. #define FLEXCAN_MCR_LPRIO_EN BIT(13)
  50. #define FLEXCAN_MCR_AEN BIT(12)
  51. /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  52. #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
  53. #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
  54. #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
  55. #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
  56. #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
  57. /* FLEXCAN control register (CANCTRL) bits */
  58. #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
  59. #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
  60. #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
  61. #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
  62. #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
  63. #define FLEXCAN_CTRL_ERR_MSK BIT(14)
  64. #define FLEXCAN_CTRL_CLK_SRC BIT(13)
  65. #define FLEXCAN_CTRL_LPB BIT(12)
  66. #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
  67. #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
  68. #define FLEXCAN_CTRL_SMP BIT(7)
  69. #define FLEXCAN_CTRL_BOFF_REC BIT(6)
  70. #define FLEXCAN_CTRL_TSYN BIT(5)
  71. #define FLEXCAN_CTRL_LBUF BIT(4)
  72. #define FLEXCAN_CTRL_LOM BIT(3)
  73. #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
  74. #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
  75. #define FLEXCAN_CTRL_ERR_STATE \
  76. (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  77. FLEXCAN_CTRL_BOFF_MSK)
  78. #define FLEXCAN_CTRL_ERR_ALL \
  79. (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  80. /* FLEXCAN control register 2 (CTRL2) bits */
  81. #define FLEXCAN_CTRL2_ECRWRE BIT(29)
  82. #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
  83. #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
  84. #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
  85. #define FLEXCAN_CTRL2_MRP BIT(18)
  86. #define FLEXCAN_CTRL2_RRS BIT(17)
  87. #define FLEXCAN_CTRL2_EACEN BIT(16)
  88. /* FLEXCAN memory error control register (MECR) bits */
  89. #define FLEXCAN_MECR_ECRWRDIS BIT(31)
  90. #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
  91. #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
  92. #define FLEXCAN_MECR_CEI_MSK BIT(16)
  93. #define FLEXCAN_MECR_HAERRIE BIT(15)
  94. #define FLEXCAN_MECR_FAERRIE BIT(14)
  95. #define FLEXCAN_MECR_EXTERRIE BIT(13)
  96. #define FLEXCAN_MECR_RERRDIS BIT(9)
  97. #define FLEXCAN_MECR_ECCDIS BIT(8)
  98. #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
  99. /* FLEXCAN error and status register (ESR) bits */
  100. #define FLEXCAN_ESR_TWRN_INT BIT(17)
  101. #define FLEXCAN_ESR_RWRN_INT BIT(16)
  102. #define FLEXCAN_ESR_BIT1_ERR BIT(15)
  103. #define FLEXCAN_ESR_BIT0_ERR BIT(14)
  104. #define FLEXCAN_ESR_ACK_ERR BIT(13)
  105. #define FLEXCAN_ESR_CRC_ERR BIT(12)
  106. #define FLEXCAN_ESR_FRM_ERR BIT(11)
  107. #define FLEXCAN_ESR_STF_ERR BIT(10)
  108. #define FLEXCAN_ESR_TX_WRN BIT(9)
  109. #define FLEXCAN_ESR_RX_WRN BIT(8)
  110. #define FLEXCAN_ESR_IDLE BIT(7)
  111. #define FLEXCAN_ESR_TXRX BIT(6)
  112. #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
  113. #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
  114. #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
  115. #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
  116. #define FLEXCAN_ESR_BOFF_INT BIT(2)
  117. #define FLEXCAN_ESR_ERR_INT BIT(1)
  118. #define FLEXCAN_ESR_WAK_INT BIT(0)
  119. #define FLEXCAN_ESR_ERR_BUS \
  120. (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
  121. FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
  122. FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
  123. #define FLEXCAN_ESR_ERR_STATE \
  124. (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
  125. #define FLEXCAN_ESR_ERR_ALL \
  126. (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
  127. #define FLEXCAN_ESR_ALL_INT \
  128. (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
  129. FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
  130. FLEXCAN_ESR_WAK_INT)
  131. /* FLEXCAN interrupt flag register (IFLAG) bits */
  132. /* Errata ERR005829 step7: Reserve first valid MB */
  133. #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
  134. #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
  135. #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
  136. #define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f)
  137. #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
  138. #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
  139. #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
  140. /* FLEXCAN message buffers */
  141. #define FLEXCAN_MB_CODE_MASK (0xf << 24)
  142. #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
  143. #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
  144. #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
  145. #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
  146. #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
  147. #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
  148. #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
  149. #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
  150. #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
  151. #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
  152. #define FLEXCAN_MB_CNT_SRR BIT(22)
  153. #define FLEXCAN_MB_CNT_IDE BIT(21)
  154. #define FLEXCAN_MB_CNT_RTR BIT(20)
  155. #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
  156. #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
  157. #define FLEXCAN_TIMEOUT_US (250)
  158. /* FLEXCAN hardware feature flags
  159. *
  160. * Below is some version info we got:
  161. * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
  162. * Filter? connected? Passive detection ception in MB
  163. * MX25 FlexCAN2 03.00.00.00 no no no no no
  164. * MX28 FlexCAN2 03.00.04.00 yes yes no no no
  165. * MX35 FlexCAN2 03.00.00.00 no no no no no
  166. * MX53 FlexCAN2 03.00.00.00 yes no no no no
  167. * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
  168. * VF610 FlexCAN3 ? no yes no yes yes?
  169. * LS1021A FlexCAN2 03.00.04.00 no yes no no yes
  170. *
  171. * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
  172. */
  173. #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
  174. #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
  175. #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
  176. #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
  177. #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
  178. #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
  179. #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
  180. #define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */
  181. /* Structure of the message buffer */
  182. struct flexcan_mb {
  183. u32 can_ctrl;
  184. u32 can_id;
  185. u32 data[];
  186. };
  187. /* Structure of the hardware registers */
  188. struct flexcan_regs {
  189. u32 mcr; /* 0x00 */
  190. u32 ctrl; /* 0x04 */
  191. u32 timer; /* 0x08 */
  192. u32 _reserved1; /* 0x0c */
  193. u32 rxgmask; /* 0x10 */
  194. u32 rx14mask; /* 0x14 */
  195. u32 rx15mask; /* 0x18 */
  196. u32 ecr; /* 0x1c */
  197. u32 esr; /* 0x20 */
  198. u32 imask2; /* 0x24 */
  199. u32 imask1; /* 0x28 */
  200. u32 iflag2; /* 0x2c */
  201. u32 iflag1; /* 0x30 */
  202. union { /* 0x34 */
  203. u32 gfwr_mx28; /* MX28, MX53 */
  204. u32 ctrl2; /* MX6, VF610 */
  205. };
  206. u32 esr2; /* 0x38 */
  207. u32 imeur; /* 0x3c */
  208. u32 lrfr; /* 0x40 */
  209. u32 crcr; /* 0x44 */
  210. u32 rxfgmask; /* 0x48 */
  211. u32 rxfir; /* 0x4c */
  212. u32 _reserved3[12]; /* 0x50 */
  213. u8 mb[2][512]; /* 0x80 */
  214. /* FIFO-mode:
  215. * MB
  216. * 0x080...0x08f 0 RX message buffer
  217. * 0x090...0x0df 1-5 reserverd
  218. * 0x0e0...0x0ff 6-7 8 entry ID table
  219. * (mx25, mx28, mx35, mx53)
  220. * 0x0e0...0x2df 6-7..37 8..128 entry ID table
  221. * size conf'ed via ctrl2::RFFN
  222. * (mx6, vf610)
  223. */
  224. u32 _reserved4[256]; /* 0x480 */
  225. u32 rximr[64]; /* 0x880 */
  226. u32 _reserved5[24]; /* 0x980 */
  227. u32 gfwr_mx6; /* 0x9e0 - MX6 */
  228. u32 _reserved6[63]; /* 0x9e4 */
  229. u32 mecr; /* 0xae0 */
  230. u32 erriar; /* 0xae4 */
  231. u32 erridpr; /* 0xae8 */
  232. u32 errippr; /* 0xaec */
  233. u32 rerrar; /* 0xaf0 */
  234. u32 rerrdr; /* 0xaf4 */
  235. u32 rerrsynr; /* 0xaf8 */
  236. u32 errsr; /* 0xafc */
  237. };
  238. struct flexcan_devtype_data {
  239. u32 quirks; /* quirks needed for different IP cores */
  240. };
  241. struct flexcan_stop_mode {
  242. struct regmap *gpr;
  243. u8 req_gpr;
  244. u8 req_bit;
  245. u8 ack_gpr;
  246. u8 ack_bit;
  247. };
  248. struct flexcan_priv {
  249. struct can_priv can;
  250. struct can_rx_offload offload;
  251. struct device *dev;
  252. struct flexcan_regs __iomem *regs;
  253. struct flexcan_mb __iomem *tx_mb;
  254. struct flexcan_mb __iomem *tx_mb_reserved;
  255. u8 tx_mb_idx;
  256. u8 mb_count;
  257. u8 mb_size;
  258. u8 clk_src; /* clock source of CAN Protocol Engine */
  259. u32 reg_ctrl_default;
  260. u32 reg_imask1_default;
  261. u32 reg_imask2_default;
  262. struct clk *clk_ipg;
  263. struct clk *clk_per;
  264. const struct flexcan_devtype_data *devtype_data;
  265. struct regulator *reg_xceiver;
  266. struct flexcan_stop_mode stm;
  267. /* Read and Write APIs */
  268. u32 (*read)(void __iomem *addr);
  269. void (*write)(u32 val, void __iomem *addr);
  270. };
  271. static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
  272. .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
  273. FLEXCAN_QUIRK_BROKEN_PERR_STATE |
  274. FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
  275. };
  276. static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
  277. .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
  278. FLEXCAN_QUIRK_BROKEN_PERR_STATE,
  279. };
  280. static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
  281. .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
  282. };
  283. static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
  284. .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
  285. FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
  286. FLEXCAN_QUIRK_SETUP_STOP_MODE,
  287. };
  288. static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
  289. .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
  290. FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
  291. FLEXCAN_QUIRK_BROKEN_PERR_STATE,
  292. };
  293. static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
  294. .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
  295. FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
  296. FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
  297. };
  298. static const struct can_bittiming_const flexcan_bittiming_const = {
  299. .name = DRV_NAME,
  300. .tseg1_min = 4,
  301. .tseg1_max = 16,
  302. .tseg2_min = 2,
  303. .tseg2_max = 8,
  304. .sjw_max = 4,
  305. .brp_min = 1,
  306. .brp_max = 256,
  307. .brp_inc = 1,
  308. };
  309. /* FlexCAN module is essentially modelled as a little-endian IP in most
  310. * SoCs, i.e the registers as well as the message buffer areas are
  311. * implemented in a little-endian fashion.
  312. *
  313. * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
  314. * module in a big-endian fashion (i.e the registers as well as the
  315. * message buffer areas are implemented in a big-endian way).
  316. *
  317. * In addition, the FlexCAN module can be found on SoCs having ARM or
  318. * PPC cores. So, we need to abstract off the register read/write
  319. * functions, ensuring that these cater to all the combinations of module
  320. * endianness and underlying CPU endianness.
  321. */
  322. static inline u32 flexcan_read_be(void __iomem *addr)
  323. {
  324. return ioread32be(addr);
  325. }
  326. static inline void flexcan_write_be(u32 val, void __iomem *addr)
  327. {
  328. iowrite32be(val, addr);
  329. }
  330. static inline u32 flexcan_read_le(void __iomem *addr)
  331. {
  332. return ioread32(addr);
  333. }
  334. static inline void flexcan_write_le(u32 val, void __iomem *addr)
  335. {
  336. iowrite32(val, addr);
  337. }
  338. static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
  339. u8 mb_index)
  340. {
  341. u8 bank_size;
  342. bool bank;
  343. if (WARN_ON(mb_index >= priv->mb_count))
  344. return NULL;
  345. bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
  346. bank = mb_index >= bank_size;
  347. if (bank)
  348. mb_index -= bank_size;
  349. return (struct flexcan_mb __iomem *)
  350. (&priv->regs->mb[bank][priv->mb_size * mb_index]);
  351. }
  352. static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
  353. {
  354. struct flexcan_regs __iomem *regs = priv->regs;
  355. u32 reg_mcr;
  356. reg_mcr = priv->read(&regs->mcr);
  357. if (enable)
  358. reg_mcr |= FLEXCAN_MCR_WAK_MSK;
  359. else
  360. reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
  361. priv->write(reg_mcr, &regs->mcr);
  362. }
  363. static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
  364. {
  365. struct flexcan_regs __iomem *regs = priv->regs;
  366. unsigned int ackval;
  367. u32 reg_mcr;
  368. reg_mcr = priv->read(&regs->mcr);
  369. reg_mcr |= FLEXCAN_MCR_SLF_WAK;
  370. priv->write(reg_mcr, &regs->mcr);
  371. /* enable stop request */
  372. regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
  373. 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
  374. /* get stop acknowledgment */
  375. if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
  376. ackval, ackval & (1 << priv->stm.ack_bit),
  377. 0, FLEXCAN_TIMEOUT_US))
  378. return -ETIMEDOUT;
  379. return 0;
  380. }
  381. static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
  382. {
  383. struct flexcan_regs __iomem *regs = priv->regs;
  384. unsigned int ackval;
  385. u32 reg_mcr;
  386. /* remove stop request */
  387. regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
  388. 1 << priv->stm.req_bit, 0);
  389. /* get stop acknowledgment */
  390. if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
  391. ackval, !(ackval & (1 << priv->stm.ack_bit)),
  392. 0, FLEXCAN_TIMEOUT_US))
  393. return -ETIMEDOUT;
  394. reg_mcr = priv->read(&regs->mcr);
  395. reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
  396. priv->write(reg_mcr, &regs->mcr);
  397. return 0;
  398. }
  399. static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
  400. {
  401. struct flexcan_regs __iomem *regs = priv->regs;
  402. u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
  403. priv->write(reg_ctrl, &regs->ctrl);
  404. }
  405. static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
  406. {
  407. struct flexcan_regs __iomem *regs = priv->regs;
  408. u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
  409. priv->write(reg_ctrl, &regs->ctrl);
  410. }
  411. static int flexcan_clks_enable(const struct flexcan_priv *priv)
  412. {
  413. int err;
  414. err = clk_prepare_enable(priv->clk_ipg);
  415. if (err)
  416. return err;
  417. err = clk_prepare_enable(priv->clk_per);
  418. if (err)
  419. clk_disable_unprepare(priv->clk_ipg);
  420. return err;
  421. }
  422. static void flexcan_clks_disable(const struct flexcan_priv *priv)
  423. {
  424. clk_disable_unprepare(priv->clk_per);
  425. clk_disable_unprepare(priv->clk_ipg);
  426. }
  427. static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
  428. {
  429. if (!priv->reg_xceiver)
  430. return 0;
  431. return regulator_enable(priv->reg_xceiver);
  432. }
  433. static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
  434. {
  435. if (!priv->reg_xceiver)
  436. return 0;
  437. return regulator_disable(priv->reg_xceiver);
  438. }
  439. static int flexcan_chip_enable(struct flexcan_priv *priv)
  440. {
  441. struct flexcan_regs __iomem *regs = priv->regs;
  442. unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  443. u32 reg;
  444. reg = priv->read(&regs->mcr);
  445. reg &= ~FLEXCAN_MCR_MDIS;
  446. priv->write(reg, &regs->mcr);
  447. while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
  448. udelay(10);
  449. if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
  450. return -ETIMEDOUT;
  451. return 0;
  452. }
  453. static int flexcan_chip_disable(struct flexcan_priv *priv)
  454. {
  455. struct flexcan_regs __iomem *regs = priv->regs;
  456. unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  457. u32 reg;
  458. reg = priv->read(&regs->mcr);
  459. reg |= FLEXCAN_MCR_MDIS;
  460. priv->write(reg, &regs->mcr);
  461. while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
  462. udelay(10);
  463. if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
  464. return -ETIMEDOUT;
  465. return 0;
  466. }
  467. static int flexcan_chip_freeze(struct flexcan_priv *priv)
  468. {
  469. struct flexcan_regs __iomem *regs = priv->regs;
  470. unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
  471. u32 reg;
  472. reg = priv->read(&regs->mcr);
  473. reg |= FLEXCAN_MCR_HALT;
  474. priv->write(reg, &regs->mcr);
  475. while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
  476. udelay(100);
  477. if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
  478. return -ETIMEDOUT;
  479. return 0;
  480. }
  481. static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
  482. {
  483. struct flexcan_regs __iomem *regs = priv->regs;
  484. unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  485. u32 reg;
  486. reg = priv->read(&regs->mcr);
  487. reg &= ~FLEXCAN_MCR_HALT;
  488. priv->write(reg, &regs->mcr);
  489. while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
  490. udelay(10);
  491. if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
  492. return -ETIMEDOUT;
  493. return 0;
  494. }
  495. static int flexcan_chip_softreset(struct flexcan_priv *priv)
  496. {
  497. struct flexcan_regs __iomem *regs = priv->regs;
  498. unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
  499. priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
  500. while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
  501. udelay(10);
  502. if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
  503. return -ETIMEDOUT;
  504. return 0;
  505. }
  506. static int __flexcan_get_berr_counter(const struct net_device *dev,
  507. struct can_berr_counter *bec)
  508. {
  509. const struct flexcan_priv *priv = netdev_priv(dev);
  510. struct flexcan_regs __iomem *regs = priv->regs;
  511. u32 reg = priv->read(&regs->ecr);
  512. bec->txerr = (reg >> 0) & 0xff;
  513. bec->rxerr = (reg >> 8) & 0xff;
  514. return 0;
  515. }
  516. static int flexcan_get_berr_counter(const struct net_device *dev,
  517. struct can_berr_counter *bec)
  518. {
  519. const struct flexcan_priv *priv = netdev_priv(dev);
  520. int err;
  521. err = pm_runtime_get_sync(priv->dev);
  522. if (err < 0)
  523. return err;
  524. err = __flexcan_get_berr_counter(dev, bec);
  525. pm_runtime_put(priv->dev);
  526. return err;
  527. }
  528. static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
  529. {
  530. const struct flexcan_priv *priv = netdev_priv(dev);
  531. struct can_frame *cf = (struct can_frame *)skb->data;
  532. u32 can_id;
  533. u32 data;
  534. u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
  535. int i;
  536. if (can_dropped_invalid_skb(dev, skb))
  537. return NETDEV_TX_OK;
  538. netif_stop_queue(dev);
  539. if (cf->can_id & CAN_EFF_FLAG) {
  540. can_id = cf->can_id & CAN_EFF_MASK;
  541. ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
  542. } else {
  543. can_id = (cf->can_id & CAN_SFF_MASK) << 18;
  544. }
  545. if (cf->can_id & CAN_RTR_FLAG)
  546. ctrl |= FLEXCAN_MB_CNT_RTR;
  547. for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
  548. data = be32_to_cpup((__be32 *)&cf->data[i]);
  549. priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
  550. }
  551. can_put_echo_skb(skb, dev, 0);
  552. priv->write(can_id, &priv->tx_mb->can_id);
  553. priv->write(ctrl, &priv->tx_mb->can_ctrl);
  554. /* Errata ERR005829 step8:
  555. * Write twice INACTIVE(0x8) code to first MB.
  556. */
  557. priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
  558. &priv->tx_mb_reserved->can_ctrl);
  559. priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
  560. &priv->tx_mb_reserved->can_ctrl);
  561. return NETDEV_TX_OK;
  562. }
  563. static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
  564. {
  565. struct flexcan_priv *priv = netdev_priv(dev);
  566. struct flexcan_regs __iomem *regs = priv->regs;
  567. struct sk_buff *skb;
  568. struct can_frame *cf;
  569. bool rx_errors = false, tx_errors = false;
  570. u32 timestamp;
  571. timestamp = priv->read(&regs->timer) << 16;
  572. skb = alloc_can_err_skb(dev, &cf);
  573. if (unlikely(!skb))
  574. return;
  575. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  576. if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
  577. netdev_dbg(dev, "BIT1_ERR irq\n");
  578. cf->data[2] |= CAN_ERR_PROT_BIT1;
  579. tx_errors = true;
  580. }
  581. if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
  582. netdev_dbg(dev, "BIT0_ERR irq\n");
  583. cf->data[2] |= CAN_ERR_PROT_BIT0;
  584. tx_errors = true;
  585. }
  586. if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
  587. netdev_dbg(dev, "ACK_ERR irq\n");
  588. cf->can_id |= CAN_ERR_ACK;
  589. cf->data[3] = CAN_ERR_PROT_LOC_ACK;
  590. tx_errors = true;
  591. }
  592. if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
  593. netdev_dbg(dev, "CRC_ERR irq\n");
  594. cf->data[2] |= CAN_ERR_PROT_BIT;
  595. cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
  596. rx_errors = true;
  597. }
  598. if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
  599. netdev_dbg(dev, "FRM_ERR irq\n");
  600. cf->data[2] |= CAN_ERR_PROT_FORM;
  601. rx_errors = true;
  602. }
  603. if (reg_esr & FLEXCAN_ESR_STF_ERR) {
  604. netdev_dbg(dev, "STF_ERR irq\n");
  605. cf->data[2] |= CAN_ERR_PROT_STUFF;
  606. rx_errors = true;
  607. }
  608. priv->can.can_stats.bus_error++;
  609. if (rx_errors)
  610. dev->stats.rx_errors++;
  611. if (tx_errors)
  612. dev->stats.tx_errors++;
  613. can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
  614. }
  615. static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
  616. {
  617. struct flexcan_priv *priv = netdev_priv(dev);
  618. struct flexcan_regs __iomem *regs = priv->regs;
  619. struct sk_buff *skb;
  620. struct can_frame *cf;
  621. enum can_state new_state, rx_state, tx_state;
  622. int flt;
  623. struct can_berr_counter bec;
  624. u32 timestamp;
  625. timestamp = priv->read(&regs->timer) << 16;
  626. flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
  627. if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
  628. tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
  629. CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
  630. rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
  631. CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
  632. new_state = max(tx_state, rx_state);
  633. } else {
  634. __flexcan_get_berr_counter(dev, &bec);
  635. new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
  636. CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
  637. rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
  638. tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
  639. }
  640. /* state hasn't changed */
  641. if (likely(new_state == priv->can.state))
  642. return;
  643. skb = alloc_can_err_skb(dev, &cf);
  644. if (unlikely(!skb))
  645. return;
  646. can_change_state(dev, cf, tx_state, rx_state);
  647. if (unlikely(new_state == CAN_STATE_BUS_OFF))
  648. can_bus_off(dev);
  649. can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
  650. }
  651. static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
  652. {
  653. return container_of(offload, struct flexcan_priv, offload);
  654. }
  655. static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
  656. struct can_frame *cf,
  657. u32 *timestamp, unsigned int n)
  658. {
  659. struct flexcan_priv *priv = rx_offload_to_priv(offload);
  660. struct flexcan_regs __iomem *regs = priv->regs;
  661. struct flexcan_mb __iomem *mb;
  662. u32 reg_ctrl, reg_id, reg_iflag1;
  663. int i;
  664. mb = flexcan_get_mb(priv, n);
  665. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
  666. u32 code;
  667. do {
  668. reg_ctrl = priv->read(&mb->can_ctrl);
  669. } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
  670. /* is this MB empty? */
  671. code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
  672. if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
  673. (code != FLEXCAN_MB_CODE_RX_OVERRUN))
  674. return 0;
  675. if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
  676. /* This MB was overrun, we lost data */
  677. offload->dev->stats.rx_over_errors++;
  678. offload->dev->stats.rx_errors++;
  679. }
  680. } else {
  681. reg_iflag1 = priv->read(&regs->iflag1);
  682. if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
  683. return 0;
  684. reg_ctrl = priv->read(&mb->can_ctrl);
  685. }
  686. /* increase timstamp to full 32 bit */
  687. *timestamp = reg_ctrl << 16;
  688. reg_id = priv->read(&mb->can_id);
  689. if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
  690. cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
  691. else
  692. cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
  693. if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
  694. cf->can_id |= CAN_RTR_FLAG;
  695. cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
  696. for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
  697. __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
  698. *(__be32 *)(cf->data + i) = data;
  699. }
  700. /* mark as read */
  701. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
  702. /* Clear IRQ */
  703. if (n < 32)
  704. priv->write(BIT(n), &regs->iflag1);
  705. else
  706. priv->write(BIT(n - 32), &regs->iflag2);
  707. } else {
  708. priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
  709. }
  710. /* Read the Free Running Timer. It is optional but recommended
  711. * to unlock Mailbox as soon as possible and make it available
  712. * for reception.
  713. */
  714. priv->read(&regs->timer);
  715. return 1;
  716. }
  717. static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
  718. {
  719. struct flexcan_regs __iomem *regs = priv->regs;
  720. u32 iflag1, iflag2;
  721. iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
  722. ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
  723. iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
  724. return (u64)iflag2 << 32 | iflag1;
  725. }
  726. static irqreturn_t flexcan_irq(int irq, void *dev_id)
  727. {
  728. struct net_device *dev = dev_id;
  729. struct net_device_stats *stats = &dev->stats;
  730. struct flexcan_priv *priv = netdev_priv(dev);
  731. struct flexcan_regs __iomem *regs = priv->regs;
  732. irqreturn_t handled = IRQ_NONE;
  733. u32 reg_iflag2, reg_esr;
  734. enum can_state last_state = priv->can.state;
  735. /* reception interrupt */
  736. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
  737. u64 reg_iflag;
  738. int ret;
  739. while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
  740. handled = IRQ_HANDLED;
  741. ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
  742. reg_iflag);
  743. if (!ret)
  744. break;
  745. }
  746. } else {
  747. u32 reg_iflag1;
  748. reg_iflag1 = priv->read(&regs->iflag1);
  749. if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
  750. handled = IRQ_HANDLED;
  751. can_rx_offload_irq_offload_fifo(&priv->offload);
  752. }
  753. /* FIFO overflow interrupt */
  754. if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
  755. handled = IRQ_HANDLED;
  756. priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
  757. &regs->iflag1);
  758. dev->stats.rx_over_errors++;
  759. dev->stats.rx_errors++;
  760. }
  761. }
  762. reg_iflag2 = priv->read(&regs->iflag2);
  763. /* transmission complete interrupt */
  764. if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
  765. u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
  766. handled = IRQ_HANDLED;
  767. stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
  768. 0, reg_ctrl << 16);
  769. stats->tx_packets++;
  770. can_led_event(dev, CAN_LED_EVENT_TX);
  771. /* after sending a RTR frame MB is in RX mode */
  772. priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
  773. &priv->tx_mb->can_ctrl);
  774. priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
  775. netif_wake_queue(dev);
  776. }
  777. reg_esr = priv->read(&regs->esr);
  778. /* ACK all bus error and state change IRQ sources */
  779. if (reg_esr & FLEXCAN_ESR_ALL_INT) {
  780. handled = IRQ_HANDLED;
  781. priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
  782. }
  783. /* state change interrupt or broken error state quirk fix is enabled */
  784. if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
  785. (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
  786. FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
  787. flexcan_irq_state(dev, reg_esr);
  788. /* bus error IRQ - handle if bus error reporting is activated */
  789. if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
  790. (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
  791. flexcan_irq_bus_err(dev, reg_esr);
  792. /* availability of error interrupt among state transitions in case
  793. * bus error reporting is de-activated and
  794. * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
  795. * +--------------------------------------------------------------+
  796. * | +----------------------------------------------+ [stopped / |
  797. * | | | sleeping] -+
  798. * +-+-> active <-> warning <-> passive -> bus off -+
  799. * ___________^^^^^^^^^^^^_______________________________
  800. * disabled(1) enabled disabled
  801. *
  802. * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
  803. */
  804. if ((last_state != priv->can.state) &&
  805. (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
  806. !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
  807. switch (priv->can.state) {
  808. case CAN_STATE_ERROR_ACTIVE:
  809. if (priv->devtype_data->quirks &
  810. FLEXCAN_QUIRK_BROKEN_WERR_STATE)
  811. flexcan_error_irq_enable(priv);
  812. else
  813. flexcan_error_irq_disable(priv);
  814. break;
  815. case CAN_STATE_ERROR_WARNING:
  816. flexcan_error_irq_enable(priv);
  817. break;
  818. case CAN_STATE_ERROR_PASSIVE:
  819. case CAN_STATE_BUS_OFF:
  820. flexcan_error_irq_disable(priv);
  821. break;
  822. default:
  823. break;
  824. }
  825. }
  826. return handled;
  827. }
  828. static void flexcan_set_bittiming(struct net_device *dev)
  829. {
  830. const struct flexcan_priv *priv = netdev_priv(dev);
  831. const struct can_bittiming *bt = &priv->can.bittiming;
  832. struct flexcan_regs __iomem *regs = priv->regs;
  833. u32 reg;
  834. reg = priv->read(&regs->ctrl);
  835. reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
  836. FLEXCAN_CTRL_RJW(0x3) |
  837. FLEXCAN_CTRL_PSEG1(0x7) |
  838. FLEXCAN_CTRL_PSEG2(0x7) |
  839. FLEXCAN_CTRL_PROPSEG(0x7) |
  840. FLEXCAN_CTRL_LPB |
  841. FLEXCAN_CTRL_SMP |
  842. FLEXCAN_CTRL_LOM);
  843. reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
  844. FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
  845. FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
  846. FLEXCAN_CTRL_RJW(bt->sjw - 1) |
  847. FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
  848. if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
  849. reg |= FLEXCAN_CTRL_LPB;
  850. if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
  851. reg |= FLEXCAN_CTRL_LOM;
  852. if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  853. reg |= FLEXCAN_CTRL_SMP;
  854. netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
  855. priv->write(reg, &regs->ctrl);
  856. /* print chip status */
  857. netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
  858. priv->read(&regs->mcr), priv->read(&regs->ctrl));
  859. }
  860. /* flexcan_chip_start
  861. *
  862. * this functions is entered with clocks enabled
  863. *
  864. */
  865. static int flexcan_chip_start(struct net_device *dev)
  866. {
  867. struct flexcan_priv *priv = netdev_priv(dev);
  868. struct flexcan_regs __iomem *regs = priv->regs;
  869. u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
  870. int err, i;
  871. struct flexcan_mb __iomem *mb;
  872. /* enable module */
  873. err = flexcan_chip_enable(priv);
  874. if (err)
  875. return err;
  876. /* soft reset */
  877. err = flexcan_chip_softreset(priv);
  878. if (err)
  879. goto out_chip_disable;
  880. flexcan_set_bittiming(dev);
  881. /* MCR
  882. *
  883. * enable freeze
  884. * halt now
  885. * only supervisor access
  886. * enable warning int
  887. * enable individual RX masking
  888. * choose format C
  889. * set max mailbox number
  890. */
  891. reg_mcr = priv->read(&regs->mcr);
  892. reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
  893. reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
  894. FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
  895. FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
  896. /* MCR
  897. *
  898. * FIFO:
  899. * - disable for timestamp mode
  900. * - enable for FIFO mode
  901. */
  902. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
  903. reg_mcr &= ~FLEXCAN_MCR_FEN;
  904. else
  905. reg_mcr |= FLEXCAN_MCR_FEN;
  906. /* MCR
  907. *
  908. * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
  909. * asserted because this will impede the self reception
  910. * of a transmitted message. This is not documented in
  911. * earlier versions of flexcan block guide.
  912. *
  913. * Self Reception:
  914. * - enable Self Reception for loopback mode
  915. * (by clearing "Self Reception Disable" bit)
  916. * - disable for normal operation
  917. */
  918. if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
  919. reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
  920. else
  921. reg_mcr |= FLEXCAN_MCR_SRX_DIS;
  922. netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
  923. priv->write(reg_mcr, &regs->mcr);
  924. /* CTRL
  925. *
  926. * disable timer sync feature
  927. *
  928. * disable auto busoff recovery
  929. * transmit lowest buffer first
  930. *
  931. * enable tx and rx warning interrupt
  932. * enable bus off interrupt
  933. * (== FLEXCAN_CTRL_ERR_STATE)
  934. */
  935. reg_ctrl = priv->read(&regs->ctrl);
  936. reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
  937. reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
  938. FLEXCAN_CTRL_ERR_STATE;
  939. /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
  940. * on most Flexcan cores, too. Otherwise we don't get
  941. * any error warning or passive interrupts.
  942. */
  943. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
  944. priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
  945. reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
  946. else
  947. reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
  948. /* save for later use */
  949. priv->reg_ctrl_default = reg_ctrl;
  950. /* leave interrupts disabled for now */
  951. reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
  952. netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
  953. priv->write(reg_ctrl, &regs->ctrl);
  954. if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
  955. reg_ctrl2 = priv->read(&regs->ctrl2);
  956. reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
  957. priv->write(reg_ctrl2, &regs->ctrl2);
  958. }
  959. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
  960. for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
  961. mb = flexcan_get_mb(priv, i);
  962. priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
  963. &mb->can_ctrl);
  964. }
  965. } else {
  966. /* clear and invalidate unused mailboxes first */
  967. for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
  968. mb = flexcan_get_mb(priv, i);
  969. priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
  970. &mb->can_ctrl);
  971. }
  972. }
  973. /* Errata ERR005829: mark first TX mailbox as INACTIVE */
  974. priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
  975. &priv->tx_mb_reserved->can_ctrl);
  976. /* mark TX mailbox as INACTIVE */
  977. priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
  978. &priv->tx_mb->can_ctrl);
  979. /* acceptance mask/acceptance code (accept everything) */
  980. priv->write(0x0, &regs->rxgmask);
  981. priv->write(0x0, &regs->rx14mask);
  982. priv->write(0x0, &regs->rx15mask);
  983. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
  984. priv->write(0x0, &regs->rxfgmask);
  985. /* clear acceptance filters */
  986. for (i = 0; i < priv->mb_count; i++)
  987. priv->write(0, &regs->rximr[i]);
  988. /* On Vybrid, disable memory error detection interrupts
  989. * and freeze mode.
  990. * This also works around errata e5295 which generates
  991. * false positive memory errors and put the device in
  992. * freeze mode.
  993. */
  994. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
  995. /* Follow the protocol as described in "Detection
  996. * and Correction of Memory Errors" to write to
  997. * MECR register
  998. */
  999. reg_ctrl2 = priv->read(&regs->ctrl2);
  1000. reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
  1001. priv->write(reg_ctrl2, &regs->ctrl2);
  1002. reg_mecr = priv->read(&regs->mecr);
  1003. reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
  1004. priv->write(reg_mecr, &regs->mecr);
  1005. reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
  1006. FLEXCAN_MECR_FANCEI_MSK);
  1007. priv->write(reg_mecr, &regs->mecr);
  1008. }
  1009. err = flexcan_transceiver_enable(priv);
  1010. if (err)
  1011. goto out_chip_disable;
  1012. /* synchronize with the can bus */
  1013. err = flexcan_chip_unfreeze(priv);
  1014. if (err)
  1015. goto out_transceiver_disable;
  1016. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  1017. /* enable interrupts atomically */
  1018. disable_irq(dev->irq);
  1019. priv->write(priv->reg_ctrl_default, &regs->ctrl);
  1020. priv->write(priv->reg_imask1_default, &regs->imask1);
  1021. priv->write(priv->reg_imask2_default, &regs->imask2);
  1022. enable_irq(dev->irq);
  1023. /* print chip status */
  1024. netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
  1025. priv->read(&regs->mcr), priv->read(&regs->ctrl));
  1026. return 0;
  1027. out_transceiver_disable:
  1028. flexcan_transceiver_disable(priv);
  1029. out_chip_disable:
  1030. flexcan_chip_disable(priv);
  1031. return err;
  1032. }
  1033. /* flexcan_chip_stop
  1034. *
  1035. * this functions is entered with clocks enabled
  1036. */
  1037. static void flexcan_chip_stop(struct net_device *dev)
  1038. {
  1039. struct flexcan_priv *priv = netdev_priv(dev);
  1040. struct flexcan_regs __iomem *regs = priv->regs;
  1041. /* freeze + disable module */
  1042. flexcan_chip_freeze(priv);
  1043. flexcan_chip_disable(priv);
  1044. /* Disable all interrupts */
  1045. priv->write(0, &regs->imask2);
  1046. priv->write(0, &regs->imask1);
  1047. priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
  1048. &regs->ctrl);
  1049. flexcan_transceiver_disable(priv);
  1050. priv->can.state = CAN_STATE_STOPPED;
  1051. }
  1052. static int flexcan_open(struct net_device *dev)
  1053. {
  1054. struct flexcan_priv *priv = netdev_priv(dev);
  1055. int err;
  1056. err = pm_runtime_get_sync(priv->dev);
  1057. if (err < 0)
  1058. return err;
  1059. err = open_candev(dev);
  1060. if (err)
  1061. goto out_runtime_put;
  1062. err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
  1063. if (err)
  1064. goto out_close;
  1065. priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
  1066. priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
  1067. (sizeof(priv->regs->mb[1]) / priv->mb_size);
  1068. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
  1069. priv->tx_mb_reserved =
  1070. flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
  1071. else
  1072. priv->tx_mb_reserved =
  1073. flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
  1074. priv->tx_mb_idx = priv->mb_count - 1;
  1075. priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
  1076. priv->reg_imask1_default = 0;
  1077. priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
  1078. priv->offload.mailbox_read = flexcan_mailbox_read;
  1079. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
  1080. u64 imask;
  1081. priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
  1082. priv->offload.mb_last = priv->mb_count - 2;
  1083. imask = GENMASK_ULL(priv->offload.mb_last,
  1084. priv->offload.mb_first);
  1085. priv->reg_imask1_default |= imask;
  1086. priv->reg_imask2_default |= imask >> 32;
  1087. err = can_rx_offload_add_timestamp(dev, &priv->offload);
  1088. } else {
  1089. priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
  1090. FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
  1091. err = can_rx_offload_add_fifo(dev, &priv->offload,
  1092. FLEXCAN_NAPI_WEIGHT);
  1093. }
  1094. if (err)
  1095. goto out_free_irq;
  1096. /* start chip and queuing */
  1097. err = flexcan_chip_start(dev);
  1098. if (err)
  1099. goto out_offload_del;
  1100. can_led_event(dev, CAN_LED_EVENT_OPEN);
  1101. can_rx_offload_enable(&priv->offload);
  1102. netif_start_queue(dev);
  1103. return 0;
  1104. out_offload_del:
  1105. can_rx_offload_del(&priv->offload);
  1106. out_free_irq:
  1107. free_irq(dev->irq, dev);
  1108. out_close:
  1109. close_candev(dev);
  1110. out_runtime_put:
  1111. pm_runtime_put(priv->dev);
  1112. return err;
  1113. }
  1114. static int flexcan_close(struct net_device *dev)
  1115. {
  1116. struct flexcan_priv *priv = netdev_priv(dev);
  1117. netif_stop_queue(dev);
  1118. can_rx_offload_disable(&priv->offload);
  1119. flexcan_chip_stop(dev);
  1120. can_rx_offload_del(&priv->offload);
  1121. free_irq(dev->irq, dev);
  1122. close_candev(dev);
  1123. pm_runtime_put(priv->dev);
  1124. can_led_event(dev, CAN_LED_EVENT_STOP);
  1125. return 0;
  1126. }
  1127. static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
  1128. {
  1129. int err;
  1130. switch (mode) {
  1131. case CAN_MODE_START:
  1132. err = flexcan_chip_start(dev);
  1133. if (err)
  1134. return err;
  1135. netif_wake_queue(dev);
  1136. break;
  1137. default:
  1138. return -EOPNOTSUPP;
  1139. }
  1140. return 0;
  1141. }
  1142. static const struct net_device_ops flexcan_netdev_ops = {
  1143. .ndo_open = flexcan_open,
  1144. .ndo_stop = flexcan_close,
  1145. .ndo_start_xmit = flexcan_start_xmit,
  1146. .ndo_change_mtu = can_change_mtu,
  1147. };
  1148. static int register_flexcandev(struct net_device *dev)
  1149. {
  1150. struct flexcan_priv *priv = netdev_priv(dev);
  1151. struct flexcan_regs __iomem *regs = priv->regs;
  1152. u32 reg, err;
  1153. err = flexcan_clks_enable(priv);
  1154. if (err)
  1155. return err;
  1156. /* select "bus clock", chip must be disabled */
  1157. err = flexcan_chip_disable(priv);
  1158. if (err)
  1159. goto out_clks_disable;
  1160. reg = priv->read(&regs->ctrl);
  1161. if (priv->clk_src)
  1162. reg |= FLEXCAN_CTRL_CLK_SRC;
  1163. else
  1164. reg &= ~FLEXCAN_CTRL_CLK_SRC;
  1165. priv->write(reg, &regs->ctrl);
  1166. err = flexcan_chip_enable(priv);
  1167. if (err)
  1168. goto out_chip_disable;
  1169. /* set freeze, halt and activate FIFO, restrict register access */
  1170. reg = priv->read(&regs->mcr);
  1171. reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
  1172. FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
  1173. priv->write(reg, &regs->mcr);
  1174. /* Currently we only support newer versions of this core
  1175. * featuring a RX hardware FIFO (although this driver doesn't
  1176. * make use of it on some cores). Older cores, found on some
  1177. * Coldfire derivates are not tested.
  1178. */
  1179. reg = priv->read(&regs->mcr);
  1180. if (!(reg & FLEXCAN_MCR_FEN)) {
  1181. netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
  1182. err = -ENODEV;
  1183. goto out_chip_disable;
  1184. }
  1185. err = register_candev(dev);
  1186. if (err)
  1187. goto out_chip_disable;
  1188. /* Disable core and let pm_runtime_put() disable the clocks.
  1189. * If CONFIG_PM is not enabled, the clocks will stay powered.
  1190. */
  1191. flexcan_chip_disable(priv);
  1192. pm_runtime_put(priv->dev);
  1193. return 0;
  1194. out_chip_disable:
  1195. flexcan_chip_disable(priv);
  1196. out_clks_disable:
  1197. flexcan_clks_disable(priv);
  1198. return err;
  1199. }
  1200. static void unregister_flexcandev(struct net_device *dev)
  1201. {
  1202. unregister_candev(dev);
  1203. }
  1204. static int flexcan_setup_stop_mode(struct platform_device *pdev)
  1205. {
  1206. struct net_device *dev = platform_get_drvdata(pdev);
  1207. struct device_node *np = pdev->dev.of_node;
  1208. struct device_node *gpr_np;
  1209. struct flexcan_priv *priv;
  1210. phandle phandle;
  1211. u32 out_val[5];
  1212. int ret;
  1213. if (!np)
  1214. return -EINVAL;
  1215. /* stop mode property format is:
  1216. * <&gpr req_gpr req_bit ack_gpr ack_bit>.
  1217. */
  1218. ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
  1219. ARRAY_SIZE(out_val));
  1220. if (ret) {
  1221. dev_dbg(&pdev->dev, "no stop-mode property\n");
  1222. return ret;
  1223. }
  1224. phandle = *out_val;
  1225. gpr_np = of_find_node_by_phandle(phandle);
  1226. if (!gpr_np) {
  1227. dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
  1228. return -ENODEV;
  1229. }
  1230. priv = netdev_priv(dev);
  1231. priv->stm.gpr = syscon_node_to_regmap(gpr_np);
  1232. if (IS_ERR(priv->stm.gpr)) {
  1233. dev_dbg(&pdev->dev, "could not find gpr regmap\n");
  1234. ret = PTR_ERR(priv->stm.gpr);
  1235. goto out_put_node;
  1236. }
  1237. priv->stm.req_gpr = out_val[1];
  1238. priv->stm.req_bit = out_val[2];
  1239. priv->stm.ack_gpr = out_val[3];
  1240. priv->stm.ack_bit = out_val[4];
  1241. dev_dbg(&pdev->dev,
  1242. "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
  1243. gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
  1244. priv->stm.ack_gpr, priv->stm.ack_bit);
  1245. device_set_wakeup_capable(&pdev->dev, true);
  1246. if (of_property_read_bool(np, "wakeup-source"))
  1247. device_set_wakeup_enable(&pdev->dev, true);
  1248. return 0;
  1249. out_put_node:
  1250. of_node_put(gpr_np);
  1251. return ret;
  1252. }
  1253. static const struct of_device_id flexcan_of_match[] = {
  1254. { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
  1255. { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
  1256. { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
  1257. { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
  1258. { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
  1259. { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
  1260. { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
  1261. { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
  1262. { /* sentinel */ },
  1263. };
  1264. MODULE_DEVICE_TABLE(of, flexcan_of_match);
  1265. static const struct platform_device_id flexcan_id_table[] = {
  1266. { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
  1267. { /* sentinel */ },
  1268. };
  1269. MODULE_DEVICE_TABLE(platform, flexcan_id_table);
  1270. static int flexcan_probe(struct platform_device *pdev)
  1271. {
  1272. const struct of_device_id *of_id;
  1273. const struct flexcan_devtype_data *devtype_data;
  1274. struct net_device *dev;
  1275. struct flexcan_priv *priv;
  1276. struct regulator *reg_xceiver;
  1277. struct resource *mem;
  1278. struct clk *clk_ipg = NULL, *clk_per = NULL;
  1279. struct flexcan_regs __iomem *regs;
  1280. int err, irq;
  1281. u8 clk_src = 1;
  1282. u32 clock_freq = 0;
  1283. reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
  1284. if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
  1285. return -EPROBE_DEFER;
  1286. else if (IS_ERR(reg_xceiver))
  1287. reg_xceiver = NULL;
  1288. if (pdev->dev.of_node) {
  1289. of_property_read_u32(pdev->dev.of_node,
  1290. "clock-frequency", &clock_freq);
  1291. of_property_read_u8(pdev->dev.of_node,
  1292. "fsl,clk-source", &clk_src);
  1293. }
  1294. if (!clock_freq) {
  1295. clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  1296. if (IS_ERR(clk_ipg)) {
  1297. dev_err(&pdev->dev, "no ipg clock defined\n");
  1298. return PTR_ERR(clk_ipg);
  1299. }
  1300. clk_per = devm_clk_get(&pdev->dev, "per");
  1301. if (IS_ERR(clk_per)) {
  1302. dev_err(&pdev->dev, "no per clock defined\n");
  1303. return PTR_ERR(clk_per);
  1304. }
  1305. clock_freq = clk_get_rate(clk_per);
  1306. }
  1307. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1308. irq = platform_get_irq(pdev, 0);
  1309. if (irq <= 0)
  1310. return -ENODEV;
  1311. regs = devm_ioremap_resource(&pdev->dev, mem);
  1312. if (IS_ERR(regs))
  1313. return PTR_ERR(regs);
  1314. of_id = of_match_device(flexcan_of_match, &pdev->dev);
  1315. if (of_id) {
  1316. devtype_data = of_id->data;
  1317. } else if (platform_get_device_id(pdev)->driver_data) {
  1318. devtype_data = (struct flexcan_devtype_data *)
  1319. platform_get_device_id(pdev)->driver_data;
  1320. } else {
  1321. return -ENODEV;
  1322. }
  1323. dev = alloc_candev(sizeof(struct flexcan_priv), 1);
  1324. if (!dev)
  1325. return -ENOMEM;
  1326. platform_set_drvdata(pdev, dev);
  1327. SET_NETDEV_DEV(dev, &pdev->dev);
  1328. dev->netdev_ops = &flexcan_netdev_ops;
  1329. dev->irq = irq;
  1330. dev->flags |= IFF_ECHO;
  1331. priv = netdev_priv(dev);
  1332. if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
  1333. devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
  1334. priv->read = flexcan_read_be;
  1335. priv->write = flexcan_write_be;
  1336. } else {
  1337. priv->read = flexcan_read_le;
  1338. priv->write = flexcan_write_le;
  1339. }
  1340. priv->dev = &pdev->dev;
  1341. priv->can.clock.freq = clock_freq;
  1342. priv->can.bittiming_const = &flexcan_bittiming_const;
  1343. priv->can.do_set_mode = flexcan_set_mode;
  1344. priv->can.do_get_berr_counter = flexcan_get_berr_counter;
  1345. priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
  1346. CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
  1347. CAN_CTRLMODE_BERR_REPORTING;
  1348. priv->regs = regs;
  1349. priv->clk_ipg = clk_ipg;
  1350. priv->clk_per = clk_per;
  1351. priv->clk_src = clk_src;
  1352. priv->devtype_data = devtype_data;
  1353. priv->reg_xceiver = reg_xceiver;
  1354. pm_runtime_get_noresume(&pdev->dev);
  1355. pm_runtime_set_active(&pdev->dev);
  1356. pm_runtime_enable(&pdev->dev);
  1357. err = register_flexcandev(dev);
  1358. if (err) {
  1359. dev_err(&pdev->dev, "registering netdev failed\n");
  1360. goto failed_register;
  1361. }
  1362. devm_can_led_init(dev);
  1363. if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
  1364. err = flexcan_setup_stop_mode(pdev);
  1365. if (err)
  1366. dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
  1367. }
  1368. return 0;
  1369. failed_register:
  1370. free_candev(dev);
  1371. return err;
  1372. }
  1373. static int flexcan_remove(struct platform_device *pdev)
  1374. {
  1375. struct net_device *dev = platform_get_drvdata(pdev);
  1376. unregister_flexcandev(dev);
  1377. pm_runtime_disable(&pdev->dev);
  1378. free_candev(dev);
  1379. return 0;
  1380. }
  1381. static int __maybe_unused flexcan_suspend(struct device *device)
  1382. {
  1383. struct net_device *dev = dev_get_drvdata(device);
  1384. struct flexcan_priv *priv = netdev_priv(dev);
  1385. int err = 0;
  1386. if (netif_running(dev)) {
  1387. /* if wakeup is enabled, enter stop mode
  1388. * else enter disabled mode.
  1389. */
  1390. if (device_may_wakeup(device)) {
  1391. enable_irq_wake(dev->irq);
  1392. err = flexcan_enter_stop_mode(priv);
  1393. if (err)
  1394. return err;
  1395. } else {
  1396. err = flexcan_chip_disable(priv);
  1397. if (err)
  1398. return err;
  1399. err = pm_runtime_force_suspend(device);
  1400. }
  1401. netif_stop_queue(dev);
  1402. netif_device_detach(dev);
  1403. }
  1404. priv->can.state = CAN_STATE_SLEEPING;
  1405. return err;
  1406. }
  1407. static int __maybe_unused flexcan_resume(struct device *device)
  1408. {
  1409. struct net_device *dev = dev_get_drvdata(device);
  1410. struct flexcan_priv *priv = netdev_priv(dev);
  1411. int err = 0;
  1412. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  1413. if (netif_running(dev)) {
  1414. netif_device_attach(dev);
  1415. netif_start_queue(dev);
  1416. if (device_may_wakeup(device)) {
  1417. disable_irq_wake(dev->irq);
  1418. } else {
  1419. err = pm_runtime_force_resume(device);
  1420. if (err)
  1421. return err;
  1422. err = flexcan_chip_enable(priv);
  1423. }
  1424. }
  1425. return err;
  1426. }
  1427. static int __maybe_unused flexcan_runtime_suspend(struct device *device)
  1428. {
  1429. struct net_device *dev = dev_get_drvdata(device);
  1430. struct flexcan_priv *priv = netdev_priv(dev);
  1431. flexcan_clks_disable(priv);
  1432. return 0;
  1433. }
  1434. static int __maybe_unused flexcan_runtime_resume(struct device *device)
  1435. {
  1436. struct net_device *dev = dev_get_drvdata(device);
  1437. struct flexcan_priv *priv = netdev_priv(dev);
  1438. return flexcan_clks_enable(priv);
  1439. }
  1440. static int __maybe_unused flexcan_noirq_suspend(struct device *device)
  1441. {
  1442. struct net_device *dev = dev_get_drvdata(device);
  1443. struct flexcan_priv *priv = netdev_priv(dev);
  1444. if (netif_running(dev) && device_may_wakeup(device))
  1445. flexcan_enable_wakeup_irq(priv, true);
  1446. return 0;
  1447. }
  1448. static int __maybe_unused flexcan_noirq_resume(struct device *device)
  1449. {
  1450. struct net_device *dev = dev_get_drvdata(device);
  1451. struct flexcan_priv *priv = netdev_priv(dev);
  1452. int err;
  1453. if (netif_running(dev) && device_may_wakeup(device)) {
  1454. flexcan_enable_wakeup_irq(priv, false);
  1455. err = flexcan_exit_stop_mode(priv);
  1456. if (err)
  1457. return err;
  1458. }
  1459. return 0;
  1460. }
  1461. static const struct dev_pm_ops flexcan_pm_ops = {
  1462. SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
  1463. SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
  1464. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
  1465. };
  1466. static struct platform_driver flexcan_driver = {
  1467. .driver = {
  1468. .name = DRV_NAME,
  1469. .pm = &flexcan_pm_ops,
  1470. .of_match_table = flexcan_of_match,
  1471. },
  1472. .probe = flexcan_probe,
  1473. .remove = flexcan_remove,
  1474. .id_table = flexcan_id_table,
  1475. };
  1476. module_platform_driver(flexcan_driver);
  1477. MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
  1478. "Marc Kleine-Budde <kernel@pengutronix.de>");
  1479. MODULE_LICENSE("GPL v2");
  1480. MODULE_DESCRIPTION("CAN port driver for flexcan based chip");