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/drivers/net/can/flexcan.c

https://codeberg.org/ddevault/linux
C | 1778 lines | 1289 code | 298 blank | 191 comment | 150 complexity | c796b3e0fd09a1771412b88eeec6a903 MD5 | raw file
Possible License(s): GPL-2.0
   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// flexcan.c - FLEXCAN CAN controller driver
   4//
   5// Copyright (c) 2005-2006 Varma Electronics Oy
   6// Copyright (c) 2009 Sascha Hauer, Pengutronix
   7// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8// Copyright (c) 2014 David Jander, Protonic Holland
   9//
  10// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12#include <linux/netdevice.h>
  13#include <linux/can.h>
  14#include <linux/can/dev.h>
  15#include <linux/can/error.h>
  16#include <linux/can/led.h>
  17#include <linux/can/rx-offload.h>
  18#include <linux/clk.h>
  19#include <linux/delay.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/mfd/syscon.h>
  23#include <linux/module.h>
  24#include <linux/of.h>
  25#include <linux/of_device.h>
  26#include <linux/platform_device.h>
  27#include <linux/pm_runtime.h>
  28#include <linux/regulator/consumer.h>
  29#include <linux/regmap.h>
  30
  31#define DRV_NAME			"flexcan"
  32
  33/* 8 for RX fifo and 2 error handling */
  34#define FLEXCAN_NAPI_WEIGHT		(8 + 2)
  35
  36/* FLEXCAN module configuration register (CANMCR) bits */
  37#define FLEXCAN_MCR_MDIS		BIT(31)
  38#define FLEXCAN_MCR_FRZ			BIT(30)
  39#define FLEXCAN_MCR_FEN			BIT(29)
  40#define FLEXCAN_MCR_HALT		BIT(28)
  41#define FLEXCAN_MCR_NOT_RDY		BIT(27)
  42#define FLEXCAN_MCR_WAK_MSK		BIT(26)
  43#define FLEXCAN_MCR_SOFTRST		BIT(25)
  44#define FLEXCAN_MCR_FRZ_ACK		BIT(24)
  45#define FLEXCAN_MCR_SUPV		BIT(23)
  46#define FLEXCAN_MCR_SLF_WAK		BIT(22)
  47#define FLEXCAN_MCR_WRN_EN		BIT(21)
  48#define FLEXCAN_MCR_LPM_ACK		BIT(20)
  49#define FLEXCAN_MCR_WAK_SRC		BIT(19)
  50#define FLEXCAN_MCR_DOZE		BIT(18)
  51#define FLEXCAN_MCR_SRX_DIS		BIT(17)
  52#define FLEXCAN_MCR_IRMQ		BIT(16)
  53#define FLEXCAN_MCR_LPRIO_EN		BIT(13)
  54#define FLEXCAN_MCR_AEN			BIT(12)
  55/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  56#define FLEXCAN_MCR_MAXMB(x)		((x) & 0x7f)
  57#define FLEXCAN_MCR_IDAM_A		(0x0 << 8)
  58#define FLEXCAN_MCR_IDAM_B		(0x1 << 8)
  59#define FLEXCAN_MCR_IDAM_C		(0x2 << 8)
  60#define FLEXCAN_MCR_IDAM_D		(0x3 << 8)
  61
  62/* FLEXCAN control register (CANCTRL) bits */
  63#define FLEXCAN_CTRL_PRESDIV(x)		(((x) & 0xff) << 24)
  64#define FLEXCAN_CTRL_RJW(x)		(((x) & 0x03) << 22)
  65#define FLEXCAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
  66#define FLEXCAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
  67#define FLEXCAN_CTRL_BOFF_MSK		BIT(15)
  68#define FLEXCAN_CTRL_ERR_MSK		BIT(14)
  69#define FLEXCAN_CTRL_CLK_SRC		BIT(13)
  70#define FLEXCAN_CTRL_LPB		BIT(12)
  71#define FLEXCAN_CTRL_TWRN_MSK		BIT(11)
  72#define FLEXCAN_CTRL_RWRN_MSK		BIT(10)
  73#define FLEXCAN_CTRL_SMP		BIT(7)
  74#define FLEXCAN_CTRL_BOFF_REC		BIT(6)
  75#define FLEXCAN_CTRL_TSYN		BIT(5)
  76#define FLEXCAN_CTRL_LBUF		BIT(4)
  77#define FLEXCAN_CTRL_LOM		BIT(3)
  78#define FLEXCAN_CTRL_PROPSEG(x)		((x) & 0x07)
  79#define FLEXCAN_CTRL_ERR_BUS		(FLEXCAN_CTRL_ERR_MSK)
  80#define FLEXCAN_CTRL_ERR_STATE \
  81	(FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  82	 FLEXCAN_CTRL_BOFF_MSK)
  83#define FLEXCAN_CTRL_ERR_ALL \
  84	(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  85
  86/* FLEXCAN control register 2 (CTRL2) bits */
  87#define FLEXCAN_CTRL2_ECRWRE		BIT(29)
  88#define FLEXCAN_CTRL2_WRMFRZ		BIT(28)
  89#define FLEXCAN_CTRL2_RFFN(x)		(((x) & 0x0f) << 24)
  90#define FLEXCAN_CTRL2_TASD(x)		(((x) & 0x1f) << 19)
  91#define FLEXCAN_CTRL2_MRP		BIT(18)
  92#define FLEXCAN_CTRL2_RRS		BIT(17)
  93#define FLEXCAN_CTRL2_EACEN		BIT(16)
  94
  95/* FLEXCAN memory error control register (MECR) bits */
  96#define FLEXCAN_MECR_ECRWRDIS		BIT(31)
  97#define FLEXCAN_MECR_HANCEI_MSK		BIT(19)
  98#define FLEXCAN_MECR_FANCEI_MSK		BIT(18)
  99#define FLEXCAN_MECR_CEI_MSK		BIT(16)
 100#define FLEXCAN_MECR_HAERRIE		BIT(15)
 101#define FLEXCAN_MECR_FAERRIE		BIT(14)
 102#define FLEXCAN_MECR_EXTERRIE		BIT(13)
 103#define FLEXCAN_MECR_RERRDIS		BIT(9)
 104#define FLEXCAN_MECR_ECCDIS		BIT(8)
 105#define FLEXCAN_MECR_NCEFAFRZ		BIT(7)
 106
 107/* FLEXCAN error and status register (ESR) bits */
 108#define FLEXCAN_ESR_TWRN_INT		BIT(17)
 109#define FLEXCAN_ESR_RWRN_INT		BIT(16)
 110#define FLEXCAN_ESR_BIT1_ERR		BIT(15)
 111#define FLEXCAN_ESR_BIT0_ERR		BIT(14)
 112#define FLEXCAN_ESR_ACK_ERR		BIT(13)
 113#define FLEXCAN_ESR_CRC_ERR		BIT(12)
 114#define FLEXCAN_ESR_FRM_ERR		BIT(11)
 115#define FLEXCAN_ESR_STF_ERR		BIT(10)
 116#define FLEXCAN_ESR_TX_WRN		BIT(9)
 117#define FLEXCAN_ESR_RX_WRN		BIT(8)
 118#define FLEXCAN_ESR_IDLE		BIT(7)
 119#define FLEXCAN_ESR_TXRX		BIT(6)
 120#define FLEXCAN_EST_FLT_CONF_SHIFT	(4)
 121#define FLEXCAN_ESR_FLT_CONF_MASK	(0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 122#define FLEXCAN_ESR_FLT_CONF_ACTIVE	(0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 123#define FLEXCAN_ESR_FLT_CONF_PASSIVE	(0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 124#define FLEXCAN_ESR_BOFF_INT		BIT(2)
 125#define FLEXCAN_ESR_ERR_INT		BIT(1)
 126#define FLEXCAN_ESR_WAK_INT		BIT(0)
 127#define FLEXCAN_ESR_ERR_BUS \
 128	(FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 129	 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 130	 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 131#define FLEXCAN_ESR_ERR_STATE \
 132	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 133#define FLEXCAN_ESR_ERR_ALL \
 134	(FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 135#define FLEXCAN_ESR_ALL_INT \
 136	(FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 137	 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
 138	 FLEXCAN_ESR_WAK_INT)
 139
 140/* FLEXCAN interrupt flag register (IFLAG) bits */
 141/* Errata ERR005829 step7: Reserve first valid MB */
 142#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO		8
 143#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP	0
 144#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST	(FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 145#define FLEXCAN_IFLAG_MB(x)		BIT((x) & 0x1f)
 146#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
 147#define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
 148#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE	BIT(5)
 149
 150/* FLEXCAN message buffers */
 151#define FLEXCAN_MB_CODE_MASK		(0xf << 24)
 152#define FLEXCAN_MB_CODE_RX_BUSY_BIT	(0x1 << 24)
 153#define FLEXCAN_MB_CODE_RX_INACTIVE	(0x0 << 24)
 154#define FLEXCAN_MB_CODE_RX_EMPTY	(0x4 << 24)
 155#define FLEXCAN_MB_CODE_RX_FULL		(0x2 << 24)
 156#define FLEXCAN_MB_CODE_RX_OVERRUN	(0x6 << 24)
 157#define FLEXCAN_MB_CODE_RX_RANSWER	(0xa << 24)
 158
 159#define FLEXCAN_MB_CODE_TX_INACTIVE	(0x8 << 24)
 160#define FLEXCAN_MB_CODE_TX_ABORT	(0x9 << 24)
 161#define FLEXCAN_MB_CODE_TX_DATA		(0xc << 24)
 162#define FLEXCAN_MB_CODE_TX_TANSWER	(0xe << 24)
 163
 164#define FLEXCAN_MB_CNT_SRR		BIT(22)
 165#define FLEXCAN_MB_CNT_IDE		BIT(21)
 166#define FLEXCAN_MB_CNT_RTR		BIT(20)
 167#define FLEXCAN_MB_CNT_LENGTH(x)	(((x) & 0xf) << 16)
 168#define FLEXCAN_MB_CNT_TIMESTAMP(x)	((x) & 0xffff)
 169
 170#define FLEXCAN_TIMEOUT_US		(250)
 171
 172/* FLEXCAN hardware feature flags
 173 *
 174 * Below is some version info we got:
 175 *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 176 *                                Filter? connected?  Passive detection  ception in MB
 177 *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 178 *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 179 *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 180 *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 181 *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 182 *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 183 * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 184 *
 185 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 186 */
 187#define FLEXCAN_QUIRK_BROKEN_WERR_STATE	BIT(1) /* [TR]WRN_INT not connected */
 188#define FLEXCAN_QUIRK_DISABLE_RXFG	BIT(2) /* Disable RX FIFO Global mask */
 189#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS	BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 190#define FLEXCAN_QUIRK_DISABLE_MECR	BIT(4) /* Disable Memory error detection */
 191#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP	BIT(5) /* Use timestamp based offloading */
 192#define FLEXCAN_QUIRK_BROKEN_PERR_STATE	BIT(6) /* No interrupt for error passive */
 193#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN	BIT(7) /* default to BE register access */
 194#define FLEXCAN_QUIRK_SETUP_STOP_MODE		BIT(8) /* Setup stop mode to support wakeup */
 195
 196/* Structure of the message buffer */
 197struct flexcan_mb {
 198	u32 can_ctrl;
 199	u32 can_id;
 200	u32 data[];
 201};
 202
 203/* Structure of the hardware registers */
 204struct flexcan_regs {
 205	u32 mcr;		/* 0x00 */
 206	u32 ctrl;		/* 0x04 */
 207	u32 timer;		/* 0x08 */
 208	u32 _reserved1;		/* 0x0c */
 209	u32 rxgmask;		/* 0x10 */
 210	u32 rx14mask;		/* 0x14 */
 211	u32 rx15mask;		/* 0x18 */
 212	u32 ecr;		/* 0x1c */
 213	u32 esr;		/* 0x20 */
 214	u32 imask2;		/* 0x24 */
 215	u32 imask1;		/* 0x28 */
 216	u32 iflag2;		/* 0x2c */
 217	u32 iflag1;		/* 0x30 */
 218	union {			/* 0x34 */
 219		u32 gfwr_mx28;	/* MX28, MX53 */
 220		u32 ctrl2;	/* MX6, VF610 */
 221	};
 222	u32 esr2;		/* 0x38 */
 223	u32 imeur;		/* 0x3c */
 224	u32 lrfr;		/* 0x40 */
 225	u32 crcr;		/* 0x44 */
 226	u32 rxfgmask;		/* 0x48 */
 227	u32 rxfir;		/* 0x4c */
 228	u32 _reserved3[12];	/* 0x50 */
 229	u8 mb[2][512];		/* 0x80 */
 230	/* FIFO-mode:
 231	 *			MB
 232	 * 0x080...0x08f	0	RX message buffer
 233	 * 0x090...0x0df	1-5	reserverd
 234	 * 0x0e0...0x0ff	6-7	8 entry ID table
 235	 *				(mx25, mx28, mx35, mx53)
 236	 * 0x0e0...0x2df	6-7..37	8..128 entry ID table
 237	 *				size conf'ed via ctrl2::RFFN
 238	 *				(mx6, vf610)
 239	 */
 240	u32 _reserved4[256];	/* 0x480 */
 241	u32 rximr[64];		/* 0x880 */
 242	u32 _reserved5[24];	/* 0x980 */
 243	u32 gfwr_mx6;		/* 0x9e0 - MX6 */
 244	u32 _reserved6[63];	/* 0x9e4 */
 245	u32 mecr;		/* 0xae0 */
 246	u32 erriar;		/* 0xae4 */
 247	u32 erridpr;		/* 0xae8 */
 248	u32 errippr;		/* 0xaec */
 249	u32 rerrar;		/* 0xaf0 */
 250	u32 rerrdr;		/* 0xaf4 */
 251	u32 rerrsynr;		/* 0xaf8 */
 252	u32 errsr;		/* 0xafc */
 253};
 254
 255struct flexcan_devtype_data {
 256	u32 quirks;		/* quirks needed for different IP cores */
 257};
 258
 259struct flexcan_stop_mode {
 260	struct regmap *gpr;
 261	u8 req_gpr;
 262	u8 req_bit;
 263	u8 ack_gpr;
 264	u8 ack_bit;
 265};
 266
 267struct flexcan_priv {
 268	struct can_priv can;
 269	struct can_rx_offload offload;
 270	struct device *dev;
 271
 272	struct flexcan_regs __iomem *regs;
 273	struct flexcan_mb __iomem *tx_mb;
 274	struct flexcan_mb __iomem *tx_mb_reserved;
 275	u8 tx_mb_idx;
 276	u8 mb_count;
 277	u8 mb_size;
 278	u8 clk_src;	/* clock source of CAN Protocol Engine */
 279
 280	u32 reg_ctrl_default;
 281	u32 reg_imask1_default;
 282	u32 reg_imask2_default;
 283
 284	struct clk *clk_ipg;
 285	struct clk *clk_per;
 286	const struct flexcan_devtype_data *devtype_data;
 287	struct regulator *reg_xceiver;
 288	struct flexcan_stop_mode stm;
 289
 290	/* Read and Write APIs */
 291	u32 (*read)(void __iomem *addr);
 292	void (*write)(u32 val, void __iomem *addr);
 293};
 294
 295static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 296	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 297		FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 298		FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 299};
 300
 301static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 302	.quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 303		FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 304};
 305
 306static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 307	.quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 308};
 309
 310static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 311	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 312		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 313		FLEXCAN_QUIRK_SETUP_STOP_MODE,
 314};
 315
 316static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 317	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 318		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 319		FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 320};
 321
 322static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 323	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 324		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 325		FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 326};
 327
 328static const struct can_bittiming_const flexcan_bittiming_const = {
 329	.name = DRV_NAME,
 330	.tseg1_min = 4,
 331	.tseg1_max = 16,
 332	.tseg2_min = 2,
 333	.tseg2_max = 8,
 334	.sjw_max = 4,
 335	.brp_min = 1,
 336	.brp_max = 256,
 337	.brp_inc = 1,
 338};
 339
 340/* FlexCAN module is essentially modelled as a little-endian IP in most
 341 * SoCs, i.e the registers as well as the message buffer areas are
 342 * implemented in a little-endian fashion.
 343 *
 344 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 345 * module in a big-endian fashion (i.e the registers as well as the
 346 * message buffer areas are implemented in a big-endian way).
 347 *
 348 * In addition, the FlexCAN module can be found on SoCs having ARM or
 349 * PPC cores. So, we need to abstract off the register read/write
 350 * functions, ensuring that these cater to all the combinations of module
 351 * endianness and underlying CPU endianness.
 352 */
 353static inline u32 flexcan_read_be(void __iomem *addr)
 354{
 355	return ioread32be(addr);
 356}
 357
 358static inline void flexcan_write_be(u32 val, void __iomem *addr)
 359{
 360	iowrite32be(val, addr);
 361}
 362
 363static inline u32 flexcan_read_le(void __iomem *addr)
 364{
 365	return ioread32(addr);
 366}
 367
 368static inline void flexcan_write_le(u32 val, void __iomem *addr)
 369{
 370	iowrite32(val, addr);
 371}
 372
 373static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 374						 u8 mb_index)
 375{
 376	u8 bank_size;
 377	bool bank;
 378
 379	if (WARN_ON(mb_index >= priv->mb_count))
 380		return NULL;
 381
 382	bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 383
 384	bank = mb_index >= bank_size;
 385	if (bank)
 386		mb_index -= bank_size;
 387
 388	return (struct flexcan_mb __iomem *)
 389		(&priv->regs->mb[bank][priv->mb_size * mb_index]);
 390}
 391
 392static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 393{
 394	struct flexcan_regs __iomem *regs = priv->regs;
 395	u32 reg_mcr;
 396
 397	reg_mcr = priv->read(&regs->mcr);
 398
 399	if (enable)
 400		reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 401	else
 402		reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 403
 404	priv->write(reg_mcr, &regs->mcr);
 405}
 406
 407static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 408{
 409	struct flexcan_regs __iomem *regs = priv->regs;
 410	unsigned int ackval;
 411	u32 reg_mcr;
 412
 413	reg_mcr = priv->read(&regs->mcr);
 414	reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 415	priv->write(reg_mcr, &regs->mcr);
 416
 417	/* enable stop request */
 418	regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 419			   1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 420
 421	/* get stop acknowledgment */
 422	if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
 423				     ackval, ackval & (1 << priv->stm.ack_bit),
 424				     0, FLEXCAN_TIMEOUT_US))
 425		return -ETIMEDOUT;
 426
 427	return 0;
 428}
 429
 430static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 431{
 432	struct flexcan_regs __iomem *regs = priv->regs;
 433	unsigned int ackval;
 434	u32 reg_mcr;
 435
 436	/* remove stop request */
 437	regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 438			   1 << priv->stm.req_bit, 0);
 439
 440	/* get stop acknowledgment */
 441	if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
 442				     ackval, !(ackval & (1 << priv->stm.ack_bit)),
 443				     0, FLEXCAN_TIMEOUT_US))
 444		return -ETIMEDOUT;
 445
 446	reg_mcr = priv->read(&regs->mcr);
 447	reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 448	priv->write(reg_mcr, &regs->mcr);
 449
 450	return 0;
 451}
 452
 453static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 454{
 455	struct flexcan_regs __iomem *regs = priv->regs;
 456	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 457
 458	priv->write(reg_ctrl, &regs->ctrl);
 459}
 460
 461static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 462{
 463	struct flexcan_regs __iomem *regs = priv->regs;
 464	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 465
 466	priv->write(reg_ctrl, &regs->ctrl);
 467}
 468
 469static int flexcan_clks_enable(const struct flexcan_priv *priv)
 470{
 471	int err;
 472
 473	err = clk_prepare_enable(priv->clk_ipg);
 474	if (err)
 475		return err;
 476
 477	err = clk_prepare_enable(priv->clk_per);
 478	if (err)
 479		clk_disable_unprepare(priv->clk_ipg);
 480
 481	return err;
 482}
 483
 484static void flexcan_clks_disable(const struct flexcan_priv *priv)
 485{
 486	clk_disable_unprepare(priv->clk_per);
 487	clk_disable_unprepare(priv->clk_ipg);
 488}
 489
 490static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 491{
 492	if (!priv->reg_xceiver)
 493		return 0;
 494
 495	return regulator_enable(priv->reg_xceiver);
 496}
 497
 498static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 499{
 500	if (!priv->reg_xceiver)
 501		return 0;
 502
 503	return regulator_disable(priv->reg_xceiver);
 504}
 505
 506static int flexcan_chip_enable(struct flexcan_priv *priv)
 507{
 508	struct flexcan_regs __iomem *regs = priv->regs;
 509	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 510	u32 reg;
 511
 512	reg = priv->read(&regs->mcr);
 513	reg &= ~FLEXCAN_MCR_MDIS;
 514	priv->write(reg, &regs->mcr);
 515
 516	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 517		udelay(10);
 518
 519	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 520		return -ETIMEDOUT;
 521
 522	return 0;
 523}
 524
 525static int flexcan_chip_disable(struct flexcan_priv *priv)
 526{
 527	struct flexcan_regs __iomem *regs = priv->regs;
 528	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 529	u32 reg;
 530
 531	reg = priv->read(&regs->mcr);
 532	reg |= FLEXCAN_MCR_MDIS;
 533	priv->write(reg, &regs->mcr);
 534
 535	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 536		udelay(10);
 537
 538	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 539		return -ETIMEDOUT;
 540
 541	return 0;
 542}
 543
 544static int flexcan_chip_freeze(struct flexcan_priv *priv)
 545{
 546	struct flexcan_regs __iomem *regs = priv->regs;
 547	unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 548	u32 reg;
 549
 550	reg = priv->read(&regs->mcr);
 551	reg |= FLEXCAN_MCR_HALT;
 552	priv->write(reg, &regs->mcr);
 553
 554	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 555		udelay(100);
 556
 557	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 558		return -ETIMEDOUT;
 559
 560	return 0;
 561}
 562
 563static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 564{
 565	struct flexcan_regs __iomem *regs = priv->regs;
 566	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 567	u32 reg;
 568
 569	reg = priv->read(&regs->mcr);
 570	reg &= ~FLEXCAN_MCR_HALT;
 571	priv->write(reg, &regs->mcr);
 572
 573	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 574		udelay(10);
 575
 576	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 577		return -ETIMEDOUT;
 578
 579	return 0;
 580}
 581
 582static int flexcan_chip_softreset(struct flexcan_priv *priv)
 583{
 584	struct flexcan_regs __iomem *regs = priv->regs;
 585	unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 586
 587	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 588	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 589		udelay(10);
 590
 591	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 592		return -ETIMEDOUT;
 593
 594	return 0;
 595}
 596
 597static int __flexcan_get_berr_counter(const struct net_device *dev,
 598				      struct can_berr_counter *bec)
 599{
 600	const struct flexcan_priv *priv = netdev_priv(dev);
 601	struct flexcan_regs __iomem *regs = priv->regs;
 602	u32 reg = priv->read(&regs->ecr);
 603
 604	bec->txerr = (reg >> 0) & 0xff;
 605	bec->rxerr = (reg >> 8) & 0xff;
 606
 607	return 0;
 608}
 609
 610static int flexcan_get_berr_counter(const struct net_device *dev,
 611				    struct can_berr_counter *bec)
 612{
 613	const struct flexcan_priv *priv = netdev_priv(dev);
 614	int err;
 615
 616	err = pm_runtime_get_sync(priv->dev);
 617	if (err < 0)
 618		return err;
 619
 620	err = __flexcan_get_berr_counter(dev, bec);
 621
 622	pm_runtime_put(priv->dev);
 623
 624	return err;
 625}
 626
 627static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 628{
 629	const struct flexcan_priv *priv = netdev_priv(dev);
 630	struct can_frame *cf = (struct can_frame *)skb->data;
 631	u32 can_id;
 632	u32 data;
 633	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 634	int i;
 635
 636	if (can_dropped_invalid_skb(dev, skb))
 637		return NETDEV_TX_OK;
 638
 639	netif_stop_queue(dev);
 640
 641	if (cf->can_id & CAN_EFF_FLAG) {
 642		can_id = cf->can_id & CAN_EFF_MASK;
 643		ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 644	} else {
 645		can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 646	}
 647
 648	if (cf->can_id & CAN_RTR_FLAG)
 649		ctrl |= FLEXCAN_MB_CNT_RTR;
 650
 651	for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 652		data = be32_to_cpup((__be32 *)&cf->data[i]);
 653		priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 654	}
 655
 656	can_put_echo_skb(skb, dev, 0);
 657
 658	priv->write(can_id, &priv->tx_mb->can_id);
 659	priv->write(ctrl, &priv->tx_mb->can_ctrl);
 660
 661	/* Errata ERR005829 step8:
 662	 * Write twice INACTIVE(0x8) code to first MB.
 663	 */
 664	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 665		    &priv->tx_mb_reserved->can_ctrl);
 666	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 667		    &priv->tx_mb_reserved->can_ctrl);
 668
 669	return NETDEV_TX_OK;
 670}
 671
 672static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 673{
 674	struct flexcan_priv *priv = netdev_priv(dev);
 675	struct flexcan_regs __iomem *regs = priv->regs;
 676	struct sk_buff *skb;
 677	struct can_frame *cf;
 678	bool rx_errors = false, tx_errors = false;
 679	u32 timestamp;
 680
 681	timestamp = priv->read(&regs->timer) << 16;
 682
 683	skb = alloc_can_err_skb(dev, &cf);
 684	if (unlikely(!skb))
 685		return;
 686
 687	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 688
 689	if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 690		netdev_dbg(dev, "BIT1_ERR irq\n");
 691		cf->data[2] |= CAN_ERR_PROT_BIT1;
 692		tx_errors = true;
 693	}
 694	if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 695		netdev_dbg(dev, "BIT0_ERR irq\n");
 696		cf->data[2] |= CAN_ERR_PROT_BIT0;
 697		tx_errors = true;
 698	}
 699	if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 700		netdev_dbg(dev, "ACK_ERR irq\n");
 701		cf->can_id |= CAN_ERR_ACK;
 702		cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 703		tx_errors = true;
 704	}
 705	if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 706		netdev_dbg(dev, "CRC_ERR irq\n");
 707		cf->data[2] |= CAN_ERR_PROT_BIT;
 708		cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 709		rx_errors = true;
 710	}
 711	if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 712		netdev_dbg(dev, "FRM_ERR irq\n");
 713		cf->data[2] |= CAN_ERR_PROT_FORM;
 714		rx_errors = true;
 715	}
 716	if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 717		netdev_dbg(dev, "STF_ERR irq\n");
 718		cf->data[2] |= CAN_ERR_PROT_STUFF;
 719		rx_errors = true;
 720	}
 721
 722	priv->can.can_stats.bus_error++;
 723	if (rx_errors)
 724		dev->stats.rx_errors++;
 725	if (tx_errors)
 726		dev->stats.tx_errors++;
 727
 728	can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 729}
 730
 731static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 732{
 733	struct flexcan_priv *priv = netdev_priv(dev);
 734	struct flexcan_regs __iomem *regs = priv->regs;
 735	struct sk_buff *skb;
 736	struct can_frame *cf;
 737	enum can_state new_state, rx_state, tx_state;
 738	int flt;
 739	struct can_berr_counter bec;
 740	u32 timestamp;
 741
 742	timestamp = priv->read(&regs->timer) << 16;
 743
 744	flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 745	if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 746		tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 747			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 748		rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 749			CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 750		new_state = max(tx_state, rx_state);
 751	} else {
 752		__flexcan_get_berr_counter(dev, &bec);
 753		new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 754			CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 755		rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 756		tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 757	}
 758
 759	/* state hasn't changed */
 760	if (likely(new_state == priv->can.state))
 761		return;
 762
 763	skb = alloc_can_err_skb(dev, &cf);
 764	if (unlikely(!skb))
 765		return;
 766
 767	can_change_state(dev, cf, tx_state, rx_state);
 768
 769	if (unlikely(new_state == CAN_STATE_BUS_OFF))
 770		can_bus_off(dev);
 771
 772	can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 773}
 774
 775static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 776{
 777	return container_of(offload, struct flexcan_priv, offload);
 778}
 779
 780static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 781					 struct can_frame *cf,
 782					 u32 *timestamp, unsigned int n)
 783{
 784	struct flexcan_priv *priv = rx_offload_to_priv(offload);
 785	struct flexcan_regs __iomem *regs = priv->regs;
 786	struct flexcan_mb __iomem *mb;
 787	u32 reg_ctrl, reg_id, reg_iflag1;
 788	int i;
 789
 790	mb = flexcan_get_mb(priv, n);
 791
 792	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 793		u32 code;
 794
 795		do {
 796			reg_ctrl = priv->read(&mb->can_ctrl);
 797		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 798
 799		/* is this MB empty? */
 800		code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 801		if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 802		    (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 803			return 0;
 804
 805		if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 806			/* This MB was overrun, we lost data */
 807			offload->dev->stats.rx_over_errors++;
 808			offload->dev->stats.rx_errors++;
 809		}
 810	} else {
 811		reg_iflag1 = priv->read(&regs->iflag1);
 812		if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 813			return 0;
 814
 815		reg_ctrl = priv->read(&mb->can_ctrl);
 816	}
 817
 818	/* increase timstamp to full 32 bit */
 819	*timestamp = reg_ctrl << 16;
 820
 821	reg_id = priv->read(&mb->can_id);
 822	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 823		cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 824	else
 825		cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 826
 827	if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 828		cf->can_id |= CAN_RTR_FLAG;
 829	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 830
 831	for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 832		__be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
 833		*(__be32 *)(cf->data + i) = data;
 834	}
 835
 836	/* mark as read */
 837	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 838		/* Clear IRQ */
 839		if (n < 32)
 840			priv->write(BIT(n), &regs->iflag1);
 841		else
 842			priv->write(BIT(n - 32), &regs->iflag2);
 843	} else {
 844		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 845	}
 846
 847	/* Read the Free Running Timer. It is optional but recommended
 848	 * to unlock Mailbox as soon as possible and make it available
 849	 * for reception.
 850	 */
 851	priv->read(&regs->timer);
 852
 853	return 1;
 854}
 855
 856
 857static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 858{
 859	struct flexcan_regs __iomem *regs = priv->regs;
 860	u32 iflag1, iflag2;
 861
 862	iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
 863		~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
 864	iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
 865
 866	return (u64)iflag2 << 32 | iflag1;
 867}
 868
 869static irqreturn_t flexcan_irq(int irq, void *dev_id)
 870{
 871	struct net_device *dev = dev_id;
 872	struct net_device_stats *stats = &dev->stats;
 873	struct flexcan_priv *priv = netdev_priv(dev);
 874	struct flexcan_regs __iomem *regs = priv->regs;
 875	irqreturn_t handled = IRQ_NONE;
 876	u32 reg_iflag2, reg_esr;
 877	enum can_state last_state = priv->can.state;
 878
 879	/* reception interrupt */
 880	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 881		u64 reg_iflag;
 882		int ret;
 883
 884		while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
 885			handled = IRQ_HANDLED;
 886			ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 887								   reg_iflag);
 888			if (!ret)
 889				break;
 890		}
 891	} else {
 892		u32 reg_iflag1;
 893
 894		reg_iflag1 = priv->read(&regs->iflag1);
 895		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 896			handled = IRQ_HANDLED;
 897			can_rx_offload_irq_offload_fifo(&priv->offload);
 898		}
 899
 900		/* FIFO overflow interrupt */
 901		if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 902			handled = IRQ_HANDLED;
 903			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 904				    &regs->iflag1);
 905			dev->stats.rx_over_errors++;
 906			dev->stats.rx_errors++;
 907		}
 908	}
 909
 910	reg_iflag2 = priv->read(&regs->iflag2);
 911
 912	/* transmission complete interrupt */
 913	if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
 914		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
 915
 916		handled = IRQ_HANDLED;
 917		stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
 918							       0, reg_ctrl << 16);
 919		stats->tx_packets++;
 920		can_led_event(dev, CAN_LED_EVENT_TX);
 921
 922		/* after sending a RTR frame MB is in RX mode */
 923		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 924			    &priv->tx_mb->can_ctrl);
 925		priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
 926		netif_wake_queue(dev);
 927	}
 928
 929	reg_esr = priv->read(&regs->esr);
 930
 931	/* ACK all bus error and state change IRQ sources */
 932	if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 933		handled = IRQ_HANDLED;
 934		priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 935	}
 936
 937	/* state change interrupt or broken error state quirk fix is enabled */
 938	if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 939	    (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 940					   FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 941		flexcan_irq_state(dev, reg_esr);
 942
 943	/* bus error IRQ - handle if bus error reporting is activated */
 944	if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 945	    (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 946		flexcan_irq_bus_err(dev, reg_esr);
 947
 948	/* availability of error interrupt among state transitions in case
 949	 * bus error reporting is de-activated and
 950	 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 951	 *  +--------------------------------------------------------------+
 952	 *  | +----------------------------------------------+ [stopped /  |
 953	 *  | |                                              |  sleeping] -+
 954	 *  +-+-> active <-> warning <-> passive -> bus off -+
 955	 *        ___________^^^^^^^^^^^^_______________________________
 956	 *        disabled(1)  enabled             disabled
 957	 *
 958	 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 959	 */
 960	if ((last_state != priv->can.state) &&
 961	    (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 962	    !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 963		switch (priv->can.state) {
 964		case CAN_STATE_ERROR_ACTIVE:
 965			if (priv->devtype_data->quirks &
 966			    FLEXCAN_QUIRK_BROKEN_WERR_STATE)
 967				flexcan_error_irq_enable(priv);
 968			else
 969				flexcan_error_irq_disable(priv);
 970			break;
 971
 972		case CAN_STATE_ERROR_WARNING:
 973			flexcan_error_irq_enable(priv);
 974			break;
 975
 976		case CAN_STATE_ERROR_PASSIVE:
 977		case CAN_STATE_BUS_OFF:
 978			flexcan_error_irq_disable(priv);
 979			break;
 980
 981		default:
 982			break;
 983		}
 984	}
 985
 986	return handled;
 987}
 988
 989static void flexcan_set_bittiming(struct net_device *dev)
 990{
 991	const struct flexcan_priv *priv = netdev_priv(dev);
 992	const struct can_bittiming *bt = &priv->can.bittiming;
 993	struct flexcan_regs __iomem *regs = priv->regs;
 994	u32 reg;
 995
 996	reg = priv->read(&regs->ctrl);
 997	reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 998		 FLEXCAN_CTRL_RJW(0x3) |
 999		 FLEXCAN_CTRL_PSEG1(0x7) |
1000		 FLEXCAN_CTRL_PSEG2(0x7) |
1001		 FLEXCAN_CTRL_PROPSEG(0x7) |
1002		 FLEXCAN_CTRL_LPB |
1003		 FLEXCAN_CTRL_SMP |
1004		 FLEXCAN_CTRL_LOM);
1005
1006	reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1007		FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1008		FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1009		FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1010		FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1011
1012	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1013		reg |= FLEXCAN_CTRL_LPB;
1014	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1015		reg |= FLEXCAN_CTRL_LOM;
1016	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1017		reg |= FLEXCAN_CTRL_SMP;
1018
1019	netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1020	priv->write(reg, &regs->ctrl);
1021
1022	/* print chip status */
1023	netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1024		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1025}
1026
1027/* flexcan_chip_start
1028 *
1029 * this functions is entered with clocks enabled
1030 *
1031 */
1032static int flexcan_chip_start(struct net_device *dev)
1033{
1034	struct flexcan_priv *priv = netdev_priv(dev);
1035	struct flexcan_regs __iomem *regs = priv->regs;
1036	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1037	int err, i;
1038	struct flexcan_mb __iomem *mb;
1039
1040	/* enable module */
1041	err = flexcan_chip_enable(priv);
1042	if (err)
1043		return err;
1044
1045	/* soft reset */
1046	err = flexcan_chip_softreset(priv);
1047	if (err)
1048		goto out_chip_disable;
1049
1050	flexcan_set_bittiming(dev);
1051
1052	/* MCR
1053	 *
1054	 * enable freeze
1055	 * halt now
1056	 * only supervisor access
1057	 * enable warning int
1058	 * enable individual RX masking
1059	 * choose format C
1060	 * set max mailbox number
1061	 */
1062	reg_mcr = priv->read(&regs->mcr);
1063	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1064	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1065		FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1066		FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1067
1068	/* MCR
1069	 *
1070	 * FIFO:
1071	 * - disable for timestamp mode
1072	 * - enable for FIFO mode
1073	 */
1074	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1075		reg_mcr &= ~FLEXCAN_MCR_FEN;
1076	else
1077		reg_mcr |= FLEXCAN_MCR_FEN;
1078
1079	/* MCR
1080	 *
1081	 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1082	 *       asserted because this will impede the self reception
1083	 *       of a transmitted message. This is not documented in
1084	 *       earlier versions of flexcan block guide.
1085	 *
1086	 * Self Reception:
1087	 * - enable Self Reception for loopback mode
1088	 *   (by clearing "Self Reception Disable" bit)
1089	 * - disable for normal operation
1090	 */
1091	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1092		reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1093	else
1094		reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1095
1096	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1097	priv->write(reg_mcr, &regs->mcr);
1098
1099	/* CTRL
1100	 *
1101	 * disable timer sync feature
1102	 *
1103	 * disable auto busoff recovery
1104	 * transmit lowest buffer first
1105	 *
1106	 * enable tx and rx warning interrupt
1107	 * enable bus off interrupt
1108	 * (== FLEXCAN_CTRL_ERR_STATE)
1109	 */
1110	reg_ctrl = priv->read(&regs->ctrl);
1111	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1112	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1113		FLEXCAN_CTRL_ERR_STATE;
1114
1115	/* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1116	 * on most Flexcan cores, too. Otherwise we don't get
1117	 * any error warning or passive interrupts.
1118	 */
1119	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1120	    priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1121		reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1122	else
1123		reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1124
1125	/* save for later use */
1126	priv->reg_ctrl_default = reg_ctrl;
1127	/* leave interrupts disabled for now */
1128	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1129	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1130	priv->write(reg_ctrl, &regs->ctrl);
1131
1132	if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1133		reg_ctrl2 = priv->read(&regs->ctrl2);
1134		reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1135		priv->write(reg_ctrl2, &regs->ctrl2);
1136	}
1137
1138	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1139		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1140			mb = flexcan_get_mb(priv, i);
1141			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1142				    &mb->can_ctrl);
1143		}
1144	} else {
1145		/* clear and invalidate unused mailboxes first */
1146		for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1147			mb = flexcan_get_mb(priv, i);
1148			priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1149				    &mb->can_ctrl);
1150		}
1151	}
1152
1153	/* Errata ERR005829: mark first TX mailbox as INACTIVE */
1154	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1155		    &priv->tx_mb_reserved->can_ctrl);
1156
1157	/* mark TX mailbox as INACTIVE */
1158	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1159		    &priv->tx_mb->can_ctrl);
1160
1161	/* acceptance mask/acceptance code (accept everything) */
1162	priv->write(0x0, &regs->rxgmask);
1163	priv->write(0x0, &regs->rx14mask);
1164	priv->write(0x0, &regs->rx15mask);
1165
1166	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1167		priv->write(0x0, &regs->rxfgmask);
1168
1169	/* clear acceptance filters */
1170	for (i = 0; i < priv->mb_count; i++)
1171		priv->write(0, &regs->rximr[i]);
1172
1173	/* On Vybrid, disable memory error detection interrupts
1174	 * and freeze mode.
1175	 * This also works around errata e5295 which generates
1176	 * false positive memory errors and put the device in
1177	 * freeze mode.
1178	 */
1179	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1180		/* Follow the protocol as described in "Detection
1181		 * and Correction of Memory Errors" to write to
1182		 * MECR register
1183		 */
1184		reg_ctrl2 = priv->read(&regs->ctrl2);
1185		reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1186		priv->write(reg_ctrl2, &regs->ctrl2);
1187
1188		reg_mecr = priv->read(&regs->mecr);
1189		reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1190		priv->write(reg_mecr, &regs->mecr);
1191		reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1192			      FLEXCAN_MECR_FANCEI_MSK);
1193		priv->write(reg_mecr, &regs->mecr);
1194	}
1195
1196	err = flexcan_transceiver_enable(priv);
1197	if (err)
1198		goto out_chip_disable;
1199
1200	/* synchronize with the can bus */
1201	err = flexcan_chip_unfreeze(priv);
1202	if (err)
1203		goto out_transceiver_disable;
1204
1205	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1206
1207	/* enable interrupts atomically */
1208	disable_irq(dev->irq);
1209	priv->write(priv->reg_ctrl_default, &regs->ctrl);
1210	priv->write(priv->reg_imask1_default, &regs->imask1);
1211	priv->write(priv->reg_imask2_default, &regs->imask2);
1212	enable_irq(dev->irq);
1213
1214	/* print chip status */
1215	netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1216		   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1217
1218	return 0;
1219
1220 out_transceiver_disable:
1221	flexcan_transceiver_disable(priv);
1222 out_chip_disable:
1223	flexcan_chip_disable(priv);
1224	return err;
1225}
1226
1227/* flexcan_chip_stop
1228 *
1229 * this functions is entered with clocks enabled
1230 */
1231static void flexcan_chip_stop(struct net_device *dev)
1232{
1233	struct flexcan_priv *priv = netdev_priv(dev);
1234	struct flexcan_regs __iomem *regs = priv->regs;
1235
1236	/* freeze + disable module */
1237	flexcan_chip_freeze(priv);
1238	flexcan_chip_disable(priv);
1239
1240	/* Disable all interrupts */
1241	priv->write(0, &regs->imask2);
1242	priv->write(0, &regs->imask1);
1243	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1244		    &regs->ctrl);
1245
1246	flexcan_transceiver_disable(priv);
1247	priv->can.state = CAN_STATE_STOPPED;
1248}
1249
1250static int flexcan_open(struct net_device *dev)
1251{
1252	struct flexcan_priv *priv = netdev_priv(dev);
1253	int err;
1254
1255	err = pm_runtime_get_sync(priv->dev);
1256	if (err < 0)
1257		return err;
1258
1259	err = open_candev(dev);
1260	if (err)
1261		goto out_runtime_put;
1262
1263	err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1264	if (err)
1265		goto out_close;
1266
1267	priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1268	priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1269			 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1270
1271	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1272		priv->tx_mb_reserved =
1273			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1274	else
1275		priv->tx_mb_reserved =
1276			flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1277	priv->tx_mb_idx = priv->mb_count - 1;
1278	priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1279
1280	priv->reg_imask1_default = 0;
1281	priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1282
1283	priv->offload.mailbox_read = flexcan_mailbox_read;
1284
1285	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1286		u64 imask;
1287
1288		priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1289		priv->offload.mb_last = priv->mb_count - 2;
1290
1291		imask = GENMASK_ULL(priv->offload.mb_last,
1292				    priv->offload.mb_first);
1293		priv->reg_imask1_default |= imask;
1294		priv->reg_imask2_default |= imask >> 32;
1295
1296		err = can_rx_offload_add_timestamp(dev, &priv->offload);
1297	} else {
1298		priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1299			FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1300		err = can_rx_offload_add_fifo(dev, &priv->offload,
1301					      FLEXCAN_NAPI_WEIGHT);
1302	}
1303	if (err)
1304		goto out_free_irq;
1305
1306	/* start chip and queuing */
1307	err = flexcan_chip_start(dev);
1308	if (err)
1309		goto out_offload_del;
1310
1311	can_led_event(dev, CAN_LED_EVENT_OPEN);
1312
1313	can_rx_offload_enable(&priv->offload);
1314	netif_start_queue(dev);
1315
1316	return 0;
1317
1318 out_offload_del:
1319	can_rx_offload_del(&priv->offload);
1320 out_free_irq:
1321	free_irq(dev->irq, dev);
1322 out_close:
1323	close_candev(dev);
1324 out_runtime_put:
1325	pm_runtime_put(priv->dev);
1326
1327	return err;
1328}
1329
1330static int flexcan_close(struct net_device *dev)
1331{
1332	struct flexcan_priv *priv = netdev_priv(dev);
1333
1334	netif_stop_queue(dev);
1335	can_rx_offload_disable(&priv->offload);
1336	flexcan_chip_stop(dev);
1337
1338	can_rx_offload_del(&priv->offload);
1339	free_irq(dev->irq, dev);
1340
1341	close_candev(dev);
1342	pm_runtime_put(priv->dev);
1343
1344	can_led_event(dev, CAN_LED_EVENT_STOP);
1345
1346	return 0;
1347}
1348
1349static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1350{
1351	int err;
1352
1353	switch (mode) {
1354	case CAN_MODE_START:
1355		err = flexcan_chip_start(dev);
1356		if (err)
1357			return err;
1358
1359		netif_wake_queue(dev);
1360		break;
1361
1362	default:
1363		return -EOPNOTSUPP;
1364	}
1365
1366	return 0;
1367}
1368
1369static const struct net_device_ops flexcan_netdev_ops = {
1370	.ndo_open	= flexcan_open,
1371	.ndo_stop	= flexcan_close,
1372	.ndo_start_xmit	= flexcan_start_xmit,
1373	.ndo_change_mtu = can_change_mtu,
1374};
1375
1376static int register_flexcandev(struct net_device *dev)
1377{
1378	struct flexcan_priv *priv = netdev_priv(dev);
1379	struct flexcan_regs __iomem *regs = priv->regs;
1380	u32 reg, err;
1381
1382	err = flexcan_clks_enable(priv);
1383	if (err)
1384		return err;
1385
1386	/* select "bus clock", chip must be disabled */
1387	err = flexcan_chip_disable(priv);
1388	if (err)
1389		goto out_clks_disable;
1390
1391	reg = priv->read(&regs->ctrl);
1392	if (priv->clk_src)
1393		reg |= FLEXCAN_CTRL_CLK_SRC;
1394	else
1395		reg &= ~FLEXCAN_CTRL_CLK_SRC;
1396	priv->write(reg, &regs->ctrl);
1397
1398	err = flexcan_chip_enable(priv);
1399	if (err)
1400		goto out_chip_disable;
1401
1402	/* set freeze, halt and activate FIFO, restrict register access */
1403	reg = priv->read(&regs->mcr);
1404	reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1405		FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1406	priv->write(reg, &regs->mcr);
1407
1408	/* Currently we only support newer versions of this core
1409	 * featuring a RX hardware FIFO (although this driver doesn't
1410	 * make use of it on some cores). Older cores, found on some
1411	 * Coldfire derivates are not tested.
1412	 */
1413	reg = priv->read(&regs->mcr);
1414	if (!(reg & FLEXCAN_MCR_FEN)) {
1415		netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1416		err = -ENODEV;
1417		goto out_chip_disable;
1418	}
1419
1420	err = register_candev(dev);
1421	if (err)
1422		goto out_chip_disable;
1423
1424	/* Disable core and let pm_runtime_put() disable the clocks.
1425	 * If CONFIG_PM is not enabled, the clocks will stay powered.
1426	 */
1427	flexcan_chip_disable(priv);
1428	pm_runtime_put(priv->dev);
1429
1430	return 0;
1431
1432 out_chip_disable:
1433	flexcan_chip_disable(priv);
1434 out_clks_disable:
1435	flexcan_clks_disable(priv);
1436	return err;
1437}
1438
1439static void unregister_flexcandev(struct net_device *dev)
1440{
1441	unregister_candev(dev);
1442}
1443
1444static int flexcan_setup_stop_mode(struct platform_device *pdev)
1445{
1446	struct net_device *dev = platform_get_drvdata(pdev);
1447	struct device_node *np = pdev->dev.of_node;
1448	struct device_node *gpr_np;
1449	struct flexcan_priv *priv;
1450	phandle phandle;
1451	u32 out_val[5];
1452	int ret;
1453
1454	if (!np)
1455		return -EINVAL;
1456
1457	/* stop mode property format is:
1458	 * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1459	 */
1460	ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1461					 ARRAY_SIZE(out_val));
1462	if (ret) {
1463		dev_dbg(&pdev->dev, "no stop-mode property\n");
1464		return ret;
1465	}
1466	phandle = *out_val;
1467
1468	gpr_np = of_find_node_by_phandle(phandle);
1469	if (!gpr_np) {
1470		dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1471		return -ENODEV;
1472	}
1473
1474	priv = netdev_priv(dev);
1475	priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1476	if (IS_ERR(priv->stm.gpr)) {
1477		dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1478		ret = PTR_ERR(priv->stm.gpr);
1479		goto out_put_node;
1480	}
1481
1482	priv->stm.req_gpr = out_val[1];
1483	priv->stm.req_bit = out_val[2];
1484	priv->stm.ack_gpr = out_val[3];
1485	priv->stm.ack_bit = out_val[4];
1486
1487	dev_dbg(&pdev->dev,
1488		"gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1489		gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1490		priv->stm.ack_gpr, priv->stm.ack_bit);
1491
1492	device_set_wakeup_capable(&pdev->dev, true);
1493
1494	if (of_property_read_bool(np, "wakeup-source"))
1495		device_set_wakeup_enable(&pdev->dev, true);
1496
1497	return 0;
1498
1499out_put_node:
1500	of_node_put(gpr_np);
1501	return ret;
1502}
1503
1504static const struct of_device_id flexcan_of_match[] = {
1505	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1506	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1507	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1508	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1509	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1510	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1511	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1512	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1513	{ /* sentinel */ },
1514};
1515MODULE_DEVICE_TABLE(of, flexcan_of_match);
1516
1517static const struct platform_device_id flexcan_id_table[] = {
1518	{ .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1519	{ /* sentinel */ },
1520};
1521MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1522
1523static int flexcan_probe(struct platform_device *pdev)
1524{
1525	const struct of_device_id *of_id;
1526	const struct flexcan_devtype_data *devtype_data;
1527	struct net_device *dev;
1528	struct flexcan_priv *priv;
1529	struct regulator *reg_xceiver;
1530	struct resource *mem;
1531	struct clk *clk_ipg = NULL, *clk_per = NULL;
1532	struct flexcan_regs __iomem *regs;
1533	int err, irq;
1534	u8 clk_src = 1;
1535	u32 clock_freq = 0;
1536
1537	reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1538	if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1539		return -EPROBE_DEFER;
1540	else if (IS_ERR(reg_xceiver))
1541		reg_xceiver = NULL;
1542
1543	if (pdev->dev.of_node) {
1544		of_property_read_u32(pdev->dev.of_node,
1545				     "clock-frequency", &clock_freq);
1546		of_property_read_u8(pdev->dev.of_node,
1547				    "fsl,clk-source", &clk_src);
1548	}
1549
1550	if (!clock_freq) {
1551		clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1552		if (IS_ERR(clk_ipg)) {
1553			dev_err(&pdev->dev, "no ipg clock defined\n");
1554			return PTR_ERR(clk_ipg);
1555		}
1556
1557		clk_per = devm_clk_get(&pdev->dev, "per");
1558		if (IS_ERR(clk_per)) {
1559			dev_err(&pdev->dev, "no per clock defined\n");
1560			return PTR_ERR(clk_per);
1561		}
1562		clock_freq = clk_get_rate(clk_per);
1563	}
1564
1565	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1566	irq = platform_get_irq(pdev, 0);
1567	if (irq <= 0)
1568		return -ENODEV;
1569
1570	regs = devm_ioremap_resource(&pdev->dev, mem);
1571	if (IS_ERR(regs))
1572		return PTR_ERR(regs);
1573
1574	of_id = of_match_device(flexcan_of_match, &pdev->dev);
1575	if (of_id) {
1576		devtype_data = of_id->data;
1577	} else if (platform_get_device_id(pdev)->driver_data) {
1578		devtype_data = (struct flexcan_devtype_data *)
1579			platform_get_device_id(pdev)->driver_data;
1580	} else {
1581		return -ENODEV;
1582	}
1583
1584	dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1585	if (!dev)
1586		return -ENOMEM;
1587
1588	platform_set_drvdata(pdev, dev);
1589	SET_NETDEV_DEV(dev, &pdev->dev);
1590
1591	dev->netdev_ops = &flexcan_netdev_ops;
1592	dev->irq = irq;
1593	dev->flags |= IFF_ECHO;
1594
1595	priv = netdev_priv(dev);
1596
1597	if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1598	    devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1599		priv->read = flexcan_read_be;
1600		priv->write = flexcan_write_be;
1601	} else {
1602		priv->read = flexcan_read_le;
1603		priv->write = flexcan_write_le;
1604	}
1605
1606	priv->dev = &pdev->dev;
1607	priv->can.clock.freq = clock_freq;
1608	priv->can.bittiming_const = &flexcan_bittiming_const;
1609	priv->can.do_set_mode = flexcan_set_mode;
1610	priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1611	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1612		CAN_CTRLMODE_LISTENONLY	| CAN_CTRLMODE_3_SAMPLES |
1613		CAN_CTRLMODE_BERR_REPORTING;
1614	priv->regs = regs;
1615	priv->clk_ipg = clk_ipg;
1616	priv->clk_per = clk_per;
1617	priv->clk_src = clk_src;
1618	priv->devtype_data = devtype_data;
1619	priv->reg_xceiver = reg_xceiver;
1620
1621	pm_runtime_get_noresume(&pdev->dev);
1622	pm_runtime_set_active(&pdev->dev);
1623	pm_runtime_enable(&pdev->dev);
1624
1625	err = register_flexcandev(dev);
1626	if (err) {
1627		dev_err(&pdev->dev, "registering netdev failed\n");
1628		goto failed_register;
1629	}
1630
1631	devm_can_led_init(dev);
1632
1633	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1634		err = flexcan_setup_stop_mode(pdev);
1635		if (err)
1636			dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1637	}
1638
1639	return 0;
1640
1641 failed_register:
1642	free_candev(dev);
1643	return err;
1644}
1645
1646static int flexcan_remove(struct platform_device *pdev)
1647{
1648	struct net_device *dev = platform_get_drvdata(pdev);
1649
1650	unregister_flexcandev(dev);
1651	pm_runtime_disable(&pdev->dev);
1652	free_candev(dev);
1653
1654	return 0;
1655}
1656
1657static int __maybe_unused flexcan_suspend(struct device *device)
1658{
1659	struct net_device *dev = dev_get_drvdata(device);
1660	struct flexcan_priv *priv = netdev_priv(dev);
1661	int err = 0;
1662
1663	if (netif_running(dev)) {
1664		/* if wakeup is enabled, enter stop mode
1665		 * else enter disabled mode.
1666		 */
1667		if (device_may_wakeup(device)) {
1668			enable_irq_wake(dev->irq);
1669			err = flexcan_enter_stop_mode(priv);
1670			if (err)
1671				return err;
1672		} else {
1673			err = flexcan_chip_disable(priv);
1674			if (err)
1675				return err;
1676
1677			err = pm_runtime_force_suspend(device);
1678		}
1679		netif_stop_queue(dev);
1680		netif_device_detach(dev);
1681	}
1682	priv->can.state = CAN_STATE_SLEEPING;
1683
1684	return err;
1685}
1686
1687static int __maybe_unused flexcan_resume(struct device *device)
1688{
1689	struct net_device *dev = dev_get_drvdata(device);
1690	struct flexcan_priv *priv = netdev_priv(dev);
1691	int err = 0;
1692
1693	priv->can.state = CAN_STATE_ERROR_ACTIVE;
1694	if (netif_running(dev)) {
1695		netif_device_attach(dev);
1696		netif_start_queue(dev);
1697		if (device_may_wakeup(device)) {
1698			disable_irq_wake(dev->irq);
1699		} else {
1700			err = pm_runtime_force_resume(device);
1701			if (err)
1702				return err;
1703
1704			err = flexcan_chip_enable(priv);
1705		}
1706	}
1707
1708	return err;
1709}
1710
1711static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1712{
1713	struct net_device *dev = dev_get_drvdata(device);
1714	struct flexcan_priv *priv = netdev_priv(dev);
1715
1716	flexcan_clks_disable(priv);
1717
1718	return 0;
1719}
1720
1721static int __maybe_unused flexcan_runtime_resume(struct device *device)
1722{
1723	struct net_device *dev = dev_get_drvdata(device);
1724	struct flexcan_priv *priv = netdev_priv(dev);
1725
1726	return flexcan_clks_enable(priv);
1727}
1728
1729static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1730{
1731	struct net_device *dev = dev_get_drvdata(device);
1732	struct flexcan_priv *priv = netdev_priv(dev);
1733
1734	if (netif_running(dev) && device_may_wakeup(device))
1735		flexcan_enable_wakeup_irq(priv, true);
1736
1737	return 0;
1738}
1739
1740static int __maybe_unused flexcan_noirq_resume(struct device *device)
1741{
1742	struct net_device *dev = dev_get_drvdata(device);
1743	struct flexcan_priv *priv = netdev_priv(dev);
1744	int err;
1745
1746	if (netif_running(dev) && device_may_wakeup(device)) {
1747		flexcan_enable_wakeup_irq(priv, false);
1748		err = flexcan_exit_stop_mode(priv);
1749		if (err)
1750			return err;
1751	}
1752
1753	return 0;
1754}
1755
1756static const struct dev_pm_ops flexcan_pm_ops = {
1757	SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1758	SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1759	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1760};
1761
1762static struct platform_driver flexcan_driver = {
1763	.driver = {
1764		.name = DRV_NAME,
1765		.pm = &flexcan_pm_ops,
1766		.of_match_table = flexcan_of_match,
1767	},
1768	.probe = flexcan_probe,
1769	.remove = flexcan_remove,
1770	.id_table = flexcan_id_table,
1771};
1772
1773module_platform_driver(flexcan_driver);
1774
1775MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1776	      "Marc Kleine-Budde <kernel@pengutronix.de>");
1777MODULE_LICENSE("GPL v2");
1778MODULE_DESCRIPTION("CAN port driver for flexcan based chip");