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/drivers/net/can/ti_hecc.c

https://codeberg.org/ddevault/linux
C | 985 lines | 736 code | 148 blank | 101 comment | 81 complexity | 451bca3b25d623e887c2b7868b7ee89d MD5 | raw file
Possible License(s): GPL-2.0
  1. /*
  2. * TI HECC (CAN) device driver
  3. *
  4. * This driver supports TI's HECC (High End CAN Controller module) and the
  5. * specs for the same is available at <http://www.ti.com>
  6. *
  7. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  8. * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com>
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation version 2.
  13. *
  14. * This program is distributed as is WITHOUT ANY WARRANTY of any
  15. * kind, whether express or implied; without even the implied warranty
  16. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. */
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/types.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/errno.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/skbuff.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/clk.h>
  29. #include <linux/io.h>
  30. #include <linux/of.h>
  31. #include <linux/of_device.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/can/dev.h>
  34. #include <linux/can/error.h>
  35. #include <linux/can/led.h>
  36. #include <linux/can/rx-offload.h>
  37. #define DRV_NAME "ti_hecc"
  38. #define HECC_MODULE_VERSION "0.7"
  39. MODULE_VERSION(HECC_MODULE_VERSION);
  40. #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
  41. /* TX / RX Mailbox Configuration */
  42. #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
  43. #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
  44. /* Important Note: TX mailbox configuration
  45. * TX mailboxes should be restricted to the number of SKB buffers to avoid
  46. * maintaining SKB buffers separately. TX mailboxes should be a power of 2
  47. * for the mailbox logic to work. Top mailbox numbers are reserved for RX
  48. * and lower mailboxes for TX.
  49. *
  50. * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT
  51. * 4 (default) 2
  52. * 8 3
  53. * 16 4
  54. */
  55. #define HECC_MB_TX_SHIFT 2 /* as per table above */
  56. #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT)
  57. #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT)
  58. #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
  59. #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
  60. #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
  61. /* RX mailbox configuration
  62. *
  63. * The remaining mailboxes are used for reception and are delivered
  64. * based on their timestamp, to avoid a hardware race when CANME is
  65. * changed while CAN-bus traffic is being received.
  66. */
  67. #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
  68. #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
  69. /* TI HECC module registers */
  70. #define HECC_CANME 0x0 /* Mailbox enable */
  71. #define HECC_CANMD 0x4 /* Mailbox direction */
  72. #define HECC_CANTRS 0x8 /* Transmit request set */
  73. #define HECC_CANTRR 0xC /* Transmit request */
  74. #define HECC_CANTA 0x10 /* Transmission acknowledge */
  75. #define HECC_CANAA 0x14 /* Abort acknowledge */
  76. #define HECC_CANRMP 0x18 /* Receive message pending */
  77. #define HECC_CANRML 0x1C /* Remote message lost */
  78. #define HECC_CANRFP 0x20 /* Remote frame pending */
  79. #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */
  80. #define HECC_CANMC 0x28 /* Master control */
  81. #define HECC_CANBTC 0x2C /* Bit timing configuration */
  82. #define HECC_CANES 0x30 /* Error and status */
  83. #define HECC_CANTEC 0x34 /* Transmit error counter */
  84. #define HECC_CANREC 0x38 /* Receive error counter */
  85. #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */
  86. #define HECC_CANGIM 0x40 /* Global interrupt mask */
  87. #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */
  88. #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */
  89. #define HECC_CANMIL 0x4C /* Mailbox interrupt level */
  90. #define HECC_CANOPC 0x50 /* Overwrite protection control */
  91. #define HECC_CANTIOC 0x54 /* Transmit I/O control */
  92. #define HECC_CANRIOC 0x58 /* Receive I/O control */
  93. #define HECC_CANLNT 0x5C /* HECC only: Local network time */
  94. #define HECC_CANTOC 0x60 /* HECC only: Time-out control */
  95. #define HECC_CANTOS 0x64 /* HECC only: Time-out status */
  96. #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */
  97. #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */
  98. /* TI HECC RAM registers */
  99. #define HECC_CANMOTS 0x80 /* Message object time stamp */
  100. /* Mailbox registers */
  101. #define HECC_CANMID 0x0
  102. #define HECC_CANMCF 0x4
  103. #define HECC_CANMDL 0x8
  104. #define HECC_CANMDH 0xC
  105. #define HECC_SET_REG 0xFFFFFFFF
  106. #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */
  107. #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */
  108. #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */
  109. #define HECC_CANMC_CCR BIT(12) /* Change config request */
  110. #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
  111. #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */
  112. #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
  113. #define HECC_CANMC_SRES BIT(5) /* Software reset */
  114. #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */
  115. #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */
  116. #define HECC_CANMID_IDE BIT(31) /* Extended frame format */
  117. #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */
  118. #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */
  119. #define HECC_CANES_FE BIT(24) /* form error */
  120. #define HECC_CANES_BE BIT(23) /* bit error */
  121. #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */
  122. #define HECC_CANES_CRCE BIT(21) /* CRC error */
  123. #define HECC_CANES_SE BIT(20) /* stuff bit error */
  124. #define HECC_CANES_ACKE BIT(19) /* ack error */
  125. #define HECC_CANES_BO BIT(18) /* Bus off status */
  126. #define HECC_CANES_EP BIT(17) /* Error passive status */
  127. #define HECC_CANES_EW BIT(16) /* Error warning status */
  128. #define HECC_CANES_SMA BIT(5) /* suspend mode ack */
  129. #define HECC_CANES_CCE BIT(4) /* Change config enabled */
  130. #define HECC_CANES_PDA BIT(3) /* Power down mode ack */
  131. #define HECC_CANBTC_SAM BIT(7) /* sample points */
  132. #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\
  133. HECC_CANES_CRCE | HECC_CANES_SE |\
  134. HECC_CANES_ACKE)
  135. #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */
  136. #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */
  137. #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */
  138. #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */
  139. #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */
  140. #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */
  141. #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */
  142. #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */
  143. #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */
  144. #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */
  145. #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */
  146. #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */
  147. #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */
  148. #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */
  149. #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */
  150. #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */
  151. /* CAN Bittiming constants as per HECC specs */
  152. static const struct can_bittiming_const ti_hecc_bittiming_const = {
  153. .name = DRV_NAME,
  154. .tseg1_min = 1,
  155. .tseg1_max = 16,
  156. .tseg2_min = 1,
  157. .tseg2_max = 8,
  158. .sjw_max = 4,
  159. .brp_min = 1,
  160. .brp_max = 256,
  161. .brp_inc = 1,
  162. };
  163. struct ti_hecc_priv {
  164. struct can_priv can; /* MUST be first member/field */
  165. struct can_rx_offload offload;
  166. struct net_device *ndev;
  167. struct clk *clk;
  168. void __iomem *base;
  169. void __iomem *hecc_ram;
  170. void __iomem *mbx;
  171. bool use_hecc1int;
  172. spinlock_t mbx_lock; /* CANME register needs protection */
  173. u32 tx_head;
  174. u32 tx_tail;
  175. struct regulator *reg_xceiver;
  176. };
  177. static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
  178. {
  179. return priv->tx_head & HECC_TX_MB_MASK;
  180. }
  181. static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
  182. {
  183. return priv->tx_tail & HECC_TX_MB_MASK;
  184. }
  185. static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
  186. {
  187. return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
  188. }
  189. static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
  190. {
  191. __raw_writel(val, priv->hecc_ram + mbxno * 4);
  192. }
  193. static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno)
  194. {
  195. return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4);
  196. }
  197. static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
  198. u32 reg, u32 val)
  199. {
  200. __raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
  201. }
  202. static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
  203. {
  204. return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
  205. }
  206. static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
  207. {
  208. __raw_writel(val, priv->base + reg);
  209. }
  210. static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
  211. {
  212. return __raw_readl(priv->base + reg);
  213. }
  214. static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
  215. u32 bit_mask)
  216. {
  217. hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
  218. }
  219. static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
  220. u32 bit_mask)
  221. {
  222. hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
  223. }
  224. static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
  225. {
  226. return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
  227. }
  228. static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
  229. {
  230. struct can_bittiming *bit_timing = &priv->can.bittiming;
  231. u32 can_btc;
  232. can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
  233. can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
  234. & 0xF) << 3;
  235. if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
  236. if (bit_timing->brp > 4)
  237. can_btc |= HECC_CANBTC_SAM;
  238. else
  239. netdev_warn(priv->ndev,
  240. "WARN: Triple sampling not set due to h/w limitations");
  241. }
  242. can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
  243. can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
  244. /* ERM being set to 0 by default meaning resync at falling edge */
  245. hecc_write(priv, HECC_CANBTC, can_btc);
  246. netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
  247. return 0;
  248. }
  249. static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
  250. int on)
  251. {
  252. if (!priv->reg_xceiver)
  253. return 0;
  254. if (on)
  255. return regulator_enable(priv->reg_xceiver);
  256. else
  257. return regulator_disable(priv->reg_xceiver);
  258. }
  259. static void ti_hecc_reset(struct net_device *ndev)
  260. {
  261. u32 cnt;
  262. struct ti_hecc_priv *priv = netdev_priv(ndev);
  263. netdev_dbg(ndev, "resetting hecc ...\n");
  264. hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
  265. /* Set change control request and wait till enabled */
  266. hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
  267. /* INFO: It has been observed that at times CCE bit may not be
  268. * set and hw seems to be ok even if this bit is not set so
  269. * timing out with a timing of 1ms to respect the specs
  270. */
  271. cnt = HECC_CCE_WAIT_COUNT;
  272. while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
  273. --cnt;
  274. udelay(10);
  275. }
  276. /* Note: On HECC, BTC can be programmed only in initialization mode, so
  277. * it is expected that the can bittiming parameters are set via ip
  278. * utility before the device is opened
  279. */
  280. ti_hecc_set_btc(priv);
  281. /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
  282. hecc_write(priv, HECC_CANMC, 0);
  283. /* INFO: CAN net stack handles bus off and hence disabling auto-bus-on
  284. * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
  285. */
  286. /* INFO: It has been observed that at times CCE bit may not be
  287. * set and hw seems to be ok even if this bit is not set so
  288. */
  289. cnt = HECC_CCE_WAIT_COUNT;
  290. while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
  291. --cnt;
  292. udelay(10);
  293. }
  294. /* Enable TX and RX I/O Control pins */
  295. hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
  296. hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
  297. /* Clear registers for clean operation */
  298. hecc_write(priv, HECC_CANTA, HECC_SET_REG);
  299. hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
  300. hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
  301. hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
  302. hecc_write(priv, HECC_CANME, 0);
  303. hecc_write(priv, HECC_CANMD, 0);
  304. /* SCC compat mode NOT supported (and not needed too) */
  305. hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
  306. }
  307. static void ti_hecc_start(struct net_device *ndev)
  308. {
  309. struct ti_hecc_priv *priv = netdev_priv(ndev);
  310. u32 cnt, mbxno, mbx_mask;
  311. /* put HECC in initialization mode and set btc */
  312. ti_hecc_reset(ndev);
  313. priv->tx_head = HECC_TX_MASK;
  314. priv->tx_tail = HECC_TX_MASK;
  315. /* Enable local and global acceptance mask registers */
  316. hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
  317. /* Prepare configured mailboxes to receive messages */
  318. for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
  319. mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
  320. mbx_mask = BIT(mbxno);
  321. hecc_clear_bit(priv, HECC_CANME, mbx_mask);
  322. hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
  323. hecc_write_lam(priv, mbxno, HECC_SET_REG);
  324. hecc_set_bit(priv, HECC_CANMD, mbx_mask);
  325. hecc_set_bit(priv, HECC_CANME, mbx_mask);
  326. hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
  327. }
  328. /* Prevent message over-write & Enable interrupts */
  329. hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
  330. if (priv->use_hecc1int) {
  331. hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
  332. hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
  333. HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
  334. } else {
  335. hecc_write(priv, HECC_CANMIL, 0);
  336. hecc_write(priv, HECC_CANGIM,
  337. HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
  338. }
  339. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  340. }
  341. static void ti_hecc_stop(struct net_device *ndev)
  342. {
  343. struct ti_hecc_priv *priv = netdev_priv(ndev);
  344. /* Disable interrupts and disable mailboxes */
  345. hecc_write(priv, HECC_CANGIM, 0);
  346. hecc_write(priv, HECC_CANMIM, 0);
  347. hecc_write(priv, HECC_CANME, 0);
  348. priv->can.state = CAN_STATE_STOPPED;
  349. }
  350. static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
  351. {
  352. int ret = 0;
  353. switch (mode) {
  354. case CAN_MODE_START:
  355. ti_hecc_start(ndev);
  356. netif_wake_queue(ndev);
  357. break;
  358. default:
  359. ret = -EOPNOTSUPP;
  360. break;
  361. }
  362. return ret;
  363. }
  364. static int ti_hecc_get_berr_counter(const struct net_device *ndev,
  365. struct can_berr_counter *bec)
  366. {
  367. struct ti_hecc_priv *priv = netdev_priv(ndev);
  368. bec->txerr = hecc_read(priv, HECC_CANTEC);
  369. bec->rxerr = hecc_read(priv, HECC_CANREC);
  370. return 0;
  371. }
  372. /* ti_hecc_xmit: HECC Transmit
  373. *
  374. * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
  375. * priority of the mailbox for tranmission is dependent upon priority setting
  376. * field in mailbox registers. The mailbox with highest value in priority field
  377. * is transmitted first. Only when two mailboxes have the same value in
  378. * priority field the highest numbered mailbox is transmitted first.
  379. *
  380. * To utilize the HECC priority feature as described above we start with the
  381. * highest numbered mailbox with highest priority level and move on to the next
  382. * mailbox with the same priority level and so on. Once we loop through all the
  383. * transmit mailboxes we choose the next priority level (lower) and so on
  384. * until we reach the lowest priority level on the lowest numbered mailbox
  385. * when we stop transmission until all mailboxes are transmitted and then
  386. * restart at highest numbered mailbox with highest priority.
  387. *
  388. * Two counters (head and tail) are used to track the next mailbox to transmit
  389. * and to track the echo buffer for already transmitted mailbox. The queue
  390. * is stopped when all the mailboxes are busy or when there is a priority
  391. * value roll-over happens.
  392. */
  393. static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
  394. {
  395. struct ti_hecc_priv *priv = netdev_priv(ndev);
  396. struct can_frame *cf = (struct can_frame *)skb->data;
  397. u32 mbxno, mbx_mask, data;
  398. unsigned long flags;
  399. if (can_dropped_invalid_skb(ndev, skb))
  400. return NETDEV_TX_OK;
  401. mbxno = get_tx_head_mb(priv);
  402. mbx_mask = BIT(mbxno);
  403. spin_lock_irqsave(&priv->mbx_lock, flags);
  404. if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
  405. spin_unlock_irqrestore(&priv->mbx_lock, flags);
  406. netif_stop_queue(ndev);
  407. netdev_err(priv->ndev,
  408. "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
  409. priv->tx_head, priv->tx_tail);
  410. return NETDEV_TX_BUSY;
  411. }
  412. spin_unlock_irqrestore(&priv->mbx_lock, flags);
  413. /* Prepare mailbox for transmission */
  414. data = cf->can_dlc | (get_tx_head_prio(priv) << 8);
  415. if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
  416. data |= HECC_CANMCF_RTR;
  417. hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
  418. if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
  419. data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
  420. else /* Standard frame format */
  421. data = (cf->can_id & CAN_SFF_MASK) << 18;
  422. hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
  423. hecc_write_mbx(priv, mbxno, HECC_CANMDL,
  424. be32_to_cpu(*(__be32 *)(cf->data)));
  425. if (cf->can_dlc > 4)
  426. hecc_write_mbx(priv, mbxno, HECC_CANMDH,
  427. be32_to_cpu(*(__be32 *)(cf->data + 4)));
  428. else
  429. *(u32 *)(cf->data + 4) = 0;
  430. can_put_echo_skb(skb, ndev, mbxno);
  431. spin_lock_irqsave(&priv->mbx_lock, flags);
  432. --priv->tx_head;
  433. if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
  434. (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
  435. netif_stop_queue(ndev);
  436. }
  437. hecc_set_bit(priv, HECC_CANME, mbx_mask);
  438. spin_unlock_irqrestore(&priv->mbx_lock, flags);
  439. hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
  440. hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
  441. hecc_write(priv, HECC_CANTRS, mbx_mask);
  442. return NETDEV_TX_OK;
  443. }
  444. static inline
  445. struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)
  446. {
  447. return container_of(offload, struct ti_hecc_priv, offload);
  448. }
  449. static unsigned int ti_hecc_mailbox_read(struct can_rx_offload *offload,
  450. struct can_frame *cf,
  451. u32 *timestamp, unsigned int mbxno)
  452. {
  453. struct ti_hecc_priv *priv = rx_offload_to_priv(offload);
  454. u32 data;
  455. data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
  456. if (data & HECC_CANMID_IDE)
  457. cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
  458. else
  459. cf->can_id = (data >> 18) & CAN_SFF_MASK;
  460. data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
  461. if (data & HECC_CANMCF_RTR)
  462. cf->can_id |= CAN_RTR_FLAG;
  463. cf->can_dlc = get_can_dlc(data & 0xF);
  464. data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
  465. *(__be32 *)(cf->data) = cpu_to_be32(data);
  466. if (cf->can_dlc > 4) {
  467. data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
  468. *(__be32 *)(cf->data + 4) = cpu_to_be32(data);
  469. }
  470. *timestamp = hecc_read_stamp(priv, mbxno);
  471. return 1;
  472. }
  473. static int ti_hecc_error(struct net_device *ndev, int int_status,
  474. int err_status)
  475. {
  476. struct ti_hecc_priv *priv = netdev_priv(ndev);
  477. struct can_frame *cf;
  478. struct sk_buff *skb;
  479. u32 timestamp;
  480. /* propagate the error condition to the can stack */
  481. skb = alloc_can_err_skb(ndev, &cf);
  482. if (!skb) {
  483. if (printk_ratelimit())
  484. netdev_err(priv->ndev,
  485. "%s: alloc_can_err_skb() failed\n",
  486. __func__);
  487. return -ENOMEM;
  488. }
  489. if (int_status & HECC_CANGIF_WLIF) { /* warning level int */
  490. if ((int_status & HECC_CANGIF_BOIF) == 0) {
  491. priv->can.state = CAN_STATE_ERROR_WARNING;
  492. ++priv->can.can_stats.error_warning;
  493. cf->can_id |= CAN_ERR_CRTL;
  494. if (hecc_read(priv, HECC_CANTEC) > 96)
  495. cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
  496. if (hecc_read(priv, HECC_CANREC) > 96)
  497. cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
  498. }
  499. hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);
  500. netdev_dbg(priv->ndev, "Error Warning interrupt\n");
  501. hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
  502. }
  503. if (int_status & HECC_CANGIF_EPIF) { /* error passive int */
  504. if ((int_status & HECC_CANGIF_BOIF) == 0) {
  505. priv->can.state = CAN_STATE_ERROR_PASSIVE;
  506. ++priv->can.can_stats.error_passive;
  507. cf->can_id |= CAN_ERR_CRTL;
  508. if (hecc_read(priv, HECC_CANTEC) > 127)
  509. cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
  510. if (hecc_read(priv, HECC_CANREC) > 127)
  511. cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
  512. }
  513. hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);
  514. netdev_dbg(priv->ndev, "Error passive interrupt\n");
  515. hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
  516. }
  517. /* Need to check busoff condition in error status register too to
  518. * ensure warning interrupts don't hog the system
  519. */
  520. if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
  521. priv->can.state = CAN_STATE_BUS_OFF;
  522. cf->can_id |= CAN_ERR_BUSOFF;
  523. hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);
  524. hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
  525. /* Disable all interrupts in bus-off to avoid int hog */
  526. hecc_write(priv, HECC_CANGIM, 0);
  527. ++priv->can.can_stats.bus_off;
  528. can_bus_off(ndev);
  529. }
  530. if (err_status & HECC_BUS_ERROR) {
  531. ++priv->can.can_stats.bus_error;
  532. cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
  533. if (err_status & HECC_CANES_FE) {
  534. hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);
  535. cf->data[2] |= CAN_ERR_PROT_FORM;
  536. }
  537. if (err_status & HECC_CANES_BE) {
  538. hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);
  539. cf->data[2] |= CAN_ERR_PROT_BIT;
  540. }
  541. if (err_status & HECC_CANES_SE) {
  542. hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);
  543. cf->data[2] |= CAN_ERR_PROT_STUFF;
  544. }
  545. if (err_status & HECC_CANES_CRCE) {
  546. hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);
  547. cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
  548. }
  549. if (err_status & HECC_CANES_ACKE) {
  550. hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);
  551. cf->data[3] = CAN_ERR_PROT_LOC_ACK;
  552. }
  553. }
  554. timestamp = hecc_read(priv, HECC_CANLNT);
  555. can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
  556. return 0;
  557. }
  558. static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
  559. {
  560. struct net_device *ndev = (struct net_device *)dev_id;
  561. struct ti_hecc_priv *priv = netdev_priv(ndev);
  562. struct net_device_stats *stats = &ndev->stats;
  563. u32 mbxno, mbx_mask, int_status, err_status, stamp;
  564. unsigned long flags, rx_pending;
  565. int_status = hecc_read(priv,
  566. priv->use_hecc1int ?
  567. HECC_CANGIF1 : HECC_CANGIF0);
  568. if (!int_status)
  569. return IRQ_NONE;
  570. err_status = hecc_read(priv, HECC_CANES);
  571. if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
  572. HECC_CANES_EP | HECC_CANES_EW))
  573. ti_hecc_error(ndev, int_status, err_status);
  574. if (int_status & HECC_CANGIF_GMIF) {
  575. while (priv->tx_tail - priv->tx_head > 0) {
  576. mbxno = get_tx_tail_mb(priv);
  577. mbx_mask = BIT(mbxno);
  578. if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
  579. break;
  580. hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
  581. hecc_write(priv, HECC_CANTA, mbx_mask);
  582. spin_lock_irqsave(&priv->mbx_lock, flags);
  583. hecc_clear_bit(priv, HECC_CANME, mbx_mask);
  584. spin_unlock_irqrestore(&priv->mbx_lock, flags);
  585. stamp = hecc_read_stamp(priv, mbxno);
  586. stats->tx_bytes +=
  587. can_rx_offload_get_echo_skb(&priv->offload,
  588. mbxno, stamp);
  589. stats->tx_packets++;
  590. can_led_event(ndev, CAN_LED_EVENT_TX);
  591. --priv->tx_tail;
  592. }
  593. /* restart queue if wrap-up or if queue stalled on last pkt */
  594. if ((priv->tx_head == priv->tx_tail &&
  595. ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
  596. (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
  597. ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
  598. netif_wake_queue(ndev);
  599. /* offload RX mailboxes and let NAPI deliver them */
  600. while ((rx_pending = hecc_read(priv, HECC_CANRMP))) {
  601. can_rx_offload_irq_offload_timestamp(&priv->offload,
  602. rx_pending);
  603. hecc_write(priv, HECC_CANRMP, rx_pending);
  604. }
  605. }
  606. /* clear all interrupt conditions - read back to avoid spurious ints */
  607. if (priv->use_hecc1int) {
  608. hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
  609. int_status = hecc_read(priv, HECC_CANGIF1);
  610. } else {
  611. hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
  612. int_status = hecc_read(priv, HECC_CANGIF0);
  613. }
  614. return IRQ_HANDLED;
  615. }
  616. static int ti_hecc_open(struct net_device *ndev)
  617. {
  618. struct ti_hecc_priv *priv = netdev_priv(ndev);
  619. int err;
  620. err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
  621. ndev->name, ndev);
  622. if (err) {
  623. netdev_err(ndev, "error requesting interrupt\n");
  624. return err;
  625. }
  626. ti_hecc_transceiver_switch(priv, 1);
  627. /* Open common can device */
  628. err = open_candev(ndev);
  629. if (err) {
  630. netdev_err(ndev, "open_candev() failed %d\n", err);
  631. ti_hecc_transceiver_switch(priv, 0);
  632. free_irq(ndev->irq, ndev);
  633. return err;
  634. }
  635. can_led_event(ndev, CAN_LED_EVENT_OPEN);
  636. ti_hecc_start(ndev);
  637. can_rx_offload_enable(&priv->offload);
  638. netif_start_queue(ndev);
  639. return 0;
  640. }
  641. static int ti_hecc_close(struct net_device *ndev)
  642. {
  643. struct ti_hecc_priv *priv = netdev_priv(ndev);
  644. netif_stop_queue(ndev);
  645. can_rx_offload_disable(&priv->offload);
  646. ti_hecc_stop(ndev);
  647. free_irq(ndev->irq, ndev);
  648. close_candev(ndev);
  649. ti_hecc_transceiver_switch(priv, 0);
  650. can_led_event(ndev, CAN_LED_EVENT_STOP);
  651. return 0;
  652. }
  653. static const struct net_device_ops ti_hecc_netdev_ops = {
  654. .ndo_open = ti_hecc_open,
  655. .ndo_stop = ti_hecc_close,
  656. .ndo_start_xmit = ti_hecc_xmit,
  657. .ndo_change_mtu = can_change_mtu,
  658. };
  659. static const struct of_device_id ti_hecc_dt_ids[] = {
  660. {
  661. .compatible = "ti,am3517-hecc",
  662. },
  663. { }
  664. };
  665. MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
  666. static int ti_hecc_probe(struct platform_device *pdev)
  667. {
  668. struct net_device *ndev = (struct net_device *)0;
  669. struct ti_hecc_priv *priv;
  670. struct device_node *np = pdev->dev.of_node;
  671. struct resource *res, *irq;
  672. struct regulator *reg_xceiver;
  673. int err = -ENODEV;
  674. if (!IS_ENABLED(CONFIG_OF) || !np)
  675. return -EINVAL;
  676. reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
  677. if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
  678. return -EPROBE_DEFER;
  679. else if (IS_ERR(reg_xceiver))
  680. reg_xceiver = NULL;
  681. ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
  682. if (!ndev) {
  683. dev_err(&pdev->dev, "alloc_candev failed\n");
  684. return -ENOMEM;
  685. }
  686. priv = netdev_priv(ndev);
  687. /* handle hecc memory */
  688. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc");
  689. if (!res) {
  690. dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc\n");
  691. return -EINVAL;
  692. }
  693. priv->base = devm_ioremap_resource(&pdev->dev, res);
  694. if (IS_ERR(priv->base)) {
  695. dev_err(&pdev->dev, "hecc ioremap failed\n");
  696. return PTR_ERR(priv->base);
  697. }
  698. /* handle hecc-ram memory */
  699. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc-ram");
  700. if (!res) {
  701. dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc-ram\n");
  702. return -EINVAL;
  703. }
  704. priv->hecc_ram = devm_ioremap_resource(&pdev->dev, res);
  705. if (IS_ERR(priv->hecc_ram)) {
  706. dev_err(&pdev->dev, "hecc-ram ioremap failed\n");
  707. return PTR_ERR(priv->hecc_ram);
  708. }
  709. /* handle mbx memory */
  710. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbx");
  711. if (!res) {
  712. dev_err(&pdev->dev, "can't get IORESOURCE_MEM mbx\n");
  713. return -EINVAL;
  714. }
  715. priv->mbx = devm_ioremap_resource(&pdev->dev, res);
  716. if (IS_ERR(priv->mbx)) {
  717. dev_err(&pdev->dev, "mbx ioremap failed\n");
  718. return PTR_ERR(priv->mbx);
  719. }
  720. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  721. if (!irq) {
  722. dev_err(&pdev->dev, "No irq resource\n");
  723. goto probe_exit;
  724. }
  725. priv->ndev = ndev;
  726. priv->reg_xceiver = reg_xceiver;
  727. priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int");
  728. priv->can.bittiming_const = &ti_hecc_bittiming_const;
  729. priv->can.do_set_mode = ti_hecc_do_set_mode;
  730. priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
  731. priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
  732. spin_lock_init(&priv->mbx_lock);
  733. ndev->irq = irq->start;
  734. ndev->flags |= IFF_ECHO;
  735. platform_set_drvdata(pdev, ndev);
  736. SET_NETDEV_DEV(ndev, &pdev->dev);
  737. ndev->netdev_ops = &ti_hecc_netdev_ops;
  738. priv->clk = clk_get(&pdev->dev, "hecc_ck");
  739. if (IS_ERR(priv->clk)) {
  740. dev_err(&pdev->dev, "No clock available\n");
  741. err = PTR_ERR(priv->clk);
  742. priv->clk = NULL;
  743. goto probe_exit_candev;
  744. }
  745. priv->can.clock.freq = clk_get_rate(priv->clk);
  746. err = clk_prepare_enable(priv->clk);
  747. if (err) {
  748. dev_err(&pdev->dev, "clk_prepare_enable() failed\n");
  749. goto probe_exit_clk;
  750. }
  751. priv->offload.mailbox_read = ti_hecc_mailbox_read;
  752. priv->offload.mb_first = HECC_RX_FIRST_MBOX;
  753. priv->offload.mb_last = HECC_MAX_TX_MBOX;
  754. err = can_rx_offload_add_timestamp(ndev, &priv->offload);
  755. if (err) {
  756. dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n");
  757. goto probe_exit_clk;
  758. }
  759. err = register_candev(ndev);
  760. if (err) {
  761. dev_err(&pdev->dev, "register_candev() failed\n");
  762. goto probe_exit_offload;
  763. }
  764. devm_can_led_init(ndev);
  765. dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
  766. priv->base, (u32)ndev->irq);
  767. return 0;
  768. probe_exit_offload:
  769. can_rx_offload_del(&priv->offload);
  770. probe_exit_clk:
  771. clk_put(priv->clk);
  772. probe_exit_candev:
  773. free_candev(ndev);
  774. probe_exit:
  775. return err;
  776. }
  777. static int ti_hecc_remove(struct platform_device *pdev)
  778. {
  779. struct net_device *ndev = platform_get_drvdata(pdev);
  780. struct ti_hecc_priv *priv = netdev_priv(ndev);
  781. unregister_candev(ndev);
  782. clk_disable_unprepare(priv->clk);
  783. clk_put(priv->clk);
  784. can_rx_offload_del(&priv->offload);
  785. free_candev(ndev);
  786. return 0;
  787. }
  788. #ifdef CONFIG_PM
  789. static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
  790. {
  791. struct net_device *dev = platform_get_drvdata(pdev);
  792. struct ti_hecc_priv *priv = netdev_priv(dev);
  793. if (netif_running(dev)) {
  794. netif_stop_queue(dev);
  795. netif_device_detach(dev);
  796. }
  797. hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
  798. priv->can.state = CAN_STATE_SLEEPING;
  799. clk_disable_unprepare(priv->clk);
  800. return 0;
  801. }
  802. static int ti_hecc_resume(struct platform_device *pdev)
  803. {
  804. struct net_device *dev = platform_get_drvdata(pdev);
  805. struct ti_hecc_priv *priv = netdev_priv(dev);
  806. int err;
  807. err = clk_prepare_enable(priv->clk);
  808. if (err)
  809. return err;
  810. hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
  811. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  812. if (netif_running(dev)) {
  813. netif_device_attach(dev);
  814. netif_start_queue(dev);
  815. }
  816. return 0;
  817. }
  818. #else
  819. #define ti_hecc_suspend NULL
  820. #define ti_hecc_resume NULL
  821. #endif
  822. /* TI HECC netdevice driver: platform driver structure */
  823. static struct platform_driver ti_hecc_driver = {
  824. .driver = {
  825. .name = DRV_NAME,
  826. .of_match_table = ti_hecc_dt_ids,
  827. },
  828. .probe = ti_hecc_probe,
  829. .remove = ti_hecc_remove,
  830. .suspend = ti_hecc_suspend,
  831. .resume = ti_hecc_resume,
  832. };
  833. module_platform_driver(ti_hecc_driver);
  834. MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
  835. MODULE_LICENSE("GPL v2");
  836. MODULE_DESCRIPTION(DRV_DESC);
  837. MODULE_ALIAS("platform:" DRV_NAME);