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/drivers/net/can/ti_hecc.c

https://codeberg.org/ddevault/linux
C | 985 lines | 736 code | 148 blank | 101 comment | 81 complexity | 451bca3b25d623e887c2b7868b7ee89d MD5 | raw file
Possible License(s): GPL-2.0
  1/*
  2 * TI HECC (CAN) device driver
  3 *
  4 * This driver supports TI's HECC (High End CAN Controller module) and the
  5 * specs for the same is available at <http://www.ti.com>
  6 *
  7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  8 * Copyright (C) 2019 Jeroen Hofstee <jhofstee@victronenergy.com>
  9 *
 10 * This program is free software; you can redistribute it and/or
 11 * modify it under the terms of the GNU General Public License as
 12 * published by the Free Software Foundation version 2.
 13 *
 14 * This program is distributed as is WITHOUT ANY WARRANTY of any
 15 * kind, whether express or implied; without even the implied warranty
 16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 17 * GNU General Public License for more details.
 18 *
 19 */
 20
 21#include <linux/module.h>
 22#include <linux/kernel.h>
 23#include <linux/types.h>
 24#include <linux/interrupt.h>
 25#include <linux/errno.h>
 26#include <linux/netdevice.h>
 27#include <linux/skbuff.h>
 28#include <linux/platform_device.h>
 29#include <linux/clk.h>
 30#include <linux/io.h>
 31#include <linux/of.h>
 32#include <linux/of_device.h>
 33#include <linux/regulator/consumer.h>
 34
 35#include <linux/can/dev.h>
 36#include <linux/can/error.h>
 37#include <linux/can/led.h>
 38#include <linux/can/rx-offload.h>
 39
 40#define DRV_NAME "ti_hecc"
 41#define HECC_MODULE_VERSION     "0.7"
 42MODULE_VERSION(HECC_MODULE_VERSION);
 43#define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
 44
 45/* TX / RX Mailbox Configuration */
 46#define HECC_MAX_MAILBOXES	32	/* hardware mailboxes - do not change */
 47#define MAX_TX_PRIO		0x3F	/* hardware value - do not change */
 48
 49/* Important Note: TX mailbox configuration
 50 * TX mailboxes should be restricted to the number of SKB buffers to avoid
 51 * maintaining SKB buffers separately. TX mailboxes should be a power of 2
 52 * for the mailbox logic to work.  Top mailbox numbers are reserved for RX
 53 * and lower mailboxes for TX.
 54 *
 55 * HECC_MAX_TX_MBOX	HECC_MB_TX_SHIFT
 56 * 4 (default)		2
 57 * 8			3
 58 * 16			4
 59 */
 60#define HECC_MB_TX_SHIFT	2 /* as per table above */
 61#define HECC_MAX_TX_MBOX	BIT(HECC_MB_TX_SHIFT)
 62
 63#define HECC_TX_PRIO_SHIFT	(HECC_MB_TX_SHIFT)
 64#define HECC_TX_PRIO_MASK	(MAX_TX_PRIO << HECC_MB_TX_SHIFT)
 65#define HECC_TX_MB_MASK		(HECC_MAX_TX_MBOX - 1)
 66#define HECC_TX_MASK		((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
 67
 68/* RX mailbox configuration
 69 *
 70 * The remaining mailboxes are used for reception and are delivered
 71 * based on their timestamp, to avoid a hardware race when CANME is
 72 * changed while CAN-bus traffic is being received.
 73 */
 74#define HECC_MAX_RX_MBOX	(HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
 75#define HECC_RX_FIRST_MBOX	(HECC_MAX_MAILBOXES - 1)
 76
 77/* TI HECC module registers */
 78#define HECC_CANME		0x0	/* Mailbox enable */
 79#define HECC_CANMD		0x4	/* Mailbox direction */
 80#define HECC_CANTRS		0x8	/* Transmit request set */
 81#define HECC_CANTRR		0xC	/* Transmit request */
 82#define HECC_CANTA		0x10	/* Transmission acknowledge */
 83#define HECC_CANAA		0x14	/* Abort acknowledge */
 84#define HECC_CANRMP		0x18	/* Receive message pending */
 85#define HECC_CANRML		0x1C	/* Remote message lost */
 86#define HECC_CANRFP		0x20	/* Remote frame pending */
 87#define HECC_CANGAM		0x24	/* SECC only:Global acceptance mask */
 88#define HECC_CANMC		0x28	/* Master control */
 89#define HECC_CANBTC		0x2C	/* Bit timing configuration */
 90#define HECC_CANES		0x30	/* Error and status */
 91#define HECC_CANTEC		0x34	/* Transmit error counter */
 92#define HECC_CANREC		0x38	/* Receive error counter */
 93#define HECC_CANGIF0		0x3C	/* Global interrupt flag 0 */
 94#define HECC_CANGIM		0x40	/* Global interrupt mask */
 95#define HECC_CANGIF1		0x44	/* Global interrupt flag 1 */
 96#define HECC_CANMIM		0x48	/* Mailbox interrupt mask */
 97#define HECC_CANMIL		0x4C	/* Mailbox interrupt level */
 98#define HECC_CANOPC		0x50	/* Overwrite protection control */
 99#define HECC_CANTIOC		0x54	/* Transmit I/O control */
100#define HECC_CANRIOC		0x58	/* Receive I/O control */
101#define HECC_CANLNT		0x5C	/* HECC only: Local network time */
102#define HECC_CANTOC		0x60	/* HECC only: Time-out control */
103#define HECC_CANTOS		0x64	/* HECC only: Time-out status */
104#define HECC_CANTIOCE		0x68	/* SCC only:Enhanced TX I/O control */
105#define HECC_CANRIOCE		0x6C	/* SCC only:Enhanced RX I/O control */
106
107/* TI HECC RAM registers */
108#define HECC_CANMOTS		0x80	/* Message object time stamp */
109
110/* Mailbox registers */
111#define HECC_CANMID		0x0
112#define HECC_CANMCF		0x4
113#define HECC_CANMDL		0x8
114#define HECC_CANMDH		0xC
115
116#define HECC_SET_REG		0xFFFFFFFF
117#define HECC_CANID_MASK		0x3FF	/* 18 bits mask for extended id's */
118#define HECC_CCE_WAIT_COUNT     100	/* Wait for ~1 sec for CCE bit */
119
120#define HECC_CANMC_SCM		BIT(13)	/* SCC compat mode */
121#define HECC_CANMC_CCR		BIT(12)	/* Change config request */
122#define HECC_CANMC_PDR		BIT(11)	/* Local Power down - for sleep mode */
123#define HECC_CANMC_ABO		BIT(7)	/* Auto Bus On */
124#define HECC_CANMC_STM		BIT(6)	/* Self test mode - loopback */
125#define HECC_CANMC_SRES		BIT(5)	/* Software reset */
126
127#define HECC_CANTIOC_EN		BIT(3)	/* Enable CAN TX I/O pin */
128#define HECC_CANRIOC_EN		BIT(3)	/* Enable CAN RX I/O pin */
129
130#define HECC_CANMID_IDE		BIT(31)	/* Extended frame format */
131#define HECC_CANMID_AME		BIT(30)	/* Acceptance mask enable */
132#define HECC_CANMID_AAM		BIT(29)	/* Auto answer mode */
133
134#define HECC_CANES_FE		BIT(24)	/* form error */
135#define HECC_CANES_BE		BIT(23)	/* bit error */
136#define HECC_CANES_SA1		BIT(22)	/* stuck at dominant error */
137#define HECC_CANES_CRCE		BIT(21)	/* CRC error */
138#define HECC_CANES_SE		BIT(20)	/* stuff bit error */
139#define HECC_CANES_ACKE		BIT(19)	/* ack error */
140#define HECC_CANES_BO		BIT(18)	/* Bus off status */
141#define HECC_CANES_EP		BIT(17)	/* Error passive status */
142#define HECC_CANES_EW		BIT(16)	/* Error warning status */
143#define HECC_CANES_SMA		BIT(5)	/* suspend mode ack */
144#define HECC_CANES_CCE		BIT(4)	/* Change config enabled */
145#define HECC_CANES_PDA		BIT(3)	/* Power down mode ack */
146
147#define HECC_CANBTC_SAM		BIT(7)	/* sample points */
148
149#define HECC_BUS_ERROR		(HECC_CANES_FE | HECC_CANES_BE |\
150				HECC_CANES_CRCE | HECC_CANES_SE |\
151				HECC_CANES_ACKE)
152
153#define HECC_CANMCF_RTR		BIT(4)	/* Remote transmit request */
154
155#define HECC_CANGIF_MAIF	BIT(17)	/* Message alarm interrupt */
156#define HECC_CANGIF_TCOIF	BIT(16) /* Timer counter overflow int */
157#define HECC_CANGIF_GMIF	BIT(15)	/* Global mailbox interrupt */
158#define HECC_CANGIF_AAIF	BIT(14)	/* Abort ack interrupt */
159#define HECC_CANGIF_WDIF	BIT(13)	/* Write denied interrupt */
160#define HECC_CANGIF_WUIF	BIT(12)	/* Wake up interrupt */
161#define HECC_CANGIF_RMLIF	BIT(11)	/* Receive message lost interrupt */
162#define HECC_CANGIF_BOIF	BIT(10)	/* Bus off interrupt */
163#define HECC_CANGIF_EPIF	BIT(9)	/* Error passive interrupt */
164#define HECC_CANGIF_WLIF	BIT(8)	/* Warning level interrupt */
165#define HECC_CANGIF_MBOX_MASK	0x1F	/* Mailbox number mask */
166#define HECC_CANGIM_I1EN	BIT(1)	/* Int line 1 enable */
167#define HECC_CANGIM_I0EN	BIT(0)	/* Int line 0 enable */
168#define HECC_CANGIM_DEF_MASK	0x700	/* only busoff/warning/passive */
169#define HECC_CANGIM_SIL		BIT(2)	/* system interrupts to int line 1 */
170
171/* CAN Bittiming constants as per HECC specs */
172static const struct can_bittiming_const ti_hecc_bittiming_const = {
173	.name = DRV_NAME,
174	.tseg1_min = 1,
175	.tseg1_max = 16,
176	.tseg2_min = 1,
177	.tseg2_max = 8,
178	.sjw_max = 4,
179	.brp_min = 1,
180	.brp_max = 256,
181	.brp_inc = 1,
182};
183
184struct ti_hecc_priv {
185	struct can_priv can;	/* MUST be first member/field */
186	struct can_rx_offload offload;
187	struct net_device *ndev;
188	struct clk *clk;
189	void __iomem *base;
190	void __iomem *hecc_ram;
191	void __iomem *mbx;
192	bool use_hecc1int;
193	spinlock_t mbx_lock; /* CANME register needs protection */
194	u32 tx_head;
195	u32 tx_tail;
196	struct regulator *reg_xceiver;
197};
198
199static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
200{
201	return priv->tx_head & HECC_TX_MB_MASK;
202}
203
204static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
205{
206	return priv->tx_tail & HECC_TX_MB_MASK;
207}
208
209static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
210{
211	return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
212}
213
214static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
215{
216	__raw_writel(val, priv->hecc_ram + mbxno * 4);
217}
218
219static inline u32 hecc_read_stamp(struct ti_hecc_priv *priv, u32 mbxno)
220{
221	return __raw_readl(priv->hecc_ram + HECC_CANMOTS + mbxno * 4);
222}
223
224static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
225				  u32 reg, u32 val)
226{
227	__raw_writel(val, priv->mbx + mbxno * 0x10 + reg);
228}
229
230static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
231{
232	return __raw_readl(priv->mbx + mbxno * 0x10 + reg);
233}
234
235static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
236{
237	__raw_writel(val, priv->base + reg);
238}
239
240static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
241{
242	return __raw_readl(priv->base + reg);
243}
244
245static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
246				u32 bit_mask)
247{
248	hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
249}
250
251static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
252				  u32 bit_mask)
253{
254	hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
255}
256
257static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
258{
259	return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
260}
261
262static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
263{
264	struct can_bittiming *bit_timing = &priv->can.bittiming;
265	u32 can_btc;
266
267	can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
268	can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
269			& 0xF) << 3;
270	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
271		if (bit_timing->brp > 4)
272			can_btc |= HECC_CANBTC_SAM;
273		else
274			netdev_warn(priv->ndev,
275				    "WARN: Triple sampling not set due to h/w limitations");
276	}
277	can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
278	can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
279
280	/* ERM being set to 0 by default meaning resync at falling edge */
281
282	hecc_write(priv, HECC_CANBTC, can_btc);
283	netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
284
285	return 0;
286}
287
288static int ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
289				      int on)
290{
291	if (!priv->reg_xceiver)
292		return 0;
293
294	if (on)
295		return regulator_enable(priv->reg_xceiver);
296	else
297		return regulator_disable(priv->reg_xceiver);
298}
299
300static void ti_hecc_reset(struct net_device *ndev)
301{
302	u32 cnt;
303	struct ti_hecc_priv *priv = netdev_priv(ndev);
304
305	netdev_dbg(ndev, "resetting hecc ...\n");
306	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
307
308	/* Set change control request and wait till enabled */
309	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
310
311	/* INFO: It has been observed that at times CCE bit may not be
312	 * set and hw seems to be ok even if this bit is not set so
313	 * timing out with a timing of 1ms to respect the specs
314	 */
315	cnt = HECC_CCE_WAIT_COUNT;
316	while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
317		--cnt;
318		udelay(10);
319	}
320
321	/* Note: On HECC, BTC can be programmed only in initialization mode, so
322	 * it is expected that the can bittiming parameters are set via ip
323	 * utility before the device is opened
324	 */
325	ti_hecc_set_btc(priv);
326
327	/* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
328	hecc_write(priv, HECC_CANMC, 0);
329
330	/* INFO: CAN net stack handles bus off and hence disabling auto-bus-on
331	 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
332	 */
333
334	/* INFO: It has been observed that at times CCE bit may not be
335	 * set and hw seems to be ok even if this bit is not set so
336	 */
337	cnt = HECC_CCE_WAIT_COUNT;
338	while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
339		--cnt;
340		udelay(10);
341	}
342
343	/* Enable TX and RX I/O Control pins */
344	hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
345	hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
346
347	/* Clear registers for clean operation */
348	hecc_write(priv, HECC_CANTA, HECC_SET_REG);
349	hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
350	hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
351	hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
352	hecc_write(priv, HECC_CANME, 0);
353	hecc_write(priv, HECC_CANMD, 0);
354
355	/* SCC compat mode NOT supported (and not needed too) */
356	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
357}
358
359static void ti_hecc_start(struct net_device *ndev)
360{
361	struct ti_hecc_priv *priv = netdev_priv(ndev);
362	u32 cnt, mbxno, mbx_mask;
363
364	/* put HECC in initialization mode and set btc */
365	ti_hecc_reset(ndev);
366
367	priv->tx_head = HECC_TX_MASK;
368	priv->tx_tail = HECC_TX_MASK;
369
370	/* Enable local and global acceptance mask registers */
371	hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
372
373	/* Prepare configured mailboxes to receive messages */
374	for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
375		mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
376		mbx_mask = BIT(mbxno);
377		hecc_clear_bit(priv, HECC_CANME, mbx_mask);
378		hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
379		hecc_write_lam(priv, mbxno, HECC_SET_REG);
380		hecc_set_bit(priv, HECC_CANMD, mbx_mask);
381		hecc_set_bit(priv, HECC_CANME, mbx_mask);
382		hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
383	}
384
385	/* Prevent message over-write & Enable interrupts */
386	hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
387	if (priv->use_hecc1int) {
388		hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
389		hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
390			HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
391	} else {
392		hecc_write(priv, HECC_CANMIL, 0);
393		hecc_write(priv, HECC_CANGIM,
394			   HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
395	}
396	priv->can.state = CAN_STATE_ERROR_ACTIVE;
397}
398
399static void ti_hecc_stop(struct net_device *ndev)
400{
401	struct ti_hecc_priv *priv = netdev_priv(ndev);
402
403	/* Disable interrupts and disable mailboxes */
404	hecc_write(priv, HECC_CANGIM, 0);
405	hecc_write(priv, HECC_CANMIM, 0);
406	hecc_write(priv, HECC_CANME, 0);
407	priv->can.state = CAN_STATE_STOPPED;
408}
409
410static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
411{
412	int ret = 0;
413
414	switch (mode) {
415	case CAN_MODE_START:
416		ti_hecc_start(ndev);
417		netif_wake_queue(ndev);
418		break;
419	default:
420		ret = -EOPNOTSUPP;
421		break;
422	}
423
424	return ret;
425}
426
427static int ti_hecc_get_berr_counter(const struct net_device *ndev,
428				    struct can_berr_counter *bec)
429{
430	struct ti_hecc_priv *priv = netdev_priv(ndev);
431
432	bec->txerr = hecc_read(priv, HECC_CANTEC);
433	bec->rxerr = hecc_read(priv, HECC_CANREC);
434
435	return 0;
436}
437
438/* ti_hecc_xmit: HECC Transmit
439 *
440 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
441 * priority of the mailbox for tranmission is dependent upon priority setting
442 * field in mailbox registers. The mailbox with highest value in priority field
443 * is transmitted first. Only when two mailboxes have the same value in
444 * priority field the highest numbered mailbox is transmitted first.
445 *
446 * To utilize the HECC priority feature as described above we start with the
447 * highest numbered mailbox with highest priority level and move on to the next
448 * mailbox with the same priority level and so on. Once we loop through all the
449 * transmit mailboxes we choose the next priority level (lower) and so on
450 * until we reach the lowest priority level on the lowest numbered mailbox
451 * when we stop transmission until all mailboxes are transmitted and then
452 * restart at highest numbered mailbox with highest priority.
453 *
454 * Two counters (head and tail) are used to track the next mailbox to transmit
455 * and to track the echo buffer for already transmitted mailbox. The queue
456 * is stopped when all the mailboxes are busy or when there is a priority
457 * value roll-over happens.
458 */
459static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
460{
461	struct ti_hecc_priv *priv = netdev_priv(ndev);
462	struct can_frame *cf = (struct can_frame *)skb->data;
463	u32 mbxno, mbx_mask, data;
464	unsigned long flags;
465
466	if (can_dropped_invalid_skb(ndev, skb))
467		return NETDEV_TX_OK;
468
469	mbxno = get_tx_head_mb(priv);
470	mbx_mask = BIT(mbxno);
471	spin_lock_irqsave(&priv->mbx_lock, flags);
472	if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
473		spin_unlock_irqrestore(&priv->mbx_lock, flags);
474		netif_stop_queue(ndev);
475		netdev_err(priv->ndev,
476			   "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
477			   priv->tx_head, priv->tx_tail);
478		return NETDEV_TX_BUSY;
479	}
480	spin_unlock_irqrestore(&priv->mbx_lock, flags);
481
482	/* Prepare mailbox for transmission */
483	data = cf->can_dlc | (get_tx_head_prio(priv) << 8);
484	if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
485		data |= HECC_CANMCF_RTR;
486	hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
487
488	if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
489		data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
490	else /* Standard frame format */
491		data = (cf->can_id & CAN_SFF_MASK) << 18;
492	hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
493	hecc_write_mbx(priv, mbxno, HECC_CANMDL,
494		       be32_to_cpu(*(__be32 *)(cf->data)));
495	if (cf->can_dlc > 4)
496		hecc_write_mbx(priv, mbxno, HECC_CANMDH,
497			       be32_to_cpu(*(__be32 *)(cf->data + 4)));
498	else
499		*(u32 *)(cf->data + 4) = 0;
500	can_put_echo_skb(skb, ndev, mbxno);
501
502	spin_lock_irqsave(&priv->mbx_lock, flags);
503	--priv->tx_head;
504	if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
505	    (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
506		netif_stop_queue(ndev);
507	}
508	hecc_set_bit(priv, HECC_CANME, mbx_mask);
509	spin_unlock_irqrestore(&priv->mbx_lock, flags);
510
511	hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
512	hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
513	hecc_write(priv, HECC_CANTRS, mbx_mask);
514
515	return NETDEV_TX_OK;
516}
517
518static inline
519struct ti_hecc_priv *rx_offload_to_priv(struct can_rx_offload *offload)
520{
521	return container_of(offload, struct ti_hecc_priv, offload);
522}
523
524static unsigned int ti_hecc_mailbox_read(struct can_rx_offload *offload,
525					 struct can_frame *cf,
526					 u32 *timestamp, unsigned int mbxno)
527{
528	struct ti_hecc_priv *priv = rx_offload_to_priv(offload);
529	u32 data;
530
531	data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
532	if (data & HECC_CANMID_IDE)
533		cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
534	else
535		cf->can_id = (data >> 18) & CAN_SFF_MASK;
536
537	data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
538	if (data & HECC_CANMCF_RTR)
539		cf->can_id |= CAN_RTR_FLAG;
540	cf->can_dlc = get_can_dlc(data & 0xF);
541
542	data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
543	*(__be32 *)(cf->data) = cpu_to_be32(data);
544	if (cf->can_dlc > 4) {
545		data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
546		*(__be32 *)(cf->data + 4) = cpu_to_be32(data);
547	}
548
549	*timestamp = hecc_read_stamp(priv, mbxno);
550
551	return 1;
552}
553
554static int ti_hecc_error(struct net_device *ndev, int int_status,
555			 int err_status)
556{
557	struct ti_hecc_priv *priv = netdev_priv(ndev);
558	struct can_frame *cf;
559	struct sk_buff *skb;
560	u32 timestamp;
561
562	/* propagate the error condition to the can stack */
563	skb = alloc_can_err_skb(ndev, &cf);
564	if (!skb) {
565		if (printk_ratelimit())
566			netdev_err(priv->ndev,
567				   "%s: alloc_can_err_skb() failed\n",
568				   __func__);
569		return -ENOMEM;
570	}
571
572	if (int_status & HECC_CANGIF_WLIF) { /* warning level int */
573		if ((int_status & HECC_CANGIF_BOIF) == 0) {
574			priv->can.state = CAN_STATE_ERROR_WARNING;
575			++priv->can.can_stats.error_warning;
576			cf->can_id |= CAN_ERR_CRTL;
577			if (hecc_read(priv, HECC_CANTEC) > 96)
578				cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
579			if (hecc_read(priv, HECC_CANREC) > 96)
580				cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
581		}
582		hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);
583		netdev_dbg(priv->ndev, "Error Warning interrupt\n");
584		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
585	}
586
587	if (int_status & HECC_CANGIF_EPIF) { /* error passive int */
588		if ((int_status & HECC_CANGIF_BOIF) == 0) {
589			priv->can.state = CAN_STATE_ERROR_PASSIVE;
590			++priv->can.can_stats.error_passive;
591			cf->can_id |= CAN_ERR_CRTL;
592			if (hecc_read(priv, HECC_CANTEC) > 127)
593				cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
594			if (hecc_read(priv, HECC_CANREC) > 127)
595				cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
596		}
597		hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);
598		netdev_dbg(priv->ndev, "Error passive interrupt\n");
599		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
600	}
601
602	/* Need to check busoff condition in error status register too to
603	 * ensure warning interrupts don't hog the system
604	 */
605	if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
606		priv->can.state = CAN_STATE_BUS_OFF;
607		cf->can_id |= CAN_ERR_BUSOFF;
608		hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);
609		hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
610		/* Disable all interrupts in bus-off to avoid int hog */
611		hecc_write(priv, HECC_CANGIM, 0);
612		++priv->can.can_stats.bus_off;
613		can_bus_off(ndev);
614	}
615
616	if (err_status & HECC_BUS_ERROR) {
617		++priv->can.can_stats.bus_error;
618		cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
619		if (err_status & HECC_CANES_FE) {
620			hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);
621			cf->data[2] |= CAN_ERR_PROT_FORM;
622		}
623		if (err_status & HECC_CANES_BE) {
624			hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);
625			cf->data[2] |= CAN_ERR_PROT_BIT;
626		}
627		if (err_status & HECC_CANES_SE) {
628			hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);
629			cf->data[2] |= CAN_ERR_PROT_STUFF;
630		}
631		if (err_status & HECC_CANES_CRCE) {
632			hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);
633			cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
634		}
635		if (err_status & HECC_CANES_ACKE) {
636			hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);
637			cf->data[3] = CAN_ERR_PROT_LOC_ACK;
638		}
639	}
640
641	timestamp = hecc_read(priv, HECC_CANLNT);
642	can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
643
644	return 0;
645}
646
647static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
648{
649	struct net_device *ndev = (struct net_device *)dev_id;
650	struct ti_hecc_priv *priv = netdev_priv(ndev);
651	struct net_device_stats *stats = &ndev->stats;
652	u32 mbxno, mbx_mask, int_status, err_status, stamp;
653	unsigned long flags, rx_pending;
654
655	int_status = hecc_read(priv,
656			       priv->use_hecc1int ?
657			       HECC_CANGIF1 : HECC_CANGIF0);
658
659	if (!int_status)
660		return IRQ_NONE;
661
662	err_status = hecc_read(priv, HECC_CANES);
663	if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
664			  HECC_CANES_EP | HECC_CANES_EW))
665		ti_hecc_error(ndev, int_status, err_status);
666
667	if (int_status & HECC_CANGIF_GMIF) {
668		while (priv->tx_tail - priv->tx_head > 0) {
669			mbxno = get_tx_tail_mb(priv);
670			mbx_mask = BIT(mbxno);
671			if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
672				break;
673			hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
674			hecc_write(priv, HECC_CANTA, mbx_mask);
675			spin_lock_irqsave(&priv->mbx_lock, flags);
676			hecc_clear_bit(priv, HECC_CANME, mbx_mask);
677			spin_unlock_irqrestore(&priv->mbx_lock, flags);
678			stamp = hecc_read_stamp(priv, mbxno);
679			stats->tx_bytes +=
680				can_rx_offload_get_echo_skb(&priv->offload,
681							    mbxno, stamp);
682			stats->tx_packets++;
683			can_led_event(ndev, CAN_LED_EVENT_TX);
684			--priv->tx_tail;
685		}
686
687		/* restart queue if wrap-up or if queue stalled on last pkt */
688		if ((priv->tx_head == priv->tx_tail &&
689		     ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
690		    (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
691		     ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
692			netif_wake_queue(ndev);
693
694		/* offload RX mailboxes and let NAPI deliver them */
695		while ((rx_pending = hecc_read(priv, HECC_CANRMP))) {
696			can_rx_offload_irq_offload_timestamp(&priv->offload,
697							     rx_pending);
698			hecc_write(priv, HECC_CANRMP, rx_pending);
699		}
700	}
701
702	/* clear all interrupt conditions - read back to avoid spurious ints */
703	if (priv->use_hecc1int) {
704		hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
705		int_status = hecc_read(priv, HECC_CANGIF1);
706	} else {
707		hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
708		int_status = hecc_read(priv, HECC_CANGIF0);
709	}
710
711	return IRQ_HANDLED;
712}
713
714static int ti_hecc_open(struct net_device *ndev)
715{
716	struct ti_hecc_priv *priv = netdev_priv(ndev);
717	int err;
718
719	err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
720			  ndev->name, ndev);
721	if (err) {
722		netdev_err(ndev, "error requesting interrupt\n");
723		return err;
724	}
725
726	ti_hecc_transceiver_switch(priv, 1);
727
728	/* Open common can device */
729	err = open_candev(ndev);
730	if (err) {
731		netdev_err(ndev, "open_candev() failed %d\n", err);
732		ti_hecc_transceiver_switch(priv, 0);
733		free_irq(ndev->irq, ndev);
734		return err;
735	}
736
737	can_led_event(ndev, CAN_LED_EVENT_OPEN);
738
739	ti_hecc_start(ndev);
740	can_rx_offload_enable(&priv->offload);
741	netif_start_queue(ndev);
742
743	return 0;
744}
745
746static int ti_hecc_close(struct net_device *ndev)
747{
748	struct ti_hecc_priv *priv = netdev_priv(ndev);
749
750	netif_stop_queue(ndev);
751	can_rx_offload_disable(&priv->offload);
752	ti_hecc_stop(ndev);
753	free_irq(ndev->irq, ndev);
754	close_candev(ndev);
755	ti_hecc_transceiver_switch(priv, 0);
756
757	can_led_event(ndev, CAN_LED_EVENT_STOP);
758
759	return 0;
760}
761
762static const struct net_device_ops ti_hecc_netdev_ops = {
763	.ndo_open		= ti_hecc_open,
764	.ndo_stop		= ti_hecc_close,
765	.ndo_start_xmit		= ti_hecc_xmit,
766	.ndo_change_mtu		= can_change_mtu,
767};
768
769static const struct of_device_id ti_hecc_dt_ids[] = {
770	{
771		.compatible = "ti,am3517-hecc",
772	},
773	{ }
774};
775MODULE_DEVICE_TABLE(of, ti_hecc_dt_ids);
776
777static int ti_hecc_probe(struct platform_device *pdev)
778{
779	struct net_device *ndev = (struct net_device *)0;
780	struct ti_hecc_priv *priv;
781	struct device_node *np = pdev->dev.of_node;
782	struct resource *res, *irq;
783	struct regulator *reg_xceiver;
784	int err = -ENODEV;
785
786	if (!IS_ENABLED(CONFIG_OF) || !np)
787		return -EINVAL;
788
789	reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
790	if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
791		return -EPROBE_DEFER;
792	else if (IS_ERR(reg_xceiver))
793		reg_xceiver = NULL;
794
795	ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
796	if (!ndev) {
797		dev_err(&pdev->dev, "alloc_candev failed\n");
798		return -ENOMEM;
799	}
800	priv = netdev_priv(ndev);
801
802	/* handle hecc memory */
803	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc");
804	if (!res) {
805		dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc\n");
806		return -EINVAL;
807	}
808
809	priv->base = devm_ioremap_resource(&pdev->dev, res);
810	if (IS_ERR(priv->base)) {
811		dev_err(&pdev->dev, "hecc ioremap failed\n");
812		return PTR_ERR(priv->base);
813	}
814
815	/* handle hecc-ram memory */
816	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hecc-ram");
817	if (!res) {
818		dev_err(&pdev->dev, "can't get IORESOURCE_MEM hecc-ram\n");
819		return -EINVAL;
820	}
821
822	priv->hecc_ram = devm_ioremap_resource(&pdev->dev, res);
823	if (IS_ERR(priv->hecc_ram)) {
824		dev_err(&pdev->dev, "hecc-ram ioremap failed\n");
825		return PTR_ERR(priv->hecc_ram);
826	}
827
828	/* handle mbx memory */
829	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbx");
830	if (!res) {
831		dev_err(&pdev->dev, "can't get IORESOURCE_MEM mbx\n");
832		return -EINVAL;
833	}
834
835	priv->mbx = devm_ioremap_resource(&pdev->dev, res);
836	if (IS_ERR(priv->mbx)) {
837		dev_err(&pdev->dev, "mbx ioremap failed\n");
838		return PTR_ERR(priv->mbx);
839	}
840
841	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
842	if (!irq) {
843		dev_err(&pdev->dev, "No irq resource\n");
844		goto probe_exit;
845	}
846
847	priv->ndev = ndev;
848	priv->reg_xceiver = reg_xceiver;
849	priv->use_hecc1int = of_property_read_bool(np, "ti,use-hecc1int");
850
851	priv->can.bittiming_const = &ti_hecc_bittiming_const;
852	priv->can.do_set_mode = ti_hecc_do_set_mode;
853	priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
854	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
855
856	spin_lock_init(&priv->mbx_lock);
857	ndev->irq = irq->start;
858	ndev->flags |= IFF_ECHO;
859	platform_set_drvdata(pdev, ndev);
860	SET_NETDEV_DEV(ndev, &pdev->dev);
861	ndev->netdev_ops = &ti_hecc_netdev_ops;
862
863	priv->clk = clk_get(&pdev->dev, "hecc_ck");
864	if (IS_ERR(priv->clk)) {
865		dev_err(&pdev->dev, "No clock available\n");
866		err = PTR_ERR(priv->clk);
867		priv->clk = NULL;
868		goto probe_exit_candev;
869	}
870	priv->can.clock.freq = clk_get_rate(priv->clk);
871
872	err = clk_prepare_enable(priv->clk);
873	if (err) {
874		dev_err(&pdev->dev, "clk_prepare_enable() failed\n");
875		goto probe_exit_clk;
876	}
877
878	priv->offload.mailbox_read = ti_hecc_mailbox_read;
879	priv->offload.mb_first = HECC_RX_FIRST_MBOX;
880	priv->offload.mb_last = HECC_MAX_TX_MBOX;
881	err = can_rx_offload_add_timestamp(ndev, &priv->offload);
882	if (err) {
883		dev_err(&pdev->dev, "can_rx_offload_add_timestamp() failed\n");
884		goto probe_exit_clk;
885	}
886
887	err = register_candev(ndev);
888	if (err) {
889		dev_err(&pdev->dev, "register_candev() failed\n");
890		goto probe_exit_offload;
891	}
892
893	devm_can_led_init(ndev);
894
895	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
896		 priv->base, (u32)ndev->irq);
897
898	return 0;
899
900probe_exit_offload:
901	can_rx_offload_del(&priv->offload);
902probe_exit_clk:
903	clk_put(priv->clk);
904probe_exit_candev:
905	free_candev(ndev);
906probe_exit:
907	return err;
908}
909
910static int ti_hecc_remove(struct platform_device *pdev)
911{
912	struct net_device *ndev = platform_get_drvdata(pdev);
913	struct ti_hecc_priv *priv = netdev_priv(ndev);
914
915	unregister_candev(ndev);
916	clk_disable_unprepare(priv->clk);
917	clk_put(priv->clk);
918	can_rx_offload_del(&priv->offload);
919	free_candev(ndev);
920
921	return 0;
922}
923
924#ifdef CONFIG_PM
925static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
926{
927	struct net_device *dev = platform_get_drvdata(pdev);
928	struct ti_hecc_priv *priv = netdev_priv(dev);
929
930	if (netif_running(dev)) {
931		netif_stop_queue(dev);
932		netif_device_detach(dev);
933	}
934
935	hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
936	priv->can.state = CAN_STATE_SLEEPING;
937
938	clk_disable_unprepare(priv->clk);
939
940	return 0;
941}
942
943static int ti_hecc_resume(struct platform_device *pdev)
944{
945	struct net_device *dev = platform_get_drvdata(pdev);
946	struct ti_hecc_priv *priv = netdev_priv(dev);
947	int err;
948
949	err = clk_prepare_enable(priv->clk);
950	if (err)
951		return err;
952
953	hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
954	priv->can.state = CAN_STATE_ERROR_ACTIVE;
955
956	if (netif_running(dev)) {
957		netif_device_attach(dev);
958		netif_start_queue(dev);
959	}
960
961	return 0;
962}
963#else
964#define ti_hecc_suspend NULL
965#define ti_hecc_resume NULL
966#endif
967
968/* TI HECC netdevice driver: platform driver structure */
969static struct platform_driver ti_hecc_driver = {
970	.driver = {
971		.name    = DRV_NAME,
972		.of_match_table = ti_hecc_dt_ids,
973	},
974	.probe = ti_hecc_probe,
975	.remove = ti_hecc_remove,
976	.suspend = ti_hecc_suspend,
977	.resume = ti_hecc_resume,
978};
979
980module_platform_driver(ti_hecc_driver);
981
982MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
983MODULE_LICENSE("GPL v2");
984MODULE_DESCRIPTION(DRV_DESC);
985MODULE_ALIAS("platform:" DRV_NAME);