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/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

https://codeberg.org/ddevault/linux
C Header | 1103 lines | 926 code | 149 blank | 28 comment | 0 complexity | 8fbbe5c37425732304846072a96b57cf MD5 | raw file
Possible License(s): GPL-2.0
  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright (c) 2016-2017 Hisilicon Limited.
  3. #ifndef __HCLGE_CMD_H
  4. #define __HCLGE_CMD_H
  5. #include <linux/types.h>
  6. #include <linux/io.h>
  7. #define HCLGE_CMDQ_TX_TIMEOUT 30000
  8. struct hclge_dev;
  9. struct hclge_desc {
  10. __le16 opcode;
  11. #define HCLGE_CMDQ_RX_INVLD_B 0
  12. #define HCLGE_CMDQ_RX_OUTVLD_B 1
  13. __le16 flag;
  14. __le16 retval;
  15. __le16 rsv;
  16. __le32 data[6];
  17. };
  18. struct hclge_cmq_ring {
  19. dma_addr_t desc_dma_addr;
  20. struct hclge_desc *desc;
  21. struct hclge_dev *dev;
  22. u32 head;
  23. u32 tail;
  24. u16 buf_size;
  25. u16 desc_num;
  26. int next_to_use;
  27. int next_to_clean;
  28. u8 ring_type; /* cmq ring type */
  29. spinlock_t lock; /* Command queue lock */
  30. };
  31. enum hclge_cmd_return_status {
  32. HCLGE_CMD_EXEC_SUCCESS = 0,
  33. HCLGE_CMD_NO_AUTH = 1,
  34. HCLGE_CMD_NOT_SUPPORTED = 2,
  35. HCLGE_CMD_QUEUE_FULL = 3,
  36. HCLGE_CMD_NEXT_ERR = 4,
  37. HCLGE_CMD_UNEXE_ERR = 5,
  38. HCLGE_CMD_PARA_ERR = 6,
  39. HCLGE_CMD_RESULT_ERR = 7,
  40. HCLGE_CMD_TIMEOUT = 8,
  41. HCLGE_CMD_HILINK_ERR = 9,
  42. HCLGE_CMD_QUEUE_ILLEGAL = 10,
  43. HCLGE_CMD_INVALID = 11,
  44. };
  45. enum hclge_cmd_status {
  46. HCLGE_STATUS_SUCCESS = 0,
  47. HCLGE_ERR_CSQ_FULL = -1,
  48. HCLGE_ERR_CSQ_TIMEOUT = -2,
  49. HCLGE_ERR_CSQ_ERROR = -3,
  50. };
  51. struct hclge_misc_vector {
  52. u8 __iomem *addr;
  53. int vector_irq;
  54. };
  55. struct hclge_cmq {
  56. struct hclge_cmq_ring csq;
  57. struct hclge_cmq_ring crq;
  58. u16 tx_timeout;
  59. enum hclge_cmd_status last_status;
  60. };
  61. #define HCLGE_CMD_FLAG_IN BIT(0)
  62. #define HCLGE_CMD_FLAG_OUT BIT(1)
  63. #define HCLGE_CMD_FLAG_NEXT BIT(2)
  64. #define HCLGE_CMD_FLAG_WR BIT(3)
  65. #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
  66. #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  67. enum hclge_opcode_type {
  68. /* Generic commands */
  69. HCLGE_OPC_QUERY_FW_VER = 0x0001,
  70. HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
  71. HCLGE_OPC_GBL_RST_STATUS = 0x0021,
  72. HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
  73. HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
  74. HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
  75. HCLGE_OPC_GET_CFG_PARAM = 0x0025,
  76. HCLGE_OPC_PF_RST_DONE = 0x0026,
  77. HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
  78. HCLGE_OPC_STATS_64_BIT = 0x0030,
  79. HCLGE_OPC_STATS_32_BIT = 0x0031,
  80. HCLGE_OPC_STATS_MAC = 0x0032,
  81. HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
  82. HCLGE_OPC_STATS_MAC_ALL = 0x0034,
  83. HCLGE_OPC_QUERY_REG_NUM = 0x0040,
  84. HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
  85. HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
  86. HCLGE_OPC_DFX_BD_NUM = 0x0043,
  87. HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
  88. HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
  89. HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
  90. HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
  91. HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
  92. HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
  93. HCLGE_OPC_DFX_NCSI_REG = 0x004A,
  94. HCLGE_OPC_DFX_RTC_REG = 0x004B,
  95. HCLGE_OPC_DFX_PPP_REG = 0x004C,
  96. HCLGE_OPC_DFX_RCB_REG = 0x004D,
  97. HCLGE_OPC_DFX_TQP_REG = 0x004E,
  98. HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
  99. HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050,
  100. /* MAC command */
  101. HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
  102. HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
  103. HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
  104. HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
  105. HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
  106. HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
  107. HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
  108. HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
  109. HCLGE_OPC_SERDES_LOOPBACK = 0x0315,
  110. HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
  111. /* PFC/Pause commands */
  112. HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
  113. HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
  114. HCLGE_OPC_CFG_MAC_PARA = 0x0703,
  115. HCLGE_OPC_CFG_PFC_PARA = 0x0704,
  116. HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
  117. HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
  118. HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
  119. HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
  120. HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
  121. HCLGE_OPC_QOS_MAP = 0x070A,
  122. /* ETS/scheduler commands */
  123. HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
  124. HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
  125. HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
  126. HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
  127. HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
  128. HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
  129. HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
  130. HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
  131. HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
  132. HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
  133. HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
  134. HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
  135. HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
  136. HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
  137. HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
  138. HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
  139. HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
  140. HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
  141. HCLGE_OPC_QSET_DFX_STS = 0x0844,
  142. HCLGE_OPC_PRI_DFX_STS = 0x0845,
  143. HCLGE_OPC_PG_DFX_STS = 0x0846,
  144. HCLGE_OPC_PORT_DFX_STS = 0x0847,
  145. HCLGE_OPC_SCH_NQ_CNT = 0x0848,
  146. HCLGE_OPC_SCH_RQ_CNT = 0x0849,
  147. HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
  148. HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
  149. HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
  150. /* Packet buffer allocate commands */
  151. HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
  152. HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
  153. HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
  154. HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
  155. HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
  156. HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
  157. /* TQP management command */
  158. HCLGE_OPC_SET_TQP_MAP = 0x0A01,
  159. /* TQP commands */
  160. HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
  161. HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
  162. HCLGE_OPC_QUERY_TX_STATUS = 0x0B03,
  163. HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
  164. HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
  165. HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
  166. HCLGE_OPC_QUERY_RX_STATUS = 0x0B13,
  167. HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
  168. HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
  169. HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
  170. HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
  171. /* PPU commands */
  172. HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
  173. /* TSO command */
  174. HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
  175. HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
  176. /* RSS commands */
  177. HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
  178. HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
  179. HCLGE_OPC_RSS_TC_MODE = 0x0D08,
  180. HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
  181. /* Promisuous mode command */
  182. HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
  183. /* Vlan offload commands */
  184. HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
  185. HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
  186. /* Interrupts commands */
  187. HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
  188. HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
  189. /* MAC commands */
  190. HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
  191. HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
  192. HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
  193. HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
  194. HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
  195. HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
  196. HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
  197. /* MAC VLAN commands */
  198. HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
  199. /* VLAN commands */
  200. HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
  201. HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
  202. HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
  203. /* Flow Director commands */
  204. HCLGE_OPC_FD_MODE_CTRL = 0x1200,
  205. HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
  206. HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
  207. HCLGE_OPC_FD_TCAM_OP = 0x1203,
  208. HCLGE_OPC_FD_AD_OP = 0x1204,
  209. /* MDIO command */
  210. HCLGE_OPC_MDIO_CONFIG = 0x1900,
  211. /* QCN commands */
  212. HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
  213. HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
  214. HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03,
  215. HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
  216. HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
  217. HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
  218. HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
  219. HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
  220. /* Mailbox command */
  221. HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
  222. /* Led command */
  223. HCLGE_OPC_LED_STATUS_CFG = 0xB000,
  224. /* NCL config command */
  225. HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
  226. /* M7 stats command */
  227. HCLGE_OPC_M7_STATS_BD = 0x7012,
  228. HCLGE_OPC_M7_STATS_INFO = 0x7013,
  229. HCLGE_OPC_M7_COMPAT_CFG = 0x701A,
  230. /* SFP command */
  231. HCLGE_OPC_GET_SFP_INFO = 0x7104,
  232. /* Error INT commands */
  233. HCLGE_MAC_COMMON_INT_EN = 0x030E,
  234. HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
  235. HCLGE_SSU_ECC_INT_CMD = 0x0989,
  236. HCLGE_SSU_COMMON_INT_CMD = 0x098C,
  237. HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
  238. HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
  239. HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
  240. HCLGE_COMMON_ECC_INT_CFG = 0x1505,
  241. HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
  242. HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
  243. HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
  244. HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
  245. HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
  246. HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
  247. HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
  248. HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
  249. HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
  250. HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
  251. HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
  252. HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
  253. HCLGE_IGU_COMMON_INT_EN = 0x1806,
  254. HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
  255. HCLGE_PPP_CMD0_INT_CMD = 0x2100,
  256. HCLGE_PPP_CMD1_INT_CMD = 0x2101,
  257. HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
  258. HCLGE_NCSI_INT_EN = 0x2401,
  259. };
  260. #define HCLGE_TQP_REG_OFFSET 0x80000
  261. #define HCLGE_TQP_REG_SIZE 0x200
  262. #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
  263. #define HCLGE_RCB_INIT_FLAG_EN_B 0
  264. #define HCLGE_RCB_INIT_FLAG_FINI_B 8
  265. struct hclge_config_rcb_init_cmd {
  266. __le16 rcb_init_flag;
  267. u8 rsv[22];
  268. };
  269. struct hclge_tqp_map_cmd {
  270. __le16 tqp_id; /* Absolute tqp id for in this pf */
  271. u8 tqp_vf; /* VF id */
  272. #define HCLGE_TQP_MAP_TYPE_PF 0
  273. #define HCLGE_TQP_MAP_TYPE_VF 1
  274. #define HCLGE_TQP_MAP_TYPE_B 0
  275. #define HCLGE_TQP_MAP_EN_B 1
  276. u8 tqp_flag; /* Indicate it's pf or vf tqp */
  277. __le16 tqp_vid; /* Virtual id in this pf/vf */
  278. u8 rsv[18];
  279. };
  280. #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
  281. enum hclge_int_type {
  282. HCLGE_INT_TX,
  283. HCLGE_INT_RX,
  284. HCLGE_INT_EVENT,
  285. };
  286. struct hclge_ctrl_vector_chain_cmd {
  287. u8 int_vector_id;
  288. u8 int_cause_num;
  289. #define HCLGE_INT_TYPE_S 0
  290. #define HCLGE_INT_TYPE_M GENMASK(1, 0)
  291. #define HCLGE_TQP_ID_S 2
  292. #define HCLGE_TQP_ID_M GENMASK(12, 2)
  293. #define HCLGE_INT_GL_IDX_S 13
  294. #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
  295. __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
  296. u8 vfid;
  297. u8 rsv;
  298. };
  299. #define HCLGE_MAX_TC_NUM 8
  300. #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
  301. #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
  302. struct hclge_tx_buff_alloc_cmd {
  303. __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
  304. u8 tx_buff_rsv[8];
  305. };
  306. struct hclge_rx_priv_buff_cmd {
  307. __le16 buf_num[HCLGE_MAX_TC_NUM];
  308. __le16 shared_buf;
  309. u8 rsv[6];
  310. };
  311. struct hclge_query_version_cmd {
  312. __le32 firmware;
  313. __le32 firmware_rsv[5];
  314. };
  315. #define HCLGE_RX_PRIV_EN_B 15
  316. #define HCLGE_TC_NUM_ONE_DESC 4
  317. struct hclge_priv_wl {
  318. __le16 high;
  319. __le16 low;
  320. };
  321. struct hclge_rx_priv_wl_buf {
  322. struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
  323. };
  324. struct hclge_rx_com_thrd {
  325. struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
  326. };
  327. struct hclge_rx_com_wl {
  328. struct hclge_priv_wl com_wl;
  329. };
  330. struct hclge_waterline {
  331. u32 low;
  332. u32 high;
  333. };
  334. struct hclge_tc_thrd {
  335. u32 low;
  336. u32 high;
  337. };
  338. struct hclge_priv_buf {
  339. struct hclge_waterline wl; /* Waterline for low and high*/
  340. u32 buf_size; /* TC private buffer size */
  341. u32 tx_buf_size;
  342. u32 enable; /* Enable TC private buffer or not */
  343. };
  344. struct hclge_shared_buf {
  345. struct hclge_waterline self;
  346. struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
  347. u32 buf_size;
  348. };
  349. struct hclge_pkt_buf_alloc {
  350. struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
  351. struct hclge_shared_buf s_buf;
  352. };
  353. #define HCLGE_RX_COM_WL_EN_B 15
  354. struct hclge_rx_com_wl_buf_cmd {
  355. __le16 high_wl;
  356. __le16 low_wl;
  357. u8 rsv[20];
  358. };
  359. #define HCLGE_RX_PKT_EN_B 15
  360. struct hclge_rx_pkt_buf_cmd {
  361. __le16 high_pkt;
  362. __le16 low_pkt;
  363. u8 rsv[20];
  364. };
  365. #define HCLGE_PF_STATE_DONE_B 0
  366. #define HCLGE_PF_STATE_MAIN_B 1
  367. #define HCLGE_PF_STATE_BOND_B 2
  368. #define HCLGE_PF_STATE_MAC_N_B 6
  369. #define HCLGE_PF_MAC_NUM_MASK 0x3
  370. #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
  371. #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
  372. struct hclge_func_status_cmd {
  373. __le32 vf_rst_state[4];
  374. u8 pf_state;
  375. u8 mac_id;
  376. u8 rsv1;
  377. u8 pf_cnt_in_mac;
  378. u8 pf_num;
  379. u8 vf_num;
  380. u8 rsv[2];
  381. };
  382. struct hclge_pf_res_cmd {
  383. __le16 tqp_num;
  384. __le16 buf_size;
  385. __le16 msixcap_localid_ba_nic;
  386. __le16 msixcap_localid_ba_rocee;
  387. #define HCLGE_MSIX_OFT_ROCEE_S 0
  388. #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
  389. #define HCLGE_PF_VEC_NUM_S 0
  390. #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
  391. __le16 pf_intr_vector_number;
  392. __le16 pf_own_fun_number;
  393. __le16 tx_buf_size;
  394. __le16 dv_buf_size;
  395. __le32 rsv[2];
  396. };
  397. #define HCLGE_CFG_OFFSET_S 0
  398. #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
  399. #define HCLGE_CFG_RD_LEN_S 24
  400. #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
  401. #define HCLGE_CFG_RD_LEN_BYTES 16
  402. #define HCLGE_CFG_RD_LEN_UNIT 4
  403. #define HCLGE_CFG_VMDQ_S 0
  404. #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
  405. #define HCLGE_CFG_TC_NUM_S 8
  406. #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
  407. #define HCLGE_CFG_TQP_DESC_N_S 16
  408. #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
  409. #define HCLGE_CFG_PHY_ADDR_S 0
  410. #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
  411. #define HCLGE_CFG_MEDIA_TP_S 8
  412. #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
  413. #define HCLGE_CFG_RX_BUF_LEN_S 16
  414. #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
  415. #define HCLGE_CFG_MAC_ADDR_H_S 0
  416. #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
  417. #define HCLGE_CFG_DEFAULT_SPEED_S 16
  418. #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
  419. #define HCLGE_CFG_RSS_SIZE_S 24
  420. #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
  421. #define HCLGE_CFG_SPEED_ABILITY_S 0
  422. #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
  423. #define HCLGE_CFG_UMV_TBL_SPACE_S 16
  424. #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
  425. struct hclge_cfg_param_cmd {
  426. __le32 offset;
  427. __le32 rsv;
  428. __le32 param[4];
  429. };
  430. #define HCLGE_MAC_MODE 0x0
  431. #define HCLGE_DESC_NUM 0x40
  432. #define HCLGE_ALLOC_VALID_B 0
  433. struct hclge_vf_num_cmd {
  434. u8 alloc_valid;
  435. u8 rsv[23];
  436. };
  437. #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
  438. #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
  439. #define HCLGE_RSS_HASH_KEY_NUM 16
  440. struct hclge_rss_config_cmd {
  441. u8 hash_config;
  442. u8 rsv[7];
  443. u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
  444. };
  445. struct hclge_rss_input_tuple_cmd {
  446. u8 ipv4_tcp_en;
  447. u8 ipv4_udp_en;
  448. u8 ipv4_sctp_en;
  449. u8 ipv4_fragment_en;
  450. u8 ipv6_tcp_en;
  451. u8 ipv6_udp_en;
  452. u8 ipv6_sctp_en;
  453. u8 ipv6_fragment_en;
  454. u8 rsv[16];
  455. };
  456. #define HCLGE_RSS_CFG_TBL_SIZE 16
  457. struct hclge_rss_indirection_table_cmd {
  458. __le16 start_table_index;
  459. __le16 rss_set_bitmap;
  460. u8 rsv[4];
  461. u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
  462. };
  463. #define HCLGE_RSS_TC_OFFSET_S 0
  464. #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
  465. #define HCLGE_RSS_TC_SIZE_S 12
  466. #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
  467. #define HCLGE_RSS_TC_VALID_B 15
  468. struct hclge_rss_tc_mode_cmd {
  469. __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
  470. u8 rsv[8];
  471. };
  472. #define HCLGE_LINK_STATUS_UP_B 0
  473. #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
  474. struct hclge_link_status_cmd {
  475. u8 status;
  476. u8 rsv[23];
  477. };
  478. struct hclge_promisc_param {
  479. u8 vf_id;
  480. u8 enable;
  481. };
  482. #define HCLGE_PROMISC_TX_EN_B BIT(4)
  483. #define HCLGE_PROMISC_RX_EN_B BIT(5)
  484. #define HCLGE_PROMISC_EN_B 1
  485. #define HCLGE_PROMISC_EN_ALL 0x7
  486. #define HCLGE_PROMISC_EN_UC 0x1
  487. #define HCLGE_PROMISC_EN_MC 0x2
  488. #define HCLGE_PROMISC_EN_BC 0x4
  489. struct hclge_promisc_cfg_cmd {
  490. u8 flag;
  491. u8 vf_id;
  492. __le16 rsv0;
  493. u8 rsv1[20];
  494. };
  495. enum hclge_promisc_type {
  496. HCLGE_UNICAST = 1,
  497. HCLGE_MULTICAST = 2,
  498. HCLGE_BROADCAST = 3,
  499. };
  500. #define HCLGE_MAC_TX_EN_B 6
  501. #define HCLGE_MAC_RX_EN_B 7
  502. #define HCLGE_MAC_PAD_TX_B 11
  503. #define HCLGE_MAC_PAD_RX_B 12
  504. #define HCLGE_MAC_1588_TX_B 13
  505. #define HCLGE_MAC_1588_RX_B 14
  506. #define HCLGE_MAC_APP_LP_B 15
  507. #define HCLGE_MAC_LINE_LP_B 16
  508. #define HCLGE_MAC_FCS_TX_B 17
  509. #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
  510. #define HCLGE_MAC_RX_FCS_STRIP_B 19
  511. #define HCLGE_MAC_RX_FCS_B 20
  512. #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
  513. #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
  514. struct hclge_config_mac_mode_cmd {
  515. __le32 txrx_pad_fcs_loop_en;
  516. u8 rsv[20];
  517. };
  518. struct hclge_pf_rst_sync_cmd {
  519. #define HCLGE_PF_RST_ALL_VF_RDY_B 0
  520. u8 all_vf_ready;
  521. u8 rsv[23];
  522. };
  523. #define HCLGE_CFG_SPEED_S 0
  524. #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
  525. #define HCLGE_CFG_DUPLEX_B 7
  526. #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
  527. struct hclge_config_mac_speed_dup_cmd {
  528. u8 speed_dup;
  529. #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
  530. u8 mac_change_fec_en;
  531. u8 rsv[22];
  532. };
  533. #define HCLGE_RING_ID_MASK GENMASK(9, 0)
  534. #define HCLGE_TQP_ENABLE_B 0
  535. #define HCLGE_MAC_CFG_AN_EN_B 0
  536. #define HCLGE_MAC_CFG_AN_INT_EN_B 1
  537. #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
  538. #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
  539. #define HCLGE_MAC_CFG_AN_RST_B 4
  540. #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
  541. struct hclge_config_auto_neg_cmd {
  542. __le32 cfg_an_cmd_flag;
  543. u8 rsv[20];
  544. };
  545. struct hclge_sfp_info_cmd {
  546. __le32 speed;
  547. u8 query_type; /* 0: sfp speed, 1: active speed */
  548. u8 active_fec;
  549. u8 autoneg; /* autoneg state */
  550. u8 autoneg_ability; /* whether support autoneg */
  551. __le32 speed_ability; /* speed ability for current media */
  552. __le32 module_type;
  553. u8 rsv[8];
  554. };
  555. #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
  556. #define HCLGE_MAC_CFG_FEC_MODE_S 1
  557. #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
  558. #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
  559. #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
  560. #define HCLGE_MAC_FEC_OFF 0
  561. #define HCLGE_MAC_FEC_BASER 1
  562. #define HCLGE_MAC_FEC_RS 2
  563. struct hclge_config_fec_cmd {
  564. u8 fec_mode;
  565. u8 default_config;
  566. u8 rsv[22];
  567. };
  568. #define HCLGE_MAC_UPLINK_PORT 0x100
  569. struct hclge_config_max_frm_size_cmd {
  570. __le16 max_frm_size;
  571. u8 min_frm_size;
  572. u8 rsv[21];
  573. };
  574. enum hclge_mac_vlan_tbl_opcode {
  575. HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
  576. HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
  577. HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
  578. HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
  579. };
  580. enum hclge_mac_vlan_add_resp_code {
  581. HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
  582. HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
  583. };
  584. #define HCLGE_MAC_VLAN_BIT0_EN_B 0
  585. #define HCLGE_MAC_VLAN_BIT1_EN_B 1
  586. #define HCLGE_MAC_EPORT_SW_EN_B 12
  587. #define HCLGE_MAC_EPORT_TYPE_B 11
  588. #define HCLGE_MAC_EPORT_VFID_S 3
  589. #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
  590. #define HCLGE_MAC_EPORT_PFID_S 0
  591. #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
  592. struct hclge_mac_vlan_tbl_entry_cmd {
  593. u8 flags;
  594. u8 resp_code;
  595. __le16 vlan_tag;
  596. __le32 mac_addr_hi32;
  597. __le16 mac_addr_lo16;
  598. __le16 rsv1;
  599. u8 entry_type;
  600. u8 mc_mac_en;
  601. __le16 egress_port;
  602. __le16 egress_queue;
  603. u8 rsv2[6];
  604. };
  605. #define HCLGE_UMV_SPC_ALC_B 0
  606. struct hclge_umv_spc_alc_cmd {
  607. u8 allocate;
  608. u8 rsv1[3];
  609. __le32 space_size;
  610. u8 rsv2[16];
  611. };
  612. #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
  613. #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
  614. #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
  615. struct hclge_mac_mgr_tbl_entry_cmd {
  616. u8 flags;
  617. u8 resp_code;
  618. __le16 vlan_tag;
  619. __le32 mac_addr_hi32;
  620. __le16 mac_addr_lo16;
  621. __le16 rsv1;
  622. __le16 ethter_type;
  623. __le16 egress_port;
  624. __le16 egress_queue;
  625. u8 sw_port_id_aware;
  626. u8 rsv2;
  627. u8 i_port_bitmap;
  628. u8 i_port_direction;
  629. u8 rsv3[2];
  630. };
  631. struct hclge_mac_vlan_add_cmd {
  632. __le16 flags;
  633. __le16 mac_addr_hi16;
  634. __le32 mac_addr_lo32;
  635. __le32 mac_addr_msk_hi32;
  636. __le16 mac_addr_msk_lo16;
  637. __le16 vlan_tag;
  638. __le16 ingress_port;
  639. __le16 egress_port;
  640. u8 rsv[4];
  641. };
  642. #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
  643. struct hclge_mac_vlan_remove_cmd {
  644. __le16 flags;
  645. __le16 mac_addr_hi16;
  646. __le32 mac_addr_lo32;
  647. __le32 mac_addr_msk_hi32;
  648. __le16 mac_addr_msk_lo16;
  649. __le16 vlan_tag;
  650. __le16 ingress_port;
  651. __le16 egress_port;
  652. u8 rsv[4];
  653. };
  654. struct hclge_vlan_filter_ctrl_cmd {
  655. u8 vlan_type;
  656. u8 vlan_fe;
  657. u8 rsv1[2];
  658. u8 vf_id;
  659. u8 rsv2[19];
  660. };
  661. struct hclge_vlan_filter_pf_cfg_cmd {
  662. u8 vlan_offset;
  663. u8 vlan_cfg;
  664. u8 rsv[2];
  665. u8 vlan_offset_bitmap[20];
  666. };
  667. struct hclge_vlan_filter_vf_cfg_cmd {
  668. __le16 vlan_id;
  669. u8 resp_code;
  670. u8 rsv;
  671. u8 vlan_cfg;
  672. u8 rsv1[3];
  673. u8 vf_bitmap[16];
  674. };
  675. #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
  676. #define HCLGE_SWITCH_ALW_LPBK_B 1U
  677. #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
  678. #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
  679. #define HCLGE_SWITCH_NO_MASK 0x0
  680. #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
  681. #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
  682. #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
  683. #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
  684. struct hclge_mac_vlan_switch_cmd {
  685. u8 roce_sel;
  686. u8 rsv1[3];
  687. __le32 func_id;
  688. u8 switch_param;
  689. u8 rsv2[3];
  690. u8 param_mask;
  691. u8 rsv3[11];
  692. };
  693. enum hclge_mac_vlan_cfg_sel {
  694. HCLGE_MAC_VLAN_NIC_SEL = 0,
  695. HCLGE_MAC_VLAN_ROCE_SEL,
  696. };
  697. #define HCLGE_ACCEPT_TAG1_B 0
  698. #define HCLGE_ACCEPT_UNTAG1_B 1
  699. #define HCLGE_PORT_INS_TAG1_EN_B 2
  700. #define HCLGE_PORT_INS_TAG2_EN_B 3
  701. #define HCLGE_CFG_NIC_ROCE_SEL_B 4
  702. #define HCLGE_ACCEPT_TAG2_B 5
  703. #define HCLGE_ACCEPT_UNTAG2_B 6
  704. struct hclge_vport_vtag_tx_cfg_cmd {
  705. u8 vport_vlan_cfg;
  706. u8 vf_offset;
  707. u8 rsv1[2];
  708. __le16 def_vlan_tag1;
  709. __le16 def_vlan_tag2;
  710. u8 vf_bitmap[8];
  711. u8 rsv2[8];
  712. };
  713. #define HCLGE_REM_TAG1_EN_B 0
  714. #define HCLGE_REM_TAG2_EN_B 1
  715. #define HCLGE_SHOW_TAG1_EN_B 2
  716. #define HCLGE_SHOW_TAG2_EN_B 3
  717. struct hclge_vport_vtag_rx_cfg_cmd {
  718. u8 vport_vlan_cfg;
  719. u8 vf_offset;
  720. u8 rsv1[6];
  721. u8 vf_bitmap[8];
  722. u8 rsv2[8];
  723. };
  724. struct hclge_tx_vlan_type_cfg_cmd {
  725. __le16 ot_vlan_type;
  726. __le16 in_vlan_type;
  727. u8 rsv[20];
  728. };
  729. struct hclge_rx_vlan_type_cfg_cmd {
  730. __le16 ot_fst_vlan_type;
  731. __le16 ot_sec_vlan_type;
  732. __le16 in_fst_vlan_type;
  733. __le16 in_sec_vlan_type;
  734. u8 rsv[16];
  735. };
  736. struct hclge_cfg_com_tqp_queue_cmd {
  737. __le16 tqp_id;
  738. __le16 stream_id;
  739. u8 enable;
  740. u8 rsv[19];
  741. };
  742. struct hclge_cfg_tx_queue_pointer_cmd {
  743. __le16 tqp_id;
  744. __le16 tx_tail;
  745. __le16 tx_head;
  746. __le16 fbd_num;
  747. __le16 ring_offset;
  748. u8 rsv[14];
  749. };
  750. #pragma pack(1)
  751. struct hclge_mac_ethertype_idx_rd_cmd {
  752. u8 flags;
  753. u8 resp_code;
  754. __le16 vlan_tag;
  755. u8 mac_addr[6];
  756. __le16 index;
  757. __le16 ethter_type;
  758. __le16 egress_port;
  759. __le16 egress_queue;
  760. __le16 rev0;
  761. u8 i_port_bitmap;
  762. u8 i_port_direction;
  763. u8 rev1[2];
  764. };
  765. #pragma pack()
  766. #define HCLGE_TSO_MSS_MIN_S 0
  767. #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
  768. #define HCLGE_TSO_MSS_MAX_S 16
  769. #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
  770. struct hclge_cfg_tso_status_cmd {
  771. __le16 tso_mss_min;
  772. __le16 tso_mss_max;
  773. u8 rsv[20];
  774. };
  775. #define HCLGE_GRO_EN_B 0
  776. struct hclge_cfg_gro_status_cmd {
  777. __le16 gro_en;
  778. u8 rsv[22];
  779. };
  780. #define HCLGE_TSO_MSS_MIN 256
  781. #define HCLGE_TSO_MSS_MAX 9668
  782. #define HCLGE_TQP_RESET_B 0
  783. struct hclge_reset_tqp_queue_cmd {
  784. __le16 tqp_id;
  785. u8 reset_req;
  786. u8 ready_to_reset;
  787. u8 rsv[20];
  788. };
  789. #define HCLGE_CFG_RESET_MAC_B 3
  790. #define HCLGE_CFG_RESET_FUNC_B 7
  791. struct hclge_reset_cmd {
  792. u8 mac_func_reset;
  793. u8 fun_reset_vfid;
  794. u8 rsv[22];
  795. };
  796. #define HCLGE_PF_RESET_DONE_BIT BIT(0)
  797. struct hclge_pf_rst_done_cmd {
  798. u8 pf_rst_done;
  799. u8 rsv[23];
  800. };
  801. #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
  802. #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
  803. #define HCLGE_CMD_SERDES_DONE_B BIT(0)
  804. #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
  805. struct hclge_serdes_lb_cmd {
  806. u8 mask;
  807. u8 enable;
  808. u8 result;
  809. u8 rsv[21];
  810. };
  811. #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
  812. #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
  813. #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
  814. #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
  815. #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
  816. #define HCLGE_TYPE_CRQ 0
  817. #define HCLGE_TYPE_CSQ 1
  818. #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
  819. #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
  820. #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
  821. #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
  822. #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
  823. #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
  824. #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
  825. #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
  826. #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
  827. #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
  828. /* this bit indicates that the driver is ready for hardware reset */
  829. #define HCLGE_NIC_SW_RST_RDY_B 16
  830. #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
  831. #define HCLGE_NIC_CMQ_DESC_NUM 1024
  832. #define HCLGE_NIC_CMQ_DESC_NUM_S 3
  833. #define HCLGE_LED_LOCATE_STATE_S 0
  834. #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
  835. struct hclge_set_led_state_cmd {
  836. u8 rsv1[3];
  837. u8 locate_led_config;
  838. u8 rsv2[20];
  839. };
  840. struct hclge_get_fd_mode_cmd {
  841. u8 mode;
  842. u8 enable;
  843. u8 rsv[22];
  844. };
  845. struct hclge_get_fd_allocation_cmd {
  846. __le32 stage1_entry_num;
  847. __le32 stage2_entry_num;
  848. __le16 stage1_counter_num;
  849. __le16 stage2_counter_num;
  850. u8 rsv[12];
  851. };
  852. struct hclge_set_fd_key_config_cmd {
  853. u8 stage;
  854. u8 key_select;
  855. u8 inner_sipv6_word_en;
  856. u8 inner_dipv6_word_en;
  857. u8 outer_sipv6_word_en;
  858. u8 outer_dipv6_word_en;
  859. u8 rsv1[2];
  860. __le32 tuple_mask;
  861. __le32 meta_data_mask;
  862. u8 rsv2[8];
  863. };
  864. #define HCLGE_FD_EPORT_SW_EN_B 0
  865. struct hclge_fd_tcam_config_1_cmd {
  866. u8 stage;
  867. u8 xy_sel;
  868. u8 port_info;
  869. u8 rsv1[1];
  870. __le32 index;
  871. u8 entry_vld;
  872. u8 rsv2[7];
  873. u8 tcam_data[8];
  874. };
  875. struct hclge_fd_tcam_config_2_cmd {
  876. u8 tcam_data[24];
  877. };
  878. struct hclge_fd_tcam_config_3_cmd {
  879. u8 tcam_data[20];
  880. u8 rsv[4];
  881. };
  882. #define HCLGE_FD_AD_DROP_B 0
  883. #define HCLGE_FD_AD_DIRECT_QID_B 1
  884. #define HCLGE_FD_AD_QID_S 2
  885. #define HCLGE_FD_AD_QID_M GENMASK(12, 2)
  886. #define HCLGE_FD_AD_USE_COUNTER_B 12
  887. #define HCLGE_FD_AD_COUNTER_NUM_S 13
  888. #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
  889. #define HCLGE_FD_AD_NXT_STEP_B 20
  890. #define HCLGE_FD_AD_NXT_KEY_S 21
  891. #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21)
  892. #define HCLGE_FD_AD_WR_RULE_ID_B 0
  893. #define HCLGE_FD_AD_RULE_ID_S 1
  894. #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1)
  895. struct hclge_fd_ad_config_cmd {
  896. u8 stage;
  897. u8 rsv1[3];
  898. __le32 index;
  899. __le64 ad_data;
  900. u8 rsv2[8];
  901. };
  902. struct hclge_get_m7_bd_cmd {
  903. __le32 bd_num;
  904. u8 rsv[20];
  905. };
  906. struct hclge_query_ppu_pf_other_int_dfx_cmd {
  907. __le16 over_8bd_no_fe_qid;
  908. __le16 over_8bd_no_fe_vf_id;
  909. __le16 tso_mss_cmp_min_err_qid;
  910. __le16 tso_mss_cmp_min_err_vf_id;
  911. __le16 tso_mss_cmp_max_err_qid;
  912. __le16 tso_mss_cmp_max_err_vf_id;
  913. __le16 tx_rd_fbd_poison_qid;
  914. __le16 tx_rd_fbd_poison_vf_id;
  915. __le16 rx_rd_fbd_poison_qid;
  916. __le16 rx_rd_fbd_poison_vf_id;
  917. u8 rsv[4];
  918. };
  919. #define HCLGE_LINK_EVENT_REPORT_EN_B 0
  920. #define HCLGE_NCSI_ERROR_REPORT_EN_B 1
  921. struct hclge_firmware_compat_cmd {
  922. __le32 compat;
  923. u8 rsv[20];
  924. };
  925. int hclge_cmd_init(struct hclge_dev *hdev);
  926. static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
  927. {
  928. writel(value, base + reg);
  929. }
  930. #define hclge_write_dev(a, reg, value) \
  931. hclge_write_reg((a)->io_base, (reg), (value))
  932. #define hclge_read_dev(a, reg) \
  933. hclge_read_reg((a)->io_base, (reg))
  934. static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
  935. {
  936. u8 __iomem *reg_addr = READ_ONCE(base);
  937. return readl(reg_addr + reg);
  938. }
  939. #define HCLGE_SEND_SYNC(flag) \
  940. ((flag) & HCLGE_CMD_FLAG_NO_INTR)
  941. struct hclge_hw;
  942. int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
  943. void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
  944. enum hclge_opcode_type opcode, bool is_read);
  945. void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
  946. int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
  947. struct hclge_promisc_param *param);
  948. enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
  949. struct hclge_desc *desc);
  950. enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
  951. struct hclge_desc *desc);
  952. void hclge_cmd_uninit(struct hclge_dev *hdev);
  953. int hclge_cmd_queue_init(struct hclge_dev *hdev);
  954. #endif