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/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

https://codeberg.org/ddevault/linux
C Header | 997 lines | 810 code | 130 blank | 57 comment | 1 complexity | 6bba5de85da86072ccc47e35a60f8ade MD5 | raw file
Possible License(s): GPL-2.0
  1// SPDX-License-Identifier: GPL-2.0+
  2// Copyright (c) 2016-2017 Hisilicon Limited.
  3
  4#ifndef __HCLGE_MAIN_H
  5#define __HCLGE_MAIN_H
  6#include <linux/fs.h>
  7#include <linux/types.h>
  8#include <linux/phy.h>
  9#include <linux/if_vlan.h>
 10#include <linux/kfifo.h>
 11
 12#include "hclge_cmd.h"
 13#include "hnae3.h"
 14
 15#define HCLGE_MOD_VERSION "1.0"
 16#define HCLGE_DRIVER_NAME "hclge"
 17
 18#define HCLGE_MAX_PF_NUM		8
 19
 20#define HCLGE_RD_FIRST_STATS_NUM        2
 21#define HCLGE_RD_OTHER_STATS_NUM        4
 22
 23#define HCLGE_INVALID_VPORT 0xffff
 24
 25#define HCLGE_PF_CFG_BLOCK_SIZE		32
 26#define HCLGE_PF_CFG_DESC_NUM \
 27	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
 28
 29#define HCLGE_VECTOR_REG_BASE		0x20000
 30#define HCLGE_MISC_VECTOR_REG_BASE	0x20400
 31
 32#define HCLGE_VECTOR_REG_OFFSET		0x4
 33#define HCLGE_VECTOR_VF_OFFSET		0x100000
 34
 35#define HCLGE_CMDQ_TX_ADDR_L_REG	0x27000
 36#define HCLGE_CMDQ_TX_ADDR_H_REG	0x27004
 37#define HCLGE_CMDQ_TX_DEPTH_REG		0x27008
 38#define HCLGE_CMDQ_TX_TAIL_REG		0x27010
 39#define HCLGE_CMDQ_TX_HEAD_REG		0x27014
 40#define HCLGE_CMDQ_RX_ADDR_L_REG	0x27018
 41#define HCLGE_CMDQ_RX_ADDR_H_REG	0x2701C
 42#define HCLGE_CMDQ_RX_DEPTH_REG		0x27020
 43#define HCLGE_CMDQ_RX_TAIL_REG		0x27024
 44#define HCLGE_CMDQ_RX_HEAD_REG		0x27028
 45#define HCLGE_CMDQ_INTR_SRC_REG		0x27100
 46#define HCLGE_CMDQ_INTR_STS_REG		0x27104
 47#define HCLGE_CMDQ_INTR_EN_REG		0x27108
 48#define HCLGE_CMDQ_INTR_GEN_REG		0x2710C
 49
 50/* bar registers for common func */
 51#define HCLGE_VECTOR0_OTER_EN_REG	0x20600
 52#define HCLGE_RAS_OTHER_STS_REG		0x20B00
 53#define HCLGE_FUNC_RESET_STS_REG	0x20C00
 54#define HCLGE_GRO_EN_REG		0x28000
 55
 56/* bar registers for rcb */
 57#define HCLGE_RING_RX_ADDR_L_REG	0x80000
 58#define HCLGE_RING_RX_ADDR_H_REG	0x80004
 59#define HCLGE_RING_RX_BD_NUM_REG	0x80008
 60#define HCLGE_RING_RX_BD_LENGTH_REG	0x8000C
 61#define HCLGE_RING_RX_MERGE_EN_REG	0x80014
 62#define HCLGE_RING_RX_TAIL_REG		0x80018
 63#define HCLGE_RING_RX_HEAD_REG		0x8001C
 64#define HCLGE_RING_RX_FBD_NUM_REG	0x80020
 65#define HCLGE_RING_RX_OFFSET_REG	0x80024
 66#define HCLGE_RING_RX_FBD_OFFSET_REG	0x80028
 67#define HCLGE_RING_RX_STASH_REG		0x80030
 68#define HCLGE_RING_RX_BD_ERR_REG	0x80034
 69#define HCLGE_RING_TX_ADDR_L_REG	0x80040
 70#define HCLGE_RING_TX_ADDR_H_REG	0x80044
 71#define HCLGE_RING_TX_BD_NUM_REG	0x80048
 72#define HCLGE_RING_TX_PRIORITY_REG	0x8004C
 73#define HCLGE_RING_TX_TC_REG		0x80050
 74#define HCLGE_RING_TX_MERGE_EN_REG	0x80054
 75#define HCLGE_RING_TX_TAIL_REG		0x80058
 76#define HCLGE_RING_TX_HEAD_REG		0x8005C
 77#define HCLGE_RING_TX_FBD_NUM_REG	0x80060
 78#define HCLGE_RING_TX_OFFSET_REG	0x80064
 79#define HCLGE_RING_TX_EBD_NUM_REG	0x80068
 80#define HCLGE_RING_TX_EBD_OFFSET_REG	0x80070
 81#define HCLGE_RING_TX_BD_ERR_REG	0x80074
 82#define HCLGE_RING_EN_REG		0x80090
 83
 84/* bar registers for tqp interrupt */
 85#define HCLGE_TQP_INTR_CTRL_REG		0x20000
 86#define HCLGE_TQP_INTR_GL0_REG		0x20100
 87#define HCLGE_TQP_INTR_GL1_REG		0x20200
 88#define HCLGE_TQP_INTR_GL2_REG		0x20300
 89#define HCLGE_TQP_INTR_RL_REG		0x20900
 90
 91#define HCLGE_RSS_IND_TBL_SIZE		512
 92#define HCLGE_RSS_SET_BITMAP_MSK	GENMASK(15, 0)
 93#define HCLGE_RSS_KEY_SIZE		40
 94#define HCLGE_RSS_HASH_ALGO_TOEPLITZ	0
 95#define HCLGE_RSS_HASH_ALGO_SIMPLE	1
 96#define HCLGE_RSS_HASH_ALGO_SYMMETRIC	2
 97#define HCLGE_RSS_HASH_ALGO_MASK	GENMASK(3, 0)
 98#define HCLGE_RSS_CFG_TBL_NUM \
 99	(HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
100
101#define HCLGE_RSS_INPUT_TUPLE_OTHER	GENMASK(3, 0)
102#define HCLGE_RSS_INPUT_TUPLE_SCTP	GENMASK(4, 0)
103#define HCLGE_D_PORT_BIT		BIT(0)
104#define HCLGE_S_PORT_BIT		BIT(1)
105#define HCLGE_D_IP_BIT			BIT(2)
106#define HCLGE_S_IP_BIT			BIT(3)
107#define HCLGE_V_TAG_BIT			BIT(4)
108
109#define HCLGE_RSS_TC_SIZE_0		1
110#define HCLGE_RSS_TC_SIZE_1		2
111#define HCLGE_RSS_TC_SIZE_2		4
112#define HCLGE_RSS_TC_SIZE_3		8
113#define HCLGE_RSS_TC_SIZE_4		16
114#define HCLGE_RSS_TC_SIZE_5		32
115#define HCLGE_RSS_TC_SIZE_6		64
116#define HCLGE_RSS_TC_SIZE_7		128
117
118#define HCLGE_UMV_TBL_SIZE		3072
119#define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
120	(HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
121
122#define HCLGE_TQP_RESET_TRY_TIMES	200
123
124#define HCLGE_PHY_PAGE_MDIX		0
125#define HCLGE_PHY_PAGE_COPPER		0
126
127/* Page Selection Reg. */
128#define HCLGE_PHY_PAGE_REG		22
129
130/* Copper Specific Control Register */
131#define HCLGE_PHY_CSC_REG		16
132
133/* Copper Specific Status Register */
134#define HCLGE_PHY_CSS_REG		17
135
136#define HCLGE_PHY_MDIX_CTRL_S		5
137#define HCLGE_PHY_MDIX_CTRL_M		GENMASK(6, 5)
138
139#define HCLGE_PHY_MDIX_STATUS_B		6
140#define HCLGE_PHY_SPEED_DUP_RESOLVE_B	11
141
142/* Factor used to calculate offset and bitmap of VF num */
143#define HCLGE_VF_NUM_PER_CMD           64
144#define HCLGE_VF_NUM_PER_BYTE          8
145
146enum HLCGE_PORT_TYPE {
147	HOST_PORT,
148	NETWORK_PORT
149};
150
151#define PF_VPORT_ID			0
152
153#define HCLGE_PF_ID_S			0
154#define HCLGE_PF_ID_M			GENMASK(2, 0)
155#define HCLGE_VF_ID_S			3
156#define HCLGE_VF_ID_M			GENMASK(10, 3)
157#define HCLGE_PORT_TYPE_B		11
158#define HCLGE_NETWORK_PORT_ID_S		0
159#define HCLGE_NETWORK_PORT_ID_M		GENMASK(3, 0)
160
161/* Reset related Registers */
162#define HCLGE_PF_OTHER_INT_REG		0x20600
163#define HCLGE_MISC_RESET_STS_REG	0x20700
164#define HCLGE_MISC_VECTOR_INT_STS	0x20800
165#define HCLGE_GLOBAL_RESET_REG		0x20A00
166#define HCLGE_GLOBAL_RESET_BIT		0
167#define HCLGE_CORE_RESET_BIT		1
168#define HCLGE_IMP_RESET_BIT		2
169#define HCLGE_RESET_INT_M		GENMASK(2, 0)
170#define HCLGE_FUN_RST_ING		0x20C00
171#define HCLGE_FUN_RST_ING_B		0
172
173/* Vector0 register bits define */
174#define HCLGE_VECTOR0_GLOBALRESET_INT_B	5
175#define HCLGE_VECTOR0_CORERESET_INT_B	6
176#define HCLGE_VECTOR0_IMPRESET_INT_B	7
177
178/* Vector0 interrupt CMDQ event source register(RW) */
179#define HCLGE_VECTOR0_CMDQ_SRC_REG	0x27100
180/* CMDQ register bits for RX event(=MBX event) */
181#define HCLGE_VECTOR0_RX_CMDQ_INT_B	1
182
183#define HCLGE_VECTOR0_IMP_RESET_INT_B	1
184#define HCLGE_VECTOR0_IMP_CMDQ_ERR_B	4U
185#define HCLGE_VECTOR0_IMP_RD_POISON_B	5U
186
187#define HCLGE_MAC_DEFAULT_FRAME \
188	(ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
189#define HCLGE_MAC_MIN_FRAME		64
190#define HCLGE_MAC_MAX_FRAME		9728
191
192#define HCLGE_SUPPORT_1G_BIT		BIT(0)
193#define HCLGE_SUPPORT_10G_BIT		BIT(1)
194#define HCLGE_SUPPORT_25G_BIT		BIT(2)
195#define HCLGE_SUPPORT_50G_BIT		BIT(3)
196#define HCLGE_SUPPORT_100G_BIT		BIT(4)
197/* to be compatible with exsit board */
198#define HCLGE_SUPPORT_40G_BIT		BIT(5)
199#define HCLGE_SUPPORT_100M_BIT		BIT(6)
200#define HCLGE_SUPPORT_10M_BIT		BIT(7)
201#define HCLGE_SUPPORT_GE \
202	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
203
204enum HCLGE_DEV_STATE {
205	HCLGE_STATE_REINITING,
206	HCLGE_STATE_DOWN,
207	HCLGE_STATE_DISABLED,
208	HCLGE_STATE_REMOVING,
209	HCLGE_STATE_NIC_REGISTERED,
210	HCLGE_STATE_ROCE_REGISTERED,
211	HCLGE_STATE_SERVICE_INITED,
212	HCLGE_STATE_SERVICE_SCHED,
213	HCLGE_STATE_RST_SERVICE_SCHED,
214	HCLGE_STATE_RST_HANDLING,
215	HCLGE_STATE_MBX_SERVICE_SCHED,
216	HCLGE_STATE_MBX_HANDLING,
217	HCLGE_STATE_STATISTICS_UPDATING,
218	HCLGE_STATE_CMD_DISABLE,
219	HCLGE_STATE_MAX
220};
221
222enum hclge_evt_cause {
223	HCLGE_VECTOR0_EVENT_RST,
224	HCLGE_VECTOR0_EVENT_MBX,
225	HCLGE_VECTOR0_EVENT_ERR,
226	HCLGE_VECTOR0_EVENT_OTHER,
227};
228
229#define HCLGE_MPF_ENBALE 1
230
231enum HCLGE_MAC_SPEED {
232	HCLGE_MAC_SPEED_UNKNOWN = 0,		/* unknown */
233	HCLGE_MAC_SPEED_10M	= 10,		/* 10 Mbps */
234	HCLGE_MAC_SPEED_100M	= 100,		/* 100 Mbps */
235	HCLGE_MAC_SPEED_1G	= 1000,		/* 1000 Mbps   = 1 Gbps */
236	HCLGE_MAC_SPEED_10G	= 10000,	/* 10000 Mbps  = 10 Gbps */
237	HCLGE_MAC_SPEED_25G	= 25000,	/* 25000 Mbps  = 25 Gbps */
238	HCLGE_MAC_SPEED_40G	= 40000,	/* 40000 Mbps  = 40 Gbps */
239	HCLGE_MAC_SPEED_50G	= 50000,	/* 50000 Mbps  = 50 Gbps */
240	HCLGE_MAC_SPEED_100G	= 100000	/* 100000 Mbps = 100 Gbps */
241};
242
243enum HCLGE_MAC_DUPLEX {
244	HCLGE_MAC_HALF,
245	HCLGE_MAC_FULL
246};
247
248#define QUERY_SFP_SPEED		0
249#define QUERY_ACTIVE_SPEED	1
250
251struct hclge_mac {
252	u8 phy_addr;
253	u8 flag;
254	u8 media_type;	/* port media type, e.g. fibre/copper/backplane */
255	u8 mac_addr[ETH_ALEN];
256	u8 autoneg;
257	u8 duplex;
258	u8 support_autoneg;
259	u8 speed_type;	/* 0: sfp speed, 1: active speed */
260	u32 speed;
261	u32 speed_ability; /* speed ability supported by current media */
262	u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
263	u32 fec_mode; /* active fec mode */
264	u32 user_fec_mode;
265	u32 fec_ability;
266	int link;	/* store the link status of mac & phy (if phy exit) */
267	struct phy_device *phydev;
268	struct mii_bus *mdio_bus;
269	phy_interface_t phy_if;
270	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
271	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
272};
273
274struct hclge_hw {
275	void __iomem *io_base;
276	struct hclge_mac mac;
277	int num_vec;
278	struct hclge_cmq cmq;
279};
280
281/* TQP stats */
282struct hlcge_tqp_stats {
283	/* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
284	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
285	/* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
286	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
287};
288
289struct hclge_tqp {
290	/* copy of device pointer from pci_dev,
291	 * used when perform DMA mapping
292	 */
293	struct device *dev;
294	struct hnae3_queue q;
295	struct hlcge_tqp_stats tqp_stats;
296	u16 index;	/* Global index in a NIC controller */
297
298	bool alloced;
299};
300
301enum hclge_fc_mode {
302	HCLGE_FC_NONE,
303	HCLGE_FC_RX_PAUSE,
304	HCLGE_FC_TX_PAUSE,
305	HCLGE_FC_FULL,
306	HCLGE_FC_PFC,
307	HCLGE_FC_DEFAULT
308};
309
310enum hclge_link_fail_code {
311	HCLGE_LF_NORMAL,
312	HCLGE_LF_REF_CLOCK_LOST,
313	HCLGE_LF_XSFP_TX_DISABLE,
314	HCLGE_LF_XSFP_ABSENT,
315};
316
317#define HCLGE_PG_NUM		4
318#define HCLGE_SCH_MODE_SP	0
319#define HCLGE_SCH_MODE_DWRR	1
320struct hclge_pg_info {
321	u8 pg_id;
322	u8 pg_sch_mode;		/* 0: sp; 1: dwrr */
323	u8 tc_bit_map;
324	u32 bw_limit;
325	u8 tc_dwrr[HNAE3_MAX_TC];
326};
327
328struct hclge_tc_info {
329	u8 tc_id;
330	u8 tc_sch_mode;		/* 0: sp; 1: dwrr */
331	u8 pgid;
332	u32 bw_limit;
333};
334
335struct hclge_cfg {
336	u8 vmdq_vport_num;
337	u8 tc_num;
338	u16 tqp_desc_num;
339	u16 rx_buf_len;
340	u16 rss_size_max;
341	u8 phy_addr;
342	u8 media_type;
343	u8 mac_addr[ETH_ALEN];
344	u8 default_speed;
345	u32 numa_node_map;
346	u8 speed_ability;
347	u16 umv_space;
348};
349
350struct hclge_tm_info {
351	u8 num_tc;
352	u8 num_pg;      /* It must be 1 if vNET-Base schd */
353	u8 pg_dwrr[HCLGE_PG_NUM];
354	u8 prio_tc[HNAE3_MAX_USER_PRIO];
355	struct hclge_pg_info pg_info[HCLGE_PG_NUM];
356	struct hclge_tc_info tc_info[HNAE3_MAX_TC];
357	enum hclge_fc_mode fc_mode;
358	u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
359	u8 pfc_en;	/* PFC enabled or not for user priority */
360};
361
362struct hclge_comm_stats_str {
363	char desc[ETH_GSTRING_LEN];
364	unsigned long offset;
365};
366
367/* mac stats ,opcode id: 0x0032 */
368struct hclge_mac_stats {
369	u64 mac_tx_mac_pause_num;
370	u64 mac_rx_mac_pause_num;
371	u64 mac_tx_pfc_pri0_pkt_num;
372	u64 mac_tx_pfc_pri1_pkt_num;
373	u64 mac_tx_pfc_pri2_pkt_num;
374	u64 mac_tx_pfc_pri3_pkt_num;
375	u64 mac_tx_pfc_pri4_pkt_num;
376	u64 mac_tx_pfc_pri5_pkt_num;
377	u64 mac_tx_pfc_pri6_pkt_num;
378	u64 mac_tx_pfc_pri7_pkt_num;
379	u64 mac_rx_pfc_pri0_pkt_num;
380	u64 mac_rx_pfc_pri1_pkt_num;
381	u64 mac_rx_pfc_pri2_pkt_num;
382	u64 mac_rx_pfc_pri3_pkt_num;
383	u64 mac_rx_pfc_pri4_pkt_num;
384	u64 mac_rx_pfc_pri5_pkt_num;
385	u64 mac_rx_pfc_pri6_pkt_num;
386	u64 mac_rx_pfc_pri7_pkt_num;
387	u64 mac_tx_total_pkt_num;
388	u64 mac_tx_total_oct_num;
389	u64 mac_tx_good_pkt_num;
390	u64 mac_tx_bad_pkt_num;
391	u64 mac_tx_good_oct_num;
392	u64 mac_tx_bad_oct_num;
393	u64 mac_tx_uni_pkt_num;
394	u64 mac_tx_multi_pkt_num;
395	u64 mac_tx_broad_pkt_num;
396	u64 mac_tx_undersize_pkt_num;
397	u64 mac_tx_oversize_pkt_num;
398	u64 mac_tx_64_oct_pkt_num;
399	u64 mac_tx_65_127_oct_pkt_num;
400	u64 mac_tx_128_255_oct_pkt_num;
401	u64 mac_tx_256_511_oct_pkt_num;
402	u64 mac_tx_512_1023_oct_pkt_num;
403	u64 mac_tx_1024_1518_oct_pkt_num;
404	u64 mac_tx_1519_2047_oct_pkt_num;
405	u64 mac_tx_2048_4095_oct_pkt_num;
406	u64 mac_tx_4096_8191_oct_pkt_num;
407	u64 rsv0;
408	u64 mac_tx_8192_9216_oct_pkt_num;
409	u64 mac_tx_9217_12287_oct_pkt_num;
410	u64 mac_tx_12288_16383_oct_pkt_num;
411	u64 mac_tx_1519_max_good_oct_pkt_num;
412	u64 mac_tx_1519_max_bad_oct_pkt_num;
413
414	u64 mac_rx_total_pkt_num;
415	u64 mac_rx_total_oct_num;
416	u64 mac_rx_good_pkt_num;
417	u64 mac_rx_bad_pkt_num;
418	u64 mac_rx_good_oct_num;
419	u64 mac_rx_bad_oct_num;
420	u64 mac_rx_uni_pkt_num;
421	u64 mac_rx_multi_pkt_num;
422	u64 mac_rx_broad_pkt_num;
423	u64 mac_rx_undersize_pkt_num;
424	u64 mac_rx_oversize_pkt_num;
425	u64 mac_rx_64_oct_pkt_num;
426	u64 mac_rx_65_127_oct_pkt_num;
427	u64 mac_rx_128_255_oct_pkt_num;
428	u64 mac_rx_256_511_oct_pkt_num;
429	u64 mac_rx_512_1023_oct_pkt_num;
430	u64 mac_rx_1024_1518_oct_pkt_num;
431	u64 mac_rx_1519_2047_oct_pkt_num;
432	u64 mac_rx_2048_4095_oct_pkt_num;
433	u64 mac_rx_4096_8191_oct_pkt_num;
434	u64 rsv1;
435	u64 mac_rx_8192_9216_oct_pkt_num;
436	u64 mac_rx_9217_12287_oct_pkt_num;
437	u64 mac_rx_12288_16383_oct_pkt_num;
438	u64 mac_rx_1519_max_good_oct_pkt_num;
439	u64 mac_rx_1519_max_bad_oct_pkt_num;
440
441	u64 mac_tx_fragment_pkt_num;
442	u64 mac_tx_undermin_pkt_num;
443	u64 mac_tx_jabber_pkt_num;
444	u64 mac_tx_err_all_pkt_num;
445	u64 mac_tx_from_app_good_pkt_num;
446	u64 mac_tx_from_app_bad_pkt_num;
447	u64 mac_rx_fragment_pkt_num;
448	u64 mac_rx_undermin_pkt_num;
449	u64 mac_rx_jabber_pkt_num;
450	u64 mac_rx_fcs_err_pkt_num;
451	u64 mac_rx_send_app_good_pkt_num;
452	u64 mac_rx_send_app_bad_pkt_num;
453	u64 mac_tx_pfc_pause_pkt_num;
454	u64 mac_rx_pfc_pause_pkt_num;
455	u64 mac_tx_ctrl_pkt_num;
456	u64 mac_rx_ctrl_pkt_num;
457};
458
459#define HCLGE_STATS_TIMER_INTERVAL	(60 * 5)
460struct hclge_hw_stats {
461	struct hclge_mac_stats      mac_stats;
462	u32 stats_timer;
463};
464
465struct hclge_vlan_type_cfg {
466	u16 rx_ot_fst_vlan_type;
467	u16 rx_ot_sec_vlan_type;
468	u16 rx_in_fst_vlan_type;
469	u16 rx_in_sec_vlan_type;
470	u16 tx_ot_vlan_type;
471	u16 tx_in_vlan_type;
472};
473
474enum HCLGE_FD_MODE {
475	HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
476	HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
477	HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
478	HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
479};
480
481enum HCLGE_FD_KEY_TYPE {
482	HCLGE_FD_KEY_BASE_ON_PTYPE,
483	HCLGE_FD_KEY_BASE_ON_TUPLE,
484};
485
486enum HCLGE_FD_STAGE {
487	HCLGE_FD_STAGE_1,
488	HCLGE_FD_STAGE_2,
489	MAX_STAGE_NUM,
490};
491
492/* OUTER_XXX indicates tuples in tunnel header of tunnel packet
493 * INNER_XXX indicate tuples in tunneled header of tunnel packet or
494 *           tuples of non-tunnel packet
495 */
496enum HCLGE_FD_TUPLE {
497	OUTER_DST_MAC,
498	OUTER_SRC_MAC,
499	OUTER_VLAN_TAG_FST,
500	OUTER_VLAN_TAG_SEC,
501	OUTER_ETH_TYPE,
502	OUTER_L2_RSV,
503	OUTER_IP_TOS,
504	OUTER_IP_PROTO,
505	OUTER_SRC_IP,
506	OUTER_DST_IP,
507	OUTER_L3_RSV,
508	OUTER_SRC_PORT,
509	OUTER_DST_PORT,
510	OUTER_L4_RSV,
511	OUTER_TUN_VNI,
512	OUTER_TUN_FLOW_ID,
513	INNER_DST_MAC,
514	INNER_SRC_MAC,
515	INNER_VLAN_TAG_FST,
516	INNER_VLAN_TAG_SEC,
517	INNER_ETH_TYPE,
518	INNER_L2_RSV,
519	INNER_IP_TOS,
520	INNER_IP_PROTO,
521	INNER_SRC_IP,
522	INNER_DST_IP,
523	INNER_L3_RSV,
524	INNER_SRC_PORT,
525	INNER_DST_PORT,
526	INNER_L4_RSV,
527	MAX_TUPLE,
528};
529
530enum HCLGE_FD_META_DATA {
531	PACKET_TYPE_ID,
532	IP_FRAGEMENT,
533	ROCE_TYPE,
534	NEXT_KEY,
535	VLAN_NUMBER,
536	SRC_VPORT,
537	DST_VPORT,
538	TUNNEL_PACKET,
539	MAX_META_DATA,
540};
541
542struct key_info {
543	u8 key_type;
544	u8 key_length; /* use bit as unit */
545};
546
547#define MAX_KEY_LENGTH	400
548#define MAX_KEY_DWORDS	DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
549#define MAX_KEY_BYTES	(MAX_KEY_DWORDS * 4)
550#define MAX_META_DATA_LENGTH	32
551
552/* assigned by firmware, the real filter number for each pf may be less */
553#define MAX_FD_FILTER_NUM	4096
554#define HCLGE_FD_ARFS_EXPIRE_TIMER_INTERVAL	5
555
556enum HCLGE_FD_ACTIVE_RULE_TYPE {
557	HCLGE_FD_RULE_NONE,
558	HCLGE_FD_ARFS_ACTIVE,
559	HCLGE_FD_EP_ACTIVE,
560};
561
562enum HCLGE_FD_PACKET_TYPE {
563	NIC_PACKET,
564	ROCE_PACKET,
565};
566
567enum HCLGE_FD_ACTION {
568	HCLGE_FD_ACTION_ACCEPT_PACKET,
569	HCLGE_FD_ACTION_DROP_PACKET,
570};
571
572struct hclge_fd_key_cfg {
573	u8 key_sel;
574	u8 inner_sipv6_word_en;
575	u8 inner_dipv6_word_en;
576	u8 outer_sipv6_word_en;
577	u8 outer_dipv6_word_en;
578	u32 tuple_active;
579	u32 meta_data_active;
580};
581
582struct hclge_fd_cfg {
583	u8 fd_mode;
584	u16 max_key_length; /* use bit as unit */
585	u32 proto_support;
586	u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
587	u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
588	struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
589};
590
591#define IPV4_INDEX	3
592#define IPV6_SIZE	4
593struct hclge_fd_rule_tuples {
594	u8 src_mac[ETH_ALEN];
595	u8 dst_mac[ETH_ALEN];
596	/* Be compatible for ip address of both ipv4 and ipv6.
597	 * For ipv4 address, we store it in src/dst_ip[3].
598	 */
599	u32 src_ip[IPV6_SIZE];
600	u32 dst_ip[IPV6_SIZE];
601	u16 src_port;
602	u16 dst_port;
603	u16 vlan_tag1;
604	u16 ether_proto;
605	u8 ip_tos;
606	u8 ip_proto;
607};
608
609struct hclge_fd_rule {
610	struct hlist_node rule_node;
611	struct hclge_fd_rule_tuples tuples;
612	struct hclge_fd_rule_tuples tuples_mask;
613	u32 unused_tuple;
614	u32 flow_type;
615	u8 action;
616	u16 vf_id;
617	u16 queue_id;
618	u16 location;
619	u16 flow_id;	/* only used for arfs */
620	enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
621};
622
623struct hclge_fd_ad_data {
624	u16 ad_id;
625	u8 drop_packet;
626	u8 forward_to_direct_queue;
627	u16 queue_id;
628	u8 use_counter;
629	u8 counter_id;
630	u8 use_next_stage;
631	u8 write_rule_id_to_bd;
632	u8 next_input_key;
633	u16 rule_id;
634};
635
636struct hclge_vport_mac_addr_cfg {
637	struct list_head node;
638	int hd_tbl_status;
639	u8 mac_addr[ETH_ALEN];
640};
641
642enum HCLGE_MAC_ADDR_TYPE {
643	HCLGE_MAC_ADDR_UC,
644	HCLGE_MAC_ADDR_MC
645};
646
647struct hclge_vport_vlan_cfg {
648	struct list_head node;
649	int hd_tbl_status;
650	u16 vlan_id;
651};
652
653struct hclge_rst_stats {
654	u32 reset_done_cnt;	/* the number of reset has completed */
655	u32 hw_reset_done_cnt;	/* the number of HW reset has completed */
656	u32 pf_rst_cnt;		/* the number of PF reset */
657	u32 flr_rst_cnt;	/* the number of FLR */
658	u32 core_rst_cnt;	/* the number of CORE reset */
659	u32 global_rst_cnt;	/* the number of GLOBAL */
660	u32 imp_rst_cnt;	/* the number of IMP reset */
661	u32 reset_cnt;		/* the number of reset */
662	u32 reset_fail_cnt;	/* the number of reset fail */
663};
664
665/* time and register status when mac tunnel interruption occur */
666struct hclge_mac_tnl_stats {
667	u64 time;
668	u32 status;
669};
670
671#define HCLGE_RESET_INTERVAL	(10 * HZ)
672#define HCLGE_WAIT_RESET_DONE	100
673
674#pragma pack(1)
675struct hclge_vf_vlan_cfg {
676	u8 mbx_cmd;
677	u8 subcode;
678	u8 is_kill;
679	u16 vlan;
680	u16 proto;
681};
682
683#pragma pack()
684
685/* For each bit of TCAM entry, it uses a pair of 'x' and
686 * 'y' to indicate which value to match, like below:
687 * ----------------------------------
688 * | bit x | bit y |  search value  |
689 * ----------------------------------
690 * |   0   |   0   |   always hit   |
691 * ----------------------------------
692 * |   1   |   0   |   match '0'    |
693 * ----------------------------------
694 * |   0   |   1   |   match '1'    |
695 * ----------------------------------
696 * |   1   |   1   |   invalid      |
697 * ----------------------------------
698 * Then for input key(k) and mask(v), we can calculate the value by
699 * the formulae:
700 *	x = (~k) & v
701 *	y = (k ^ ~v) & k
702 */
703#define calc_x(x, k, v) ((x) = (~(k) & (v)))
704#define calc_y(y, k, v) \
705	do { \
706		const typeof(k) _k_ = (k); \
707		const typeof(v) _v_ = (v); \
708		(y) = (_k_ ^ ~_v_) & (_k_); \
709	} while (0)
710
711#define HCLGE_MAC_TNL_LOG_SIZE	8
712#define HCLGE_VPORT_NUM 256
713struct hclge_dev {
714	struct pci_dev *pdev;
715	struct hnae3_ae_dev *ae_dev;
716	struct hclge_hw hw;
717	struct hclge_misc_vector misc_vector;
718	struct hclge_hw_stats hw_stats;
719	unsigned long state;
720	unsigned long flr_state;
721	unsigned long last_reset_time;
722
723	enum hnae3_reset_type reset_type;
724	enum hnae3_reset_type reset_level;
725	unsigned long default_reset_request;
726	unsigned long reset_request;	/* reset has been requested */
727	unsigned long reset_pending;	/* client rst is pending to be served */
728	struct hclge_rst_stats rst_stats;
729	u32 fw_version;
730	u16 num_vmdq_vport;		/* Num vmdq vport this PF has set up */
731	u16 num_tqps;			/* Num task queue pairs of this PF */
732	u16 num_req_vfs;		/* Num VFs requested for this PF */
733
734	u16 base_tqp_pid;	/* Base task tqp physical id of this PF */
735	u16 alloc_rss_size;		/* Allocated RSS task queue */
736	u16 rss_size_max;		/* HW defined max RSS task queue */
737
738	u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
739	u16 num_alloc_vport;		/* Num vports this driver supports */
740	u32 numa_node_mask;
741	u16 rx_buf_len;
742	u16 num_tx_desc;		/* desc num of per tx queue */
743	u16 num_rx_desc;		/* desc num of per rx queue */
744	u8 hw_tc_map;
745	u8 tc_num_last_time;
746	enum hclge_fc_mode fc_mode_last_time;
747	u8 support_sfp_query;
748
749#define HCLGE_FLAG_TC_BASE_SCH_MODE		1
750#define HCLGE_FLAG_VNET_BASE_SCH_MODE		2
751	u8 tx_sch_mode;
752	u8 tc_max;
753	u8 pfc_max;
754
755	u8 default_up;
756	u8 dcbx_cap;
757	struct hclge_tm_info tm_info;
758
759	u16 num_msi;
760	u16 num_msi_left;
761	u16 num_msi_used;
762	u16 roce_base_msix_offset;
763	u32 base_msi_vector;
764	u16 *vector_status;
765	int *vector_irq;
766	u16 num_nic_msi;	/* Num of nic vectors for this PF */
767	u16 num_roce_msi;	/* Num of roce vectors for this PF */
768	int roce_base_vector;
769
770	u16 pending_udp_bitmap;
771
772	u16 rx_itr_default;
773	u16 tx_itr_default;
774
775	u16 adminq_work_limit; /* Num of admin receive queue desc to process */
776	unsigned long service_timer_period;
777	unsigned long service_timer_previous;
778	struct timer_list reset_timer;
779	struct delayed_work service_task;
780	struct work_struct rst_service_task;
781	struct work_struct mbx_service_task;
782
783	bool cur_promisc;
784	int num_alloc_vfs;	/* Actual number of VFs allocated */
785
786	struct hclge_tqp *htqp;
787	struct hclge_vport *vport;
788
789	struct dentry *hclge_dbgfs;
790
791	struct hnae3_client *nic_client;
792	struct hnae3_client *roce_client;
793
794#define HCLGE_FLAG_MAIN			BIT(0)
795#define HCLGE_FLAG_DCB_CAPABLE		BIT(1)
796#define HCLGE_FLAG_DCB_ENABLE		BIT(2)
797#define HCLGE_FLAG_MQPRIO_ENABLE	BIT(3)
798	u32 flag;
799
800	u32 pkt_buf_size; /* Total pf buf size for tx/rx */
801	u32 tx_buf_size; /* Tx buffer size for each TC */
802	u32 dv_buf_size; /* Dv buffer size for each TC */
803
804	u32 mps; /* Max packet size */
805	/* vport_lock protect resource shared by vports */
806	struct mutex vport_lock;
807
808	struct hclge_vlan_type_cfg vlan_type_cfg;
809
810	unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
811	unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
812
813	struct hclge_fd_cfg fd_cfg;
814	struct hlist_head fd_rule_list;
815	spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
816	u16 hclge_fd_rule_num;
817	u16 fd_arfs_expire_timer;
818	unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
819	enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
820	u8 fd_en;
821
822	u16 wanted_umv_size;
823	/* max available unicast mac vlan space */
824	u16 max_umv_size;
825	/* private unicast mac vlan space, it's same for PF and its VFs */
826	u16 priv_umv_size;
827	/* unicast mac vlan space shared by PF and its VFs */
828	u16 share_umv_size;
829	struct mutex umv_mutex; /* protect share_umv_size */
830
831	struct mutex vport_cfg_mutex;   /* Protect stored vf table */
832
833	DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
834		      HCLGE_MAC_TNL_LOG_SIZE);
835
836	/* affinity mask and notify for misc interrupt */
837	cpumask_t affinity_mask;
838	struct irq_affinity_notify affinity_notify;
839};
840
841/* VPort level vlan tag configuration for TX direction */
842struct hclge_tx_vtag_cfg {
843	bool accept_tag1;	/* Whether accept tag1 packet from host */
844	bool accept_untag1;	/* Whether accept untag1 packet from host */
845	bool accept_tag2;
846	bool accept_untag2;
847	bool insert_tag1_en;	/* Whether insert inner vlan tag */
848	bool insert_tag2_en;	/* Whether insert outer vlan tag */
849	u16  default_tag1;	/* The default inner vlan tag to insert */
850	u16  default_tag2;	/* The default outer vlan tag to insert */
851};
852
853/* VPort level vlan tag configuration for RX direction */
854struct hclge_rx_vtag_cfg {
855	u8 rx_vlan_offload_en;	/* Whether enable rx vlan offload */
856	u8 strip_tag1_en;	/* Whether strip inner vlan tag */
857	u8 strip_tag2_en;	/* Whether strip outer vlan tag */
858	u8 vlan1_vlan_prionly;	/* Inner VLAN Tag up to descriptor Enable */
859	u8 vlan2_vlan_prionly;	/* Outer VLAN Tag up to descriptor Enable */
860};
861
862struct hclge_rss_tuple_cfg {
863	u8 ipv4_tcp_en;
864	u8 ipv4_udp_en;
865	u8 ipv4_sctp_en;
866	u8 ipv4_fragment_en;
867	u8 ipv6_tcp_en;
868	u8 ipv6_udp_en;
869	u8 ipv6_sctp_en;
870	u8 ipv6_fragment_en;
871};
872
873enum HCLGE_VPORT_STATE {
874	HCLGE_VPORT_STATE_ALIVE,
875	HCLGE_VPORT_STATE_MAX
876};
877
878struct hclge_vlan_info {
879	u16 vlan_proto; /* so far support 802.1Q only */
880	u16 qos;
881	u16 vlan_tag;
882};
883
884struct hclge_port_base_vlan_config {
885	u16 state;
886	struct hclge_vlan_info vlan_info;
887};
888
889struct hclge_vport {
890	u16 alloc_tqps;	/* Allocated Tx/Rx queues */
891
892	u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
893	/* User configured lookup table entries */
894	u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
895	int rss_algo;		/* User configured hash algorithm */
896	/* User configured rss tuple sets */
897	struct hclge_rss_tuple_cfg rss_tuple_sets;
898
899	u16 alloc_rss_size;
900
901	u16 qs_offset;
902	u32 bw_limit;		/* VSI BW Limit (0 = disabled) */
903	u8  dwrr;
904
905	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
906	struct hclge_port_base_vlan_config port_base_vlan_cfg;
907	struct hclge_tx_vtag_cfg  txvlan_cfg;
908	struct hclge_rx_vtag_cfg  rxvlan_cfg;
909
910	u16 used_umv_num;
911
912	u16 vport_id;
913	struct hclge_dev *back;  /* Back reference to associated dev */
914	struct hnae3_handle nic;
915	struct hnae3_handle roce;
916
917	unsigned long state;
918	unsigned long last_active_jiffies;
919	u32 mps; /* Max packet size */
920
921	struct list_head uc_mac_list;   /* Store VF unicast table */
922	struct list_head mc_mac_list;   /* Store VF multicast table */
923	struct list_head vlan_list;     /* Store VF vlan table */
924};
925
926void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
927			      bool en_mc, bool en_bc, int vport_id);
928
929int hclge_add_uc_addr_common(struct hclge_vport *vport,
930			     const unsigned char *addr);
931int hclge_rm_uc_addr_common(struct hclge_vport *vport,
932			    const unsigned char *addr);
933int hclge_add_mc_addr_common(struct hclge_vport *vport,
934			     const unsigned char *addr);
935int hclge_rm_mc_addr_common(struct hclge_vport *vport,
936			    const unsigned char *addr);
937
938struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
939int hclge_bind_ring_with_vector(struct hclge_vport *vport,
940				int vector_id, bool en,
941				struct hnae3_ring_chain_node *ring_chain);
942
943static inline int hclge_get_queue_id(struct hnae3_queue *queue)
944{
945	struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
946
947	return tqp->index;
948}
949
950static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
951{
952	return !!hdev->reset_pending;
953}
954
955int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
956int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
957int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
958			  u16 vlan_id, bool is_kill);
959int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
960
961int hclge_buffer_alloc(struct hclge_dev *hdev);
962int hclge_rss_init_hw(struct hclge_dev *hdev);
963void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
964
965void hclge_mbx_handler(struct hclge_dev *hdev);
966int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
967void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
968int hclge_cfg_flowctrl(struct hclge_dev *hdev);
969int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
970int hclge_vport_start(struct hclge_vport *vport);
971void hclge_vport_stop(struct hclge_vport *vport);
972int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
973int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf);
974u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
975int hclge_notify_client(struct hclge_dev *hdev,
976			enum hnae3_reset_notify_type type);
977void hclge_add_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr,
978			       enum HCLGE_MAC_ADDR_TYPE mac_type);
979void hclge_rm_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr,
980			      bool is_write_tbl,
981			      enum HCLGE_MAC_ADDR_TYPE mac_type);
982void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
983				  enum HCLGE_MAC_ADDR_TYPE mac_type);
984void hclge_uninit_vport_mac_table(struct hclge_dev *hdev);
985void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
986void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
987int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
988				    struct hclge_vlan_info *vlan_info);
989int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
990				      u16 state, u16 vlan_tag, u16 qos,
991				      u16 vlan_proto);
992void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
993int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
994				struct hclge_desc *desc);
995void hclge_report_hw_error(struct hclge_dev *hdev,
996			   enum hnae3_hw_error_type type);
997#endif