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/drivers/soundwire/intel.c

https://codeberg.org/ddevault/linux
C | 1114 lines | 806 code | 223 blank | 85 comment | 93 complexity | 2fabf89ace572ff6132cd9a5cb73efbf MD5 | raw file
Possible License(s): GPL-2.0
  1. // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
  2. // Copyright(c) 2015-17 Intel Corporation.
  3. /*
  4. * Soundwire Intel Master Driver
  5. */
  6. #include <linux/acpi.h>
  7. #include <linux/debugfs.h>
  8. #include <linux/delay.h>
  9. #include <linux/module.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/platform_device.h>
  12. #include <sound/pcm_params.h>
  13. #include <sound/soc.h>
  14. #include <linux/soundwire/sdw_registers.h>
  15. #include <linux/soundwire/sdw.h>
  16. #include <linux/soundwire/sdw_intel.h>
  17. #include "cadence_master.h"
  18. #include "bus.h"
  19. #include "intel.h"
  20. /* Intel SHIM Registers Definition */
  21. #define SDW_SHIM_LCAP 0x0
  22. #define SDW_SHIM_LCTL 0x4
  23. #define SDW_SHIM_IPPTR 0x8
  24. #define SDW_SHIM_SYNC 0xC
  25. #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
  26. #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
  27. #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
  28. #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
  29. #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
  30. #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
  31. #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
  32. #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
  33. #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
  34. #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
  35. #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
  36. #define SDW_SHIM_WAKEEN 0x190
  37. #define SDW_SHIM_WAKESTS 0x192
  38. #define SDW_SHIM_LCTL_SPA BIT(0)
  39. #define SDW_SHIM_LCTL_CPA BIT(8)
  40. #define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
  41. #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
  42. #define SDW_SHIM_SYNC_SYNCCPU BIT(15)
  43. #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
  44. #define SDW_SHIM_SYNC_CMDSYNC BIT(16)
  45. #define SDW_SHIM_SYNC_SYNCGO BIT(24)
  46. #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
  47. #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
  48. #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
  49. #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
  50. #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
  51. #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
  52. #define SDW_SHIM_PCMSYCM_DIR BIT(15)
  53. #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
  54. #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
  55. #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
  56. #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
  57. #define SDW_SHIM_IOCTL_MIF BIT(0)
  58. #define SDW_SHIM_IOCTL_CO BIT(1)
  59. #define SDW_SHIM_IOCTL_COE BIT(2)
  60. #define SDW_SHIM_IOCTL_DO BIT(3)
  61. #define SDW_SHIM_IOCTL_DOE BIT(4)
  62. #define SDW_SHIM_IOCTL_BKE BIT(5)
  63. #define SDW_SHIM_IOCTL_WPDD BIT(6)
  64. #define SDW_SHIM_IOCTL_CIBD BIT(8)
  65. #define SDW_SHIM_IOCTL_DIBD BIT(9)
  66. #define SDW_SHIM_CTMCTL_DACTQE BIT(0)
  67. #define SDW_SHIM_CTMCTL_DODS BIT(1)
  68. #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
  69. #define SDW_SHIM_WAKEEN_ENABLE BIT(0)
  70. #define SDW_SHIM_WAKESTS_STATUS BIT(0)
  71. /* Intel ALH Register definitions */
  72. #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
  73. #define SDW_ALH_NUM_STREAMS 64
  74. #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
  75. #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
  76. #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
  77. #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
  78. enum intel_pdi_type {
  79. INTEL_PDI_IN = 0,
  80. INTEL_PDI_OUT = 1,
  81. INTEL_PDI_BD = 2,
  82. };
  83. struct sdw_intel {
  84. struct sdw_cdns cdns;
  85. int instance;
  86. struct sdw_intel_link_res *res;
  87. #ifdef CONFIG_DEBUG_FS
  88. struct dentry *debugfs;
  89. #endif
  90. };
  91. #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
  92. /*
  93. * Read, write helpers for HW registers
  94. */
  95. static inline int intel_readl(void __iomem *base, int offset)
  96. {
  97. return readl(base + offset);
  98. }
  99. static inline void intel_writel(void __iomem *base, int offset, int value)
  100. {
  101. writel(value, base + offset);
  102. }
  103. static inline u16 intel_readw(void __iomem *base, int offset)
  104. {
  105. return readw(base + offset);
  106. }
  107. static inline void intel_writew(void __iomem *base, int offset, u16 value)
  108. {
  109. writew(value, base + offset);
  110. }
  111. static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
  112. {
  113. int timeout = 10;
  114. u32 reg_read;
  115. writel(value, base + offset);
  116. do {
  117. reg_read = readl(base + offset);
  118. if (!(reg_read & mask))
  119. return 0;
  120. timeout--;
  121. udelay(50);
  122. } while (timeout != 0);
  123. return -EAGAIN;
  124. }
  125. static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
  126. {
  127. int timeout = 10;
  128. u32 reg_read;
  129. writel(value, base + offset);
  130. do {
  131. reg_read = readl(base + offset);
  132. if (reg_read & mask)
  133. return 0;
  134. timeout--;
  135. udelay(50);
  136. } while (timeout != 0);
  137. return -EAGAIN;
  138. }
  139. /*
  140. * debugfs
  141. */
  142. #ifdef CONFIG_DEBUG_FS
  143. #define RD_BUF (2 * PAGE_SIZE)
  144. static ssize_t intel_sprintf(void __iomem *mem, bool l,
  145. char *buf, size_t pos, unsigned int reg)
  146. {
  147. int value;
  148. if (l)
  149. value = intel_readl(mem, reg);
  150. else
  151. value = intel_readw(mem, reg);
  152. return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
  153. }
  154. static int intel_reg_show(struct seq_file *s_file, void *data)
  155. {
  156. struct sdw_intel *sdw = s_file->private;
  157. void __iomem *s = sdw->res->shim;
  158. void __iomem *a = sdw->res->alh;
  159. char *buf;
  160. ssize_t ret;
  161. int i, j;
  162. unsigned int links, reg;
  163. buf = kzalloc(RD_BUF, GFP_KERNEL);
  164. if (!buf)
  165. return -ENOMEM;
  166. links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
  167. ret = scnprintf(buf, RD_BUF, "Register Value\n");
  168. ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
  169. for (i = 0; i < links; i++) {
  170. reg = SDW_SHIM_LCAP + i * 4;
  171. ret += intel_sprintf(s, true, buf, ret, reg);
  172. }
  173. for (i = 0; i < links; i++) {
  174. ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
  175. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
  176. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
  177. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
  178. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
  179. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
  180. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
  181. ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
  182. /*
  183. * the value 10 is the number of PDIs. We will need a
  184. * cleanup to remove hard-coded Intel configurations
  185. * from cadence_master.c
  186. */
  187. for (j = 0; j < 10; j++) {
  188. ret += intel_sprintf(s, false, buf, ret,
  189. SDW_SHIM_PCMSYCHM(i, j));
  190. ret += intel_sprintf(s, false, buf, ret,
  191. SDW_SHIM_PCMSYCHC(i, j));
  192. }
  193. ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
  194. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
  195. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
  196. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
  197. }
  198. ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
  199. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
  200. ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
  201. ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
  202. for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
  203. ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
  204. seq_printf(s_file, "%s", buf);
  205. kfree(buf);
  206. return 0;
  207. }
  208. DEFINE_SHOW_ATTRIBUTE(intel_reg);
  209. static void intel_debugfs_init(struct sdw_intel *sdw)
  210. {
  211. struct dentry *root = sdw->cdns.bus.debugfs;
  212. if (!root)
  213. return;
  214. sdw->debugfs = debugfs_create_dir("intel-sdw", root);
  215. debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
  216. &intel_reg_fops);
  217. sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
  218. }
  219. static void intel_debugfs_exit(struct sdw_intel *sdw)
  220. {
  221. debugfs_remove_recursive(sdw->debugfs);
  222. }
  223. #else
  224. static void intel_debugfs_init(struct sdw_intel *sdw) {}
  225. static void intel_debugfs_exit(struct sdw_intel *sdw) {}
  226. #endif /* CONFIG_DEBUG_FS */
  227. /*
  228. * shim ops
  229. */
  230. static int intel_link_power_up(struct sdw_intel *sdw)
  231. {
  232. unsigned int link_id = sdw->instance;
  233. void __iomem *shim = sdw->res->shim;
  234. int spa_mask, cpa_mask;
  235. int link_control, ret;
  236. /* Link power up sequence */
  237. link_control = intel_readl(shim, SDW_SHIM_LCTL);
  238. spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
  239. cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
  240. link_control |= spa_mask;
  241. ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
  242. if (ret < 0)
  243. return ret;
  244. sdw->cdns.link_up = true;
  245. return 0;
  246. }
  247. static int intel_shim_init(struct sdw_intel *sdw)
  248. {
  249. void __iomem *shim = sdw->res->shim;
  250. unsigned int link_id = sdw->instance;
  251. int sync_reg, ret;
  252. u16 ioctl = 0, act = 0;
  253. /* Initialize Shim */
  254. ioctl |= SDW_SHIM_IOCTL_BKE;
  255. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  256. ioctl |= SDW_SHIM_IOCTL_WPDD;
  257. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  258. ioctl |= SDW_SHIM_IOCTL_DO;
  259. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  260. ioctl |= SDW_SHIM_IOCTL_DOE;
  261. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  262. /* Switch to MIP from Glue logic */
  263. ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
  264. ioctl &= ~(SDW_SHIM_IOCTL_DOE);
  265. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  266. ioctl &= ~(SDW_SHIM_IOCTL_DO);
  267. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  268. ioctl |= (SDW_SHIM_IOCTL_MIF);
  269. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  270. ioctl &= ~(SDW_SHIM_IOCTL_BKE);
  271. ioctl &= ~(SDW_SHIM_IOCTL_COE);
  272. intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
  273. act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
  274. act |= SDW_SHIM_CTMCTL_DACTQE;
  275. act |= SDW_SHIM_CTMCTL_DODS;
  276. intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
  277. /* Now set SyncPRD period */
  278. sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
  279. sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
  280. SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
  281. /* Set SyncCPU bit */
  282. sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
  283. ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
  284. SDW_SHIM_SYNC_SYNCCPU);
  285. if (ret < 0)
  286. dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
  287. return ret;
  288. }
  289. /*
  290. * PDI routines
  291. */
  292. static void intel_pdi_init(struct sdw_intel *sdw,
  293. struct sdw_cdns_stream_config *config)
  294. {
  295. void __iomem *shim = sdw->res->shim;
  296. unsigned int link_id = sdw->instance;
  297. int pcm_cap, pdm_cap;
  298. /* PCM Stream Capability */
  299. pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
  300. config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
  301. SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
  302. config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
  303. SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
  304. config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
  305. SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
  306. dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
  307. config->pcm_bd, config->pcm_in, config->pcm_out);
  308. /* PDM Stream Capability */
  309. pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
  310. config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
  311. SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
  312. config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
  313. SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
  314. config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
  315. SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
  316. dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
  317. config->pdm_bd, config->pdm_in, config->pdm_out);
  318. }
  319. static int
  320. intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
  321. {
  322. void __iomem *shim = sdw->res->shim;
  323. unsigned int link_id = sdw->instance;
  324. int count;
  325. if (pcm) {
  326. count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
  327. /*
  328. * WORKAROUND: on all existing Intel controllers, pdi
  329. * number 2 reports channel count as 1 even though it
  330. * supports 8 channels. Performing hardcoding for pdi
  331. * number 2.
  332. */
  333. if (pdi_num == 2)
  334. count = 7;
  335. } else {
  336. count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
  337. count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
  338. SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
  339. }
  340. /* zero based values for channel count in register */
  341. count++;
  342. return count;
  343. }
  344. static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
  345. struct sdw_cdns_pdi *pdi,
  346. unsigned int num_pdi,
  347. unsigned int *num_ch, bool pcm)
  348. {
  349. int i, ch_count = 0;
  350. for (i = 0; i < num_pdi; i++) {
  351. pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
  352. ch_count += pdi->ch_count;
  353. pdi++;
  354. }
  355. *num_ch = ch_count;
  356. return 0;
  357. }
  358. static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
  359. struct sdw_cdns_streams *stream, bool pcm)
  360. {
  361. intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
  362. &stream->num_ch_bd, pcm);
  363. intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
  364. &stream->num_ch_in, pcm);
  365. intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
  366. &stream->num_ch_out, pcm);
  367. return 0;
  368. }
  369. static int intel_pdi_ch_update(struct sdw_intel *sdw)
  370. {
  371. /* First update PCM streams followed by PDM streams */
  372. intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
  373. intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
  374. return 0;
  375. }
  376. static void
  377. intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
  378. {
  379. void __iomem *shim = sdw->res->shim;
  380. unsigned int link_id = sdw->instance;
  381. int pdi_conf = 0;
  382. pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
  383. /*
  384. * Program stream parameters to stream SHIM register
  385. * This is applicable for PCM stream only.
  386. */
  387. if (pdi->type != SDW_STREAM_PCM)
  388. return;
  389. if (pdi->dir == SDW_DATA_DIR_RX)
  390. pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
  391. else
  392. pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
  393. pdi_conf |= (pdi->intel_alh_id <<
  394. SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
  395. pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
  396. pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
  397. intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
  398. }
  399. static void
  400. intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
  401. {
  402. void __iomem *alh = sdw->res->alh;
  403. unsigned int link_id = sdw->instance;
  404. unsigned int conf;
  405. pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
  406. /* Program Stream config ALH register */
  407. conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
  408. conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
  409. SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
  410. conf |= ((pdi->ch_count - 1) <<
  411. SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
  412. intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
  413. }
  414. static int intel_config_stream(struct sdw_intel *sdw,
  415. struct snd_pcm_substream *substream,
  416. struct snd_soc_dai *dai,
  417. struct snd_pcm_hw_params *hw_params, int link_id)
  418. {
  419. struct sdw_intel_link_res *res = sdw->res;
  420. if (res->ops && res->ops->config_stream && res->arg)
  421. return res->ops->config_stream(res->arg,
  422. substream, dai, hw_params, link_id);
  423. return -EIO;
  424. }
  425. /*
  426. * bank switch routines
  427. */
  428. static int intel_pre_bank_switch(struct sdw_bus *bus)
  429. {
  430. struct sdw_cdns *cdns = bus_to_cdns(bus);
  431. struct sdw_intel *sdw = cdns_to_intel(cdns);
  432. void __iomem *shim = sdw->res->shim;
  433. int sync_reg;
  434. /* Write to register only for multi-link */
  435. if (!bus->multi_link)
  436. return 0;
  437. /* Read SYNC register */
  438. sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
  439. sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
  440. intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
  441. return 0;
  442. }
  443. static int intel_post_bank_switch(struct sdw_bus *bus)
  444. {
  445. struct sdw_cdns *cdns = bus_to_cdns(bus);
  446. struct sdw_intel *sdw = cdns_to_intel(cdns);
  447. void __iomem *shim = sdw->res->shim;
  448. int sync_reg, ret;
  449. /* Write to register only for multi-link */
  450. if (!bus->multi_link)
  451. return 0;
  452. /* Read SYNC register */
  453. sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
  454. /*
  455. * post_bank_switch() ops is called from the bus in loop for
  456. * all the Masters in the steam with the expectation that
  457. * we trigger the bankswitch for the only first Master in the list
  458. * and do nothing for the other Masters
  459. *
  460. * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
  461. */
  462. if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
  463. return 0;
  464. /*
  465. * Set SyncGO bit to synchronously trigger a bank switch for
  466. * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
  467. * the Masters.
  468. */
  469. sync_reg |= SDW_SHIM_SYNC_SYNCGO;
  470. ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
  471. SDW_SHIM_SYNC_SYNCGO);
  472. if (ret < 0)
  473. dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
  474. return ret;
  475. }
  476. /*
  477. * DAI routines
  478. */
  479. static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw,
  480. u32 ch, u32 dir, bool pcm)
  481. {
  482. struct sdw_cdns *cdns = &sdw->cdns;
  483. struct sdw_cdns_port *port = NULL;
  484. int i, ret = 0;
  485. for (i = 0; i < cdns->num_ports; i++) {
  486. if (cdns->ports[i].assigned)
  487. continue;
  488. port = &cdns->ports[i];
  489. port->assigned = true;
  490. port->direction = dir;
  491. port->ch = ch;
  492. break;
  493. }
  494. if (!port) {
  495. dev_err(cdns->dev, "Unable to find a free port\n");
  496. return NULL;
  497. }
  498. if (pcm) {
  499. ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir);
  500. if (ret)
  501. goto out;
  502. intel_pdi_shim_configure(sdw, port->pdi);
  503. sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi);
  504. intel_pdi_alh_configure(sdw, port->pdi);
  505. } else {
  506. ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir);
  507. }
  508. out:
  509. if (ret) {
  510. port->assigned = false;
  511. port = NULL;
  512. }
  513. return port;
  514. }
  515. static void intel_port_cleanup(struct sdw_cdns_dma_data *dma)
  516. {
  517. int i;
  518. for (i = 0; i < dma->nr_ports; i++) {
  519. if (dma->port[i]) {
  520. dma->port[i]->pdi->assigned = false;
  521. dma->port[i]->pdi = NULL;
  522. dma->port[i]->assigned = false;
  523. dma->port[i] = NULL;
  524. }
  525. }
  526. }
  527. static int intel_hw_params(struct snd_pcm_substream *substream,
  528. struct snd_pcm_hw_params *params,
  529. struct snd_soc_dai *dai)
  530. {
  531. struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
  532. struct sdw_intel *sdw = cdns_to_intel(cdns);
  533. struct sdw_cdns_dma_data *dma;
  534. struct sdw_stream_config sconfig;
  535. struct sdw_port_config *pconfig;
  536. int ret, i, ch, dir;
  537. bool pcm = true;
  538. dma = snd_soc_dai_get_dma_data(dai, substream);
  539. if (!dma)
  540. return -EIO;
  541. ch = params_channels(params);
  542. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  543. dir = SDW_DATA_DIR_RX;
  544. else
  545. dir = SDW_DATA_DIR_TX;
  546. if (dma->stream_type == SDW_STREAM_PDM) {
  547. /* TODO: Check whether PDM decimator is already in use */
  548. dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir);
  549. pcm = false;
  550. } else {
  551. dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir);
  552. }
  553. if (!dma->nr_ports) {
  554. dev_err(dai->dev, "ports/resources not available\n");
  555. return -EINVAL;
  556. }
  557. dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL);
  558. if (!dma->port)
  559. return -ENOMEM;
  560. for (i = 0; i < dma->nr_ports; i++) {
  561. dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm);
  562. if (!dma->port[i]) {
  563. ret = -EINVAL;
  564. goto port_error;
  565. }
  566. }
  567. /* Inform DSP about PDI stream number */
  568. for (i = 0; i < dma->nr_ports; i++) {
  569. ret = intel_config_stream(sdw, substream, dai, params,
  570. dma->port[i]->pdi->intel_alh_id);
  571. if (ret)
  572. goto port_error;
  573. }
  574. sconfig.direction = dir;
  575. sconfig.ch_count = ch;
  576. sconfig.frame_rate = params_rate(params);
  577. sconfig.type = dma->stream_type;
  578. if (dma->stream_type == SDW_STREAM_PDM) {
  579. sconfig.frame_rate *= 50;
  580. sconfig.bps = 1;
  581. } else {
  582. sconfig.bps = snd_pcm_format_width(params_format(params));
  583. }
  584. /* Port configuration */
  585. pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL);
  586. if (!pconfig) {
  587. ret = -ENOMEM;
  588. goto port_error;
  589. }
  590. for (i = 0; i < dma->nr_ports; i++) {
  591. pconfig[i].num = dma->port[i]->num;
  592. pconfig[i].ch_mask = (1 << ch) - 1;
  593. }
  594. ret = sdw_stream_add_master(&cdns->bus, &sconfig,
  595. pconfig, dma->nr_ports, dma->stream);
  596. if (ret) {
  597. dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
  598. goto stream_error;
  599. }
  600. kfree(pconfig);
  601. return ret;
  602. stream_error:
  603. kfree(pconfig);
  604. port_error:
  605. intel_port_cleanup(dma);
  606. kfree(dma->port);
  607. return ret;
  608. }
  609. static int
  610. intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
  611. {
  612. struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
  613. struct sdw_cdns_dma_data *dma;
  614. int ret;
  615. dma = snd_soc_dai_get_dma_data(dai, substream);
  616. if (!dma)
  617. return -EIO;
  618. ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
  619. if (ret < 0)
  620. dev_err(dai->dev, "remove master from stream %s failed: %d\n",
  621. dma->stream->name, ret);
  622. intel_port_cleanup(dma);
  623. kfree(dma->port);
  624. return ret;
  625. }
  626. static void intel_shutdown(struct snd_pcm_substream *substream,
  627. struct snd_soc_dai *dai)
  628. {
  629. struct sdw_cdns_dma_data *dma;
  630. dma = snd_soc_dai_get_dma_data(dai, substream);
  631. if (!dma)
  632. return;
  633. snd_soc_dai_set_dma_data(dai, substream, NULL);
  634. kfree(dma);
  635. }
  636. static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
  637. void *stream, int direction)
  638. {
  639. return cdns_set_sdw_stream(dai, stream, true, direction);
  640. }
  641. static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
  642. void *stream, int direction)
  643. {
  644. return cdns_set_sdw_stream(dai, stream, false, direction);
  645. }
  646. static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
  647. .hw_params = intel_hw_params,
  648. .hw_free = intel_hw_free,
  649. .shutdown = intel_shutdown,
  650. .set_sdw_stream = intel_pcm_set_sdw_stream,
  651. };
  652. static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
  653. .hw_params = intel_hw_params,
  654. .hw_free = intel_hw_free,
  655. .shutdown = intel_shutdown,
  656. .set_sdw_stream = intel_pdm_set_sdw_stream,
  657. };
  658. static const struct snd_soc_component_driver dai_component = {
  659. .name = "soundwire",
  660. };
  661. static int intel_create_dai(struct sdw_cdns *cdns,
  662. struct snd_soc_dai_driver *dais,
  663. enum intel_pdi_type type,
  664. u32 num, u32 off, u32 max_ch, bool pcm)
  665. {
  666. int i;
  667. if (num == 0)
  668. return 0;
  669. /* TODO: Read supported rates/formats from hardware */
  670. for (i = off; i < (off + num); i++) {
  671. dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
  672. cdns->instance, i);
  673. if (!dais[i].name)
  674. return -ENOMEM;
  675. if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
  676. dais[i].playback.stream_name =
  677. kasprintf(GFP_KERNEL, "SDW%d Tx%d",
  678. cdns->instance, i);
  679. if (!dais[i].playback.stream_name) {
  680. kfree(dais[i].name);
  681. return -ENOMEM;
  682. }
  683. dais[i].playback.channels_min = 1;
  684. dais[i].playback.channels_max = max_ch;
  685. dais[i].playback.rates = SNDRV_PCM_RATE_48000;
  686. dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
  687. }
  688. if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
  689. dais[i].capture.stream_name =
  690. kasprintf(GFP_KERNEL, "SDW%d Rx%d",
  691. cdns->instance, i);
  692. if (!dais[i].capture.stream_name) {
  693. kfree(dais[i].name);
  694. kfree(dais[i].playback.stream_name);
  695. return -ENOMEM;
  696. }
  697. dais[i].capture.channels_min = 1;
  698. dais[i].capture.channels_max = max_ch;
  699. dais[i].capture.rates = SNDRV_PCM_RATE_48000;
  700. dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
  701. }
  702. dais[i].id = SDW_DAI_ID_RANGE_START + i;
  703. if (pcm)
  704. dais[i].ops = &intel_pcm_dai_ops;
  705. else
  706. dais[i].ops = &intel_pdm_dai_ops;
  707. }
  708. return 0;
  709. }
  710. static int intel_register_dai(struct sdw_intel *sdw)
  711. {
  712. struct sdw_cdns *cdns = &sdw->cdns;
  713. struct sdw_cdns_streams *stream;
  714. struct snd_soc_dai_driver *dais;
  715. int num_dai, ret, off = 0;
  716. /* DAIs are created based on total number of PDIs supported */
  717. num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
  718. dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
  719. if (!dais)
  720. return -ENOMEM;
  721. /* Create PCM DAIs */
  722. stream = &cdns->pcm;
  723. ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in,
  724. off, stream->num_ch_in, true);
  725. if (ret)
  726. return ret;
  727. off += cdns->pcm.num_in;
  728. ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
  729. off, stream->num_ch_out, true);
  730. if (ret)
  731. return ret;
  732. off += cdns->pcm.num_out;
  733. ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
  734. off, stream->num_ch_bd, true);
  735. if (ret)
  736. return ret;
  737. /* Create PDM DAIs */
  738. stream = &cdns->pdm;
  739. off += cdns->pcm.num_bd;
  740. ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
  741. off, stream->num_ch_in, false);
  742. if (ret)
  743. return ret;
  744. off += cdns->pdm.num_in;
  745. ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
  746. off, stream->num_ch_out, false);
  747. if (ret)
  748. return ret;
  749. off += cdns->pdm.num_bd;
  750. ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
  751. off, stream->num_ch_bd, false);
  752. if (ret)
  753. return ret;
  754. return snd_soc_register_component(cdns->dev, &dai_component,
  755. dais, num_dai);
  756. }
  757. static int sdw_master_read_intel_prop(struct sdw_bus *bus)
  758. {
  759. struct sdw_master_prop *prop = &bus->prop;
  760. struct fwnode_handle *link;
  761. char name[32];
  762. u32 quirk_mask;
  763. /* Find master handle */
  764. snprintf(name, sizeof(name),
  765. "mipi-sdw-link-%d-subproperties", bus->link_id);
  766. link = device_get_named_child_node(bus->dev, name);
  767. if (!link) {
  768. dev_err(bus->dev, "Master node %s not found\n", name);
  769. return -EIO;
  770. }
  771. fwnode_property_read_u32(link,
  772. "intel-sdw-ip-clock",
  773. &prop->mclk_freq);
  774. fwnode_property_read_u32(link,
  775. "intel-quirk-mask",
  776. &quirk_mask);
  777. if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
  778. prop->hw_disabled = true;
  779. return 0;
  780. }
  781. static int intel_prop_read(struct sdw_bus *bus)
  782. {
  783. /* Initialize with default handler to read all DisCo properties */
  784. sdw_master_read_prop(bus);
  785. /* read Intel-specific properties */
  786. sdw_master_read_intel_prop(bus);
  787. return 0;
  788. }
  789. static struct sdw_master_ops sdw_intel_ops = {
  790. .read_prop = sdw_master_read_prop,
  791. .xfer_msg = cdns_xfer_msg,
  792. .xfer_msg_defer = cdns_xfer_msg_defer,
  793. .reset_page_addr = cdns_reset_page_addr,
  794. .set_bus_conf = cdns_bus_conf,
  795. .pre_bank_switch = intel_pre_bank_switch,
  796. .post_bank_switch = intel_post_bank_switch,
  797. };
  798. /*
  799. * probe and init
  800. */
  801. static int intel_probe(struct platform_device *pdev)
  802. {
  803. struct sdw_cdns_stream_config config;
  804. struct sdw_intel *sdw;
  805. int ret;
  806. sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
  807. if (!sdw)
  808. return -ENOMEM;
  809. sdw->instance = pdev->id;
  810. sdw->res = dev_get_platdata(&pdev->dev);
  811. sdw->cdns.dev = &pdev->dev;
  812. sdw->cdns.registers = sdw->res->registers;
  813. sdw->cdns.instance = sdw->instance;
  814. sdw->cdns.msg_count = 0;
  815. sdw->cdns.bus.dev = &pdev->dev;
  816. sdw->cdns.bus.link_id = pdev->id;
  817. sdw_cdns_probe(&sdw->cdns);
  818. /* Set property read ops */
  819. sdw_intel_ops.read_prop = intel_prop_read;
  820. sdw->cdns.bus.ops = &sdw_intel_ops;
  821. platform_set_drvdata(pdev, sdw);
  822. ret = sdw_add_bus_master(&sdw->cdns.bus);
  823. if (ret) {
  824. dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
  825. goto err_master_reg;
  826. }
  827. if (sdw->cdns.bus.prop.hw_disabled) {
  828. dev_info(&pdev->dev, "SoundWire master %d is disabled, ignoring\n",
  829. sdw->cdns.bus.link_id);
  830. return 0;
  831. }
  832. /* Initialize shim and controller */
  833. intel_link_power_up(sdw);
  834. intel_shim_init(sdw);
  835. ret = sdw_cdns_init(&sdw->cdns);
  836. if (ret)
  837. goto err_init;
  838. ret = sdw_cdns_enable_interrupt(&sdw->cdns);
  839. /* Read the PDI config and initialize cadence PDI */
  840. intel_pdi_init(sdw, &config);
  841. ret = sdw_cdns_pdi_init(&sdw->cdns, config);
  842. if (ret)
  843. goto err_init;
  844. intel_pdi_ch_update(sdw);
  845. /* Acquire IRQ */
  846. ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
  847. IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
  848. if (ret < 0) {
  849. dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
  850. sdw->res->irq);
  851. goto err_init;
  852. }
  853. /* Register DAIs */
  854. ret = intel_register_dai(sdw);
  855. if (ret) {
  856. dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
  857. snd_soc_unregister_component(sdw->cdns.dev);
  858. goto err_dai;
  859. }
  860. intel_debugfs_init(sdw);
  861. return 0;
  862. err_dai:
  863. free_irq(sdw->res->irq, sdw);
  864. err_init:
  865. sdw_delete_bus_master(&sdw->cdns.bus);
  866. err_master_reg:
  867. return ret;
  868. }
  869. static int intel_remove(struct platform_device *pdev)
  870. {
  871. struct sdw_intel *sdw;
  872. sdw = platform_get_drvdata(pdev);
  873. if (!sdw->cdns.bus.prop.hw_disabled) {
  874. intel_debugfs_exit(sdw);
  875. free_irq(sdw->res->irq, sdw);
  876. snd_soc_unregister_component(sdw->cdns.dev);
  877. }
  878. sdw_delete_bus_master(&sdw->cdns.bus);
  879. return 0;
  880. }
  881. static struct platform_driver sdw_intel_drv = {
  882. .probe = intel_probe,
  883. .remove = intel_remove,
  884. .driver = {
  885. .name = "int-sdw",
  886. },
  887. };
  888. module_platform_driver(sdw_intel_drv);
  889. MODULE_LICENSE("Dual BSD/GPL");
  890. MODULE_ALIAS("platform:int-sdw");
  891. MODULE_DESCRIPTION("Intel Soundwire Master Driver");