PageRenderTime 22ms CodeModel.GetById 13ms app.highlight 4ms RepoModel.GetById 1ms app.codeStats 1ms

/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0003-omap4-add-OMAP4430-revision-check.patch

http://github.com/OpenELEC/OpenELEC.tv
Patch | 137 lines | 131 code | 6 blank | 0 comment | 0 complexity | ad18743fc2a6af4dab99db104cb8b1a8 MD5 | raw file
  1From 3130b153ed6d6d1e486973a5d782e0480db748d6 Mon Sep 17 00:00:00 2001
  2From: Aneesh V <aneesh@ti.com>
  3Date: Wed, 16 Feb 2011 23:51:21 +0530
  4Subject: [PATCH 03/22] omap4: add OMAP4430 revision check
  5
  6Signed-off-by: Aneesh V <aneesh@ti.com>
  7---
  8 arch/arm/cpu/armv7/omap4/board.c        |   35 +++++++++++++++++++++++++++++++
  9 arch/arm/include/asm/arch-omap4/omap4.h |   17 +++++++++-----
 10 arch/arm/include/asm/armv7.h            |   31 +++++++++++++++++++++++++++
 11 3 files changed, 77 insertions(+), 6 deletions(-)
 12 create mode 100644 arch/arm/include/asm/armv7.h
 13
 14diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
 15index fcd29a7..7583a0d 100644
 16--- a/arch/arm/cpu/armv7/omap4/board.c
 17+++ b/arch/arm/cpu/armv7/omap4/board.c
 18@@ -28,6 +28,7 @@
 19  * MA 02111-1307 USA
 20  */
 21 #include <common.h>
 22+#include <asm/armv7.h>
 23 #include <asm/arch/cpu.h>
 24 #include <asm/arch/sys_proto.h>
 25 #include <asm/sizes.h>
 26@@ -127,3 +128,37 @@ int arch_cpu_init(void)
 27 	set_muxconf_regs();
 28 	return 0;
 29 }
 30+
 31+static u32 cortex_a9_rev(void)
 32+{
 33+
 34+	unsigned int rev;
 35+
 36+	/* Read Main ID Register (MIDR) */
 37+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
 38+
 39+	return rev;
 40+}
 41+
 42+u32 omap4_revision(void)
 43+{
 44+	if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_1)
 45+		return OMAP4430_ES2_1;
 46+	else if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_2)
 47+		return OMAP4430_ES2_2;
 48+	/*
 49+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
 50+	 * Also, ES1 and ES2 have different ARM revisions
 51+	 * So use ARM revision for identification
 52+	 */
 53+	unsigned int rev = cortex_a9_rev();
 54+
 55+	switch (rev) {
 56+	case MIDR_CORTEX_A9_R0P1:
 57+		return OMAP4430_ES1_0;
 58+	case MIDR_CORTEX_A9_R1P2:
 59+		return OMAP4430_ES2_0;
 60+	default:
 61+		return OMAP4430_SILICON_ID_INVALID;
 62+	}
 63+}
 64diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
 65index a30bb33..1f88732 100644
 66--- a/arch/arm/include/asm/arch-omap4/omap4.h
 67+++ b/arch/arm/include/asm/arch-omap4/omap4.h
 68@@ -51,6 +51,11 @@
 69 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 70 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 71 
 72+/* CONTROL_ID_CODE */
 73+#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
 74+
 75+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
 76+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
 77 /* UART */
 78 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 79 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
 80@@ -121,11 +126,11 @@ struct s32ktimer {
 81 /* Temporary SRAM stack used while low level init is done */
 82 #define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
 83 
 84-/*
 85- * OMAP4 real hardware:
 86- * TODO: Change this to the IDCODE in the hw regsiter
 87- */
 88-#define CPU_OMAP4430_ES10	1
 89-#define CPU_OMAP4430_ES20	2
 90+/* Silicon revisions */
 91+#define OMAP4430_SILICON_ID_INVALID	0
 92+#define OMAP4430_ES1_0	1
 93+#define OMAP4430_ES2_0	2
 94+#define OMAP4430_ES2_1	3
 95+#define OMAP4430_ES2_2	4
 96 
 97 #endif
 98diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
 99new file mode 100644
100index 0000000..6c24a80
101--- /dev/null
102+++ b/arch/arm/include/asm/armv7.h
103@@ -0,0 +1,31 @@
104+/*
105+ * (C) Copyright 2010
106+ * Texas Instruments Incorporated - http://www.ti.com/
107+ *
108+ * Aneesh V <aneesh@ti.com>
109+ *
110+ * See file CREDITS for list of people who contributed to this
111+ * project.
112+ *
113+ * This program is free software; you can redistribute it and/or
114+ * modify it under the terms of the GNU General Public License as
115+ * published by the Free Software Foundation; either version 2 of
116+ * the License, or (at your option) any later version.
117+ *
118+ * This program is distributed in the hope that it will be useful,
119+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
120+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
121+ * GNU General Public License for more details.
122+ *
123+ * You should have received a copy of the GNU General Public License
124+ * along with this program; if not, write to the Free Software
125+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
126+ * MA 02111-1307 USA
127+ */
128+#ifndef ARMV7_H
129+#define ARMV7_H
130+
131+#define MIDR_CORTEX_A9_R0P1	0x410FC091
132+#define MIDR_CORTEX_A9_R1P2	0x411FC092
133+
134+#endif /* ARMV7_H */
135-- 
1361.7.2.3
137