/packages/tools/u-boot/patches/u-boot-2011.03-rc1-0003-omap4-add-OMAP4430-revision-check.patch

http://github.com/OpenELEC/OpenELEC.tv · Patch · 137 lines · 131 code · 6 blank · 0 comment · 0 complexity · ad18743fc2a6af4dab99db104cb8b1a8 MD5 · raw file

  1. From 3130b153ed6d6d1e486973a5d782e0480db748d6 Mon Sep 17 00:00:00 2001
  2. From: Aneesh V <aneesh@ti.com>
  3. Date: Wed, 16 Feb 2011 23:51:21 +0530
  4. Subject: [PATCH 03/22] omap4: add OMAP4430 revision check
  5. Signed-off-by: Aneesh V <aneesh@ti.com>
  6. ---
  7. arch/arm/cpu/armv7/omap4/board.c | 35 +++++++++++++++++++++++++++++++
  8. arch/arm/include/asm/arch-omap4/omap4.h | 17 +++++++++-----
  9. arch/arm/include/asm/armv7.h | 31 +++++++++++++++++++++++++++
  10. 3 files changed, 77 insertions(+), 6 deletions(-)
  11. create mode 100644 arch/arm/include/asm/armv7.h
  12. diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
  13. index fcd29a7..7583a0d 100644
  14. --- a/arch/arm/cpu/armv7/omap4/board.c
  15. +++ b/arch/arm/cpu/armv7/omap4/board.c
  16. @@ -28,6 +28,7 @@
  17. * MA 02111-1307 USA
  18. */
  19. #include <common.h>
  20. +#include <asm/armv7.h>
  21. #include <asm/arch/cpu.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/sizes.h>
  24. @@ -127,3 +128,37 @@ int arch_cpu_init(void)
  25. set_muxconf_regs();
  26. return 0;
  27. }
  28. +
  29. +static u32 cortex_a9_rev(void)
  30. +{
  31. +
  32. + unsigned int rev;
  33. +
  34. + /* Read Main ID Register (MIDR) */
  35. + asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
  36. +
  37. + return rev;
  38. +}
  39. +
  40. +u32 omap4_revision(void)
  41. +{
  42. + if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_1)
  43. + return OMAP4430_ES2_1;
  44. + else if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_2)
  45. + return OMAP4430_ES2_2;
  46. + /*
  47. + * For some of the ES2/ES1 boards ID_CODE is not reliable:
  48. + * Also, ES1 and ES2 have different ARM revisions
  49. + * So use ARM revision for identification
  50. + */
  51. + unsigned int rev = cortex_a9_rev();
  52. +
  53. + switch (rev) {
  54. + case MIDR_CORTEX_A9_R0P1:
  55. + return OMAP4430_ES1_0;
  56. + case MIDR_CORTEX_A9_R1P2:
  57. + return OMAP4430_ES2_0;
  58. + default:
  59. + return OMAP4430_SILICON_ID_INVALID;
  60. + }
  61. +}
  62. diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
  63. index a30bb33..1f88732 100644
  64. --- a/arch/arm/include/asm/arch-omap4/omap4.h
  65. +++ b/arch/arm/include/asm/arch-omap4/omap4.h
  66. @@ -51,6 +51,11 @@
  67. #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
  68. #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
  69. +/* CONTROL_ID_CODE */
  70. +#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
  71. +
  72. +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
  73. +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
  74. /* UART */
  75. #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
  76. #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
  77. @@ -121,11 +126,11 @@ struct s32ktimer {
  78. /* Temporary SRAM stack used while low level init is done */
  79. #define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
  80. -/*
  81. - * OMAP4 real hardware:
  82. - * TODO: Change this to the IDCODE in the hw regsiter
  83. - */
  84. -#define CPU_OMAP4430_ES10 1
  85. -#define CPU_OMAP4430_ES20 2
  86. +/* Silicon revisions */
  87. +#define OMAP4430_SILICON_ID_INVALID 0
  88. +#define OMAP4430_ES1_0 1
  89. +#define OMAP4430_ES2_0 2
  90. +#define OMAP4430_ES2_1 3
  91. +#define OMAP4430_ES2_2 4
  92. #endif
  93. diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
  94. new file mode 100644
  95. index 0000000..6c24a80
  96. --- /dev/null
  97. +++ b/arch/arm/include/asm/armv7.h
  98. @@ -0,0 +1,31 @@
  99. +/*
  100. + * (C) Copyright 2010
  101. + * Texas Instruments Incorporated - http://www.ti.com/
  102. + *
  103. + * Aneesh V <aneesh@ti.com>
  104. + *
  105. + * See file CREDITS for list of people who contributed to this
  106. + * project.
  107. + *
  108. + * This program is free software; you can redistribute it and/or
  109. + * modify it under the terms of the GNU General Public License as
  110. + * published by the Free Software Foundation; either version 2 of
  111. + * the License, or (at your option) any later version.
  112. + *
  113. + * This program is distributed in the hope that it will be useful,
  114. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  115. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  116. + * GNU General Public License for more details.
  117. + *
  118. + * You should have received a copy of the GNU General Public License
  119. + * along with this program; if not, write to the Free Software
  120. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  121. + * MA 02111-1307 USA
  122. + */
  123. +#ifndef ARMV7_H
  124. +#define ARMV7_H
  125. +
  126. +#define MIDR_CORTEX_A9_R0P1 0x410FC091
  127. +#define MIDR_CORTEX_A9_R1P2 0x411FC092
  128. +
  129. +#endif /* ARMV7_H */
  130. --
  131. 1.7.2.3