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/sound/soc/codecs/msm8916-wcd-analog.c

https://codeberg.org/ddevault/linux
C | 1262 lines | 1028 code | 187 blank | 47 comment | 56 complexity | f560bb6a1cad0e89b06bcce91409c452 MD5 | raw file
Possible License(s): GPL-2.0 
    

  1. // SPDX-License-Identifier: GPL-2.0
    2. 

  2. // Copyright (c) 2016, The Linux Foundation. All rights reserved.
    3. 

  3. 

  4. #include <linux/module.h>
    5. 

  5. #include <linux/err.h>
    6. 

  6. #include <linux/kernel.h>
    7. 

  7. #include <linux/delay.h>
    8. 

  8. #include <linux/regulator/consumer.h>
    9. 

  9. #include <linux/types.h>
    10. 

  10. #include <linux/clk.h>
    11. 

  11. #include <linux/of.h>
    12. 

  12. #include <linux/platform_device.h>
    13. 

  13. #include <linux/regmap.h>
    14. 

  14. #include <sound/soc.h>
    15. 

  15. #include <sound/pcm.h>
    16. 

  16. #include <sound/pcm_params.h>
    17. 

  17. #include <sound/tlv.h>
    18. 

  18. #include <sound/jack.h>
    19. 

  19. 

  20. #define CDC_D_REVISION1			(0xf000)
    21. 

  21. #define CDC_D_PERPH_SUBTYPE		(0xf005)
    22. 

  22. #define CDC_D_INT_EN_SET		(0x015)
    23. 

  23. #define CDC_D_INT_EN_CLR		(0x016)
    24. 

  24. #define MBHC_SWITCH_INT			BIT(7)
    25. 

  25. #define MBHC_MIC_ELECTRICAL_INS_REM_DET	BIT(6)
    26. 

  26. #define MBHC_BUTTON_PRESS_DET		BIT(5)
    27. 

  27. #define MBHC_BUTTON_RELEASE_DET		BIT(4)
    28. 

  28. #define CDC_D_CDC_RST_CTL		(0xf046)
    29. 

  29. #define RST_CTL_DIG_SW_RST_N_MASK	BIT(7)
    30. 

  30. #define RST_CTL_DIG_SW_RST_N_RESET	0
    31. 

  31. #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
    32. 

  32. 

  33. #define CDC_D_CDC_TOP_CLK_CTL		(0xf048)
    34. 

  34. #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
    35. 

  35. #define TOP_CLK_CTL_A_MCLK_EN_ENABLE	 BIT(2)
    36. 

  36. #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE	BIT(3)
    37. 

  37. 

  38. #define CDC_D_CDC_ANA_CLK_CTL		(0xf049)
    39. 

  39. #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
    40. 

  40. #define ANA_CLK_CTL_EAR_HPHR_CLK_EN	BIT(0)
    41. 

  41. #define ANA_CLK_CTL_EAR_HPHL_CLK_EN	BIT(1)
    42. 

  42. #define ANA_CLK_CTL_SPKR_CLK_EN_MASK	BIT(4)
    43. 

  43. #define ANA_CLK_CTL_SPKR_CLK_EN	BIT(4)
    44. 

  44. #define ANA_CLK_CTL_TXA_CLK25_EN	BIT(5)
    45. 

  45. 

  46. #define CDC_D_CDC_DIG_CLK_CTL		(0xf04A)
    47. 

  47. #define DIG_CLK_CTL_RXD1_CLK_EN		BIT(0)
    48. 

  48. #define DIG_CLK_CTL_RXD2_CLK_EN		BIT(1)
    49. 

  49. #define DIG_CLK_CTL_RXD3_CLK_EN		BIT(2)
    50. 

  50. #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK	BIT(3)
    51. 

  51. #define DIG_CLK_CTL_D_MBHC_CLK_EN	BIT(3)
    52. 

  52. #define DIG_CLK_CTL_TXD_CLK_EN		BIT(4)
    53. 

  53. #define DIG_CLK_CTL_NCP_CLK_EN_MASK	BIT(6)
    54. 

  54. #define DIG_CLK_CTL_NCP_CLK_EN		BIT(6)
    55. 

  55. #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK	BIT(7)
    56. 

  56. #define DIG_CLK_CTL_RXD_PDM_CLK_EN	BIT(7)
    57. 

  57. 

  58. #define CDC_D_CDC_CONN_TX1_CTL		(0xf050)
    59. 

  59. #define CONN_TX1_SERIAL_TX1_MUX		GENMASK(1, 0)
    60. 

  60. #define CONN_TX1_SERIAL_TX1_ADC_1	0x0
    61. 

  61. #define CONN_TX1_SERIAL_TX1_RX_PDM_LB	0x1
    62. 

  62. #define CONN_TX1_SERIAL_TX1_ZERO	0x2
    63. 

  63. 

  64. #define CDC_D_CDC_CONN_TX2_CTL		(0xf051)
    65. 

  65. #define CONN_TX2_SERIAL_TX2_MUX		GENMASK(1, 0)
    66. 

  66. #define CONN_TX2_SERIAL_TX2_ADC_2	0x0
    67. 

  67. #define CONN_TX2_SERIAL_TX2_RX_PDM_LB	0x1
    68. 

  68. #define CONN_TX2_SERIAL_TX2_ZERO	0x2
    69. 

  69. #define CDC_D_CDC_CONN_HPHR_DAC_CTL	(0xf052)
    70. 

  70. #define CDC_D_CDC_CONN_RX1_CTL		(0xf053)
    71. 

  71. #define CDC_D_CDC_CONN_RX2_CTL		(0xf054)
    72. 

  72. #define CDC_D_CDC_CONN_RX3_CTL		(0xf055)
    73. 

  73. #define CDC_D_CDC_CONN_RX_LB_CTL	(0xf056)
    74. 

  74. #define CDC_D_SEC_ACCESS		(0xf0D0)
    75. 

  75. #define CDC_D_PERPH_RESET_CTL3		(0xf0DA)
    76. 

  76. #define CDC_D_PERPH_RESET_CTL4		(0xf0DB)
    77. 

  77. #define CDC_A_REVISION1			(0xf100)
    78. 

  78. #define CDC_A_REVISION2			(0xf101)
    79. 

  79. #define CDC_A_REVISION3			(0xf102)
    80. 

  80. #define CDC_A_REVISION4			(0xf103)
    81. 

  81. #define CDC_A_PERPH_TYPE		(0xf104)
    82. 

  82. #define CDC_A_PERPH_SUBTYPE		(0xf105)
    83. 

  83. #define CDC_A_INT_RT_STS		(0xf110)
    84. 

  84. #define CDC_A_INT_SET_TYPE		(0xf111)
    85. 

  85. #define CDC_A_INT_POLARITY_HIGH		(0xf112)
    86. 

  86. #define CDC_A_INT_POLARITY_LOW		(0xf113)
    87. 

  87. #define CDC_A_INT_LATCHED_CLR		(0xf114)
    88. 

  88. #define CDC_A_INT_EN_SET		(0xf115)
    89. 

  89. #define CDC_A_INT_EN_CLR		(0xf116)
    90. 

  90. #define CDC_A_INT_LATCHED_STS		(0xf118)
    91. 

  91. #define CDC_A_INT_PENDING_STS		(0xf119)
    92. 

  92. #define CDC_A_INT_MID_SEL		(0xf11A)
    93. 

  93. #define CDC_A_INT_PRIORITY		(0xf11B)
    94. 

  94. #define CDC_A_MICB_1_EN			(0xf140)
    95. 

  95. #define MICB_1_EN_MICB_ENABLE		BIT(7)
    96. 

  96. #define MICB_1_EN_BYP_CAP_MASK		BIT(6)
    97. 

  97. #define MICB_1_EN_NO_EXT_BYP_CAP	BIT(6)
    98. 

  98. #define MICB_1_EN_EXT_BYP_CAP		0
    99. 

  99. #define MICB_1_EN_PULL_DOWN_EN_MASK	BIT(5)
    100. 

  100. #define MICB_1_EN_PULL_DOWN_EN_ENABLE	BIT(5)
    101. 

  101. #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
    102. 

  102. #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA	(0x4)
    103. 

  103. #define MICB_1_EN_PULL_UP_EN_MASK	BIT(4)
    104. 

  104. #define MICB_1_EN_TX3_GND_SEL_MASK	BIT(0)
    105. 

  105. #define MICB_1_EN_TX3_GND_SEL_TX_GND	0
    106. 

  106. 

  107. #define CDC_A_MICB_1_VAL		(0xf141)
    108. 

  108. #define MICB_MIN_VAL 1600
    109. 

  109. #define MICB_STEP_SIZE 50
    110. 

  110. #define MICB_VOLTAGE_REGVAL(v)		(((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
    111. 

  111. #define MICB_1_VAL_MICB_OUT_VAL_MASK	GENMASK(7, 3)
    112. 

  112. #define MICB_1_VAL_MICB_OUT_VAL_V2P70V	((0x16)  << 3)
    113. 

  113. #define MICB_1_VAL_MICB_OUT_VAL_V1P80V	((0x4)  << 3)
    114. 

  114. #define CDC_A_MICB_1_CTL		(0xf142)
    115. 

  115. 

  116. #define MICB_1_CTL_CFILT_REF_SEL_MASK		BIT(1)
    117. 

  117. #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF	BIT(1)
    118. 

  118. #define MICB_1_CTL_EXT_PRECHARG_EN_MASK		BIT(5)
    119. 

  119. #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE	BIT(5)
    120. 

  120. #define MICB_1_CTL_INT_PRECHARG_BYP_MASK	BIT(6)
    121. 

  121. #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL	BIT(6)
    122. 

  122. 

  123. #define CDC_A_MICB_1_INT_RBIAS			(0xf143)
    124. 

  124. #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK	BIT(7)
    125. 

  125. #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE	BIT(7)
    126. 

  126. #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE	0
    127. 

  127. 

  128. #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK	BIT(6)
    129. 

  129. #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
    130. 

  130. #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND	0
    131. 

  131. 

  132. #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK	BIT(4)
    133. 

  133. #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE	BIT(4)
    134. 

  134. #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE	0
    135. 

  135. #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK	BIT(3)
    136. 

  136. #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
    137. 

  137. #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND	0
    138. 

  138. 

  139. #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK	BIT(1)
    140. 

  140. #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE	BIT(1)
    141. 

  141. #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE	0
    142. 

  142. #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK	BIT(0)
    143. 

  143. #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
    144. 

  144. #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND	0
    145. 

  145. 

  146. #define CDC_A_MICB_2_EN			(0xf144)
    147. 

  147. #define CDC_A_MICB_2_EN_ENABLE		BIT(7)
    148. 

  148. #define CDC_A_MICB_2_PULL_DOWN_EN_MASK	BIT(5)
    149. 

  149. #define CDC_A_MICB_2_PULL_DOWN_EN	BIT(5)
    150. 

  150. #define CDC_A_TX_1_2_ATEST_CTL_2	(0xf145)
    151. 

  151. #define CDC_A_MASTER_BIAS_CTL		(0xf146)
    152. 

  152. #define CDC_A_MBHC_DET_CTL_1		(0xf147)
    153. 

  153. #define CDC_A_MBHC_DET_CTL_L_DET_EN			BIT(7)
    154. 

  154. #define CDC_A_MBHC_DET_CTL_GND_DET_EN			BIT(6)
    155. 

  155. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION	BIT(5)
    156. 

  156. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL	(0)
    157. 

  157. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK		BIT(5)
    158. 

  158. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT		(5)
    159. 

  159. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO		BIT(4)
    160. 

  160. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL		BIT(3)
    161. 

  161. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK		GENMASK(4, 3)
    162. 

  162. #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN			BIT(2)
    163. 

  163. #define CDC_A_MBHC_DET_CTL_2		(0xf150)
    164. 

  164. #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0	(BIT(7) | BIT(6))
    165. 

  165. #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD	BIT(5)
    166. 

  166. #define CDC_A_PLUG_TYPE_MASK				GENMASK(4, 3)
    167. 

  167. #define CDC_A_HPHL_PLUG_TYPE_NO				BIT(4)
    168. 

  168. #define CDC_A_GND_PLUG_TYPE_NO				BIT(3)
    169. 

  169. #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK	BIT(0)
    170. 

  170. #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN		BIT(0)
    171. 

  171. #define CDC_A_MBHC_FSM_CTL		(0xf151)
    172. 

  172. #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN			BIT(7)
    173. 

  173. #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK		BIT(7)
    174. 

  174. #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA	(0x3 << 4)
    175. 

  175. #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK		GENMASK(6, 4)
    176. 

  176. #define CDC_A_MBHC_DBNC_TIMER		(0xf152)
    177. 

  177. #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS		BIT(3)
    178. 

  178. #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS	(0x9 << 4)
    179. 

  179. #define CDC_A_MBHC_BTN0_ZDET_CTL_0	(0xf153)
    180. 

  180. #define CDC_A_MBHC_BTN1_ZDET_CTL_1	(0xf154)
    181. 

  181. #define CDC_A_MBHC_BTN2_ZDET_CTL_2	(0xf155)
    182. 

  182. #define CDC_A_MBHC_BTN3_CTL		(0xf156)
    183. 

  183. #define CDC_A_MBHC_BTN4_CTL		(0xf157)
    184. 

  184. #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT	(2)
    185. 

  185. #define CDC_A_MBHC_BTN_VREF_FINE_MASK	GENMASK(4, 2)
    186. 

  186. #define CDC_A_MBHC_BTN_VREF_COARSE_MASK	GENMASK(7, 5)
    187. 

  187. #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
    188. 

  188. #define CDC_A_MBHC_BTN_VREF_MASK	(CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
    189. 

  189. 					CDC_A_MBHC_BTN_VREF_FINE_MASK)
    190. 

  190. #define CDC_A_MBHC_RESULT_1		(0xf158)
    191. 

  191. #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK	GENMASK(4, 0)
    192. 

  192. #define CDC_A_TX_1_EN			(0xf160)
    193. 

  193. #define CDC_A_TX_2_EN			(0xf161)
    194. 

  194. #define CDC_A_TX_1_2_TEST_CTL_1		(0xf162)
    195. 

  195. #define CDC_A_TX_1_2_TEST_CTL_2		(0xf163)
    196. 

  196. #define CDC_A_TX_1_2_ATEST_CTL		(0xf164)
    197. 

  197. #define CDC_A_TX_1_2_OPAMP_BIAS		(0xf165)
    198. 

  198. #define CDC_A_TX_3_EN			(0xf167)
    199. 

  199. #define CDC_A_NCP_EN			(0xf180)
    200. 

  200. #define CDC_A_NCP_CLK			(0xf181)
    201. 

  201. #define CDC_A_NCP_FBCTRL		(0xf183)
    202. 

  202. #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK	BIT(5)
    203. 

  203. #define CDC_A_NCP_FBCTRL_FB_CLK_INV		BIT(5)
    204. 

  204. #define CDC_A_NCP_BIAS			(0xf184)
    205. 

  205. #define CDC_A_NCP_VCTRL			(0xf185)
    206. 

  206. #define CDC_A_NCP_TEST			(0xf186)
    207. 

  207. #define CDC_A_NCP_CLIM_ADDR		(0xf187)
    208. 

  208. #define CDC_A_RX_CLOCK_DIVIDER		(0xf190)
    209. 

  209. #define CDC_A_RX_COM_OCP_CTL		(0xf191)
    210. 

  210. #define CDC_A_RX_COM_OCP_COUNT		(0xf192)
    211. 

  211. #define CDC_A_RX_COM_BIAS_DAC		(0xf193)
    212. 

  212. #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK		BIT(7)
    213. 

  213. #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE	BIT(7)
    214. 

  214. #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK		BIT(0)
    215. 

  215. #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE	BIT(0)
    216. 

  216. 

  217. #define CDC_A_RX_HPH_BIAS_PA		(0xf194)
    218. 

  218. #define CDC_A_RX_HPH_BIAS_LDO_OCP	(0xf195)
    219. 

  219. #define CDC_A_RX_HPH_BIAS_CNP		(0xf196)
    220. 

  220. #define CDC_A_RX_HPH_CNP_EN		(0xf197)
    221. 

  221. #define CDC_A_RX_HPH_L_PA_DAC_CTL	(0xf19B)
    222. 

  222. #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK	BIT(1)
    223. 

  223. #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET	BIT(1)
    224. 

  224. #define CDC_A_RX_HPH_R_PA_DAC_CTL	(0xf19D)
    225. 

  225. #define RX_HPH_R_PA_DAC_CTL_DATA_RESET	BIT(1)
    226. 

  226. #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
    227. 

  227. 

  228. #define CDC_A_RX_EAR_CTL			(0xf19E)
    229. 

  229. #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK		BIT(0)
    230. 

  230. #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE	BIT(0)
    231. 

  231. 

  232. #define CDC_A_SPKR_DAC_CTL		(0xf1B0)
    233. 

  233. #define SPKR_DAC_CTL_DAC_RESET_MASK	BIT(4)
    234. 

  234. #define SPKR_DAC_CTL_DAC_RESET_NORMAL	0
    235. 

  235. 

  236. #define CDC_A_SPKR_DRV_CTL		(0xf1B2)
    237. 

  237. #define SPKR_DRV_CTL_DEF_MASK		0xEF
    238. 

  238. #define SPKR_DRV_CLASSD_PA_EN_MASK	BIT(7)
    239. 

  239. #define SPKR_DRV_CLASSD_PA_EN_ENABLE	BIT(7)
    240. 

  240. #define SPKR_DRV_CAL_EN			BIT(6)
    241. 

  241. #define SPKR_DRV_SETTLE_EN		BIT(5)
    242. 

  242. #define SPKR_DRV_FW_EN			BIT(3)
    243. 

  243. #define SPKR_DRV_BOOST_SET		BIT(2)
    244. 

  244. #define SPKR_DRV_CMFB_SET		BIT(1)
    245. 

  245. #define SPKR_DRV_GAIN_SET		BIT(0)
    246. 

  246. #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
    247. 

  247. 		SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
    248. 

  248. 		SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
    249. 

  249. 		SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
    250. 

  250. #define CDC_A_SPKR_OCP_CTL		(0xf1B4)
    251. 

  251. #define CDC_A_SPKR_PWRSTG_CTL		(0xf1B5)
    252. 

  252. #define SPKR_PWRSTG_CTL_DAC_EN_MASK	BIT(0)
    253. 

  253. #define SPKR_PWRSTG_CTL_DAC_EN		BIT(0)
    254. 

  254. #define SPKR_PWRSTG_CTL_MASK		0xE0
    255. 

  255. #define SPKR_PWRSTG_CTL_BBM_MASK	BIT(7)
    256. 

  256. #define SPKR_PWRSTG_CTL_BBM_EN		BIT(7)
    257. 

  257. #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK	BIT(6)
    258. 

  258. #define SPKR_PWRSTG_CTL_HBRDGE_EN	BIT(6)
    259. 

  259. #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK	BIT(5)
    260. 

  260. #define SPKR_PWRSTG_CTL_CLAMP_EN	BIT(5)
    261. 

  261. 

  262. #define CDC_A_SPKR_DRV_DBG		(0xf1B7)
    263. 

  263. #define CDC_A_CURRENT_LIMIT		(0xf1C0)
    264. 

  264. #define CDC_A_BOOST_EN_CTL		(0xf1C3)
    265. 

  265. #define CDC_A_SLOPE_COMP_IP_ZERO	(0xf1C4)
    266. 

  266. #define CDC_A_SEC_ACCESS		(0xf1D0)
    267. 

  267. #define CDC_A_PERPH_RESET_CTL3		(0xf1DA)
    268. 

  268. #define CDC_A_PERPH_RESET_CTL4		(0xf1DB)
    269. 

  269. 

  270. #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
    271. 

  271. 			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
    272. 

  272. #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
    273. 

  273. 				    SNDRV_PCM_FMTBIT_S32_LE)
    274. 

  274. 

  275. static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
    276. 

  276. 	       SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
    277. 

  277. static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
    278. 

  278. 

  279. static const char * const supply_names[] = {
    280. 

  280. 	"vdd-cdc-io",
    281. 

  281. 	"vdd-cdc-tx-rx-cx",
    282. 

  282. };
    283. 

  283. 

  284. #define MBHC_MAX_BUTTONS	(5)
    285. 

  285. 

  286. struct pm8916_wcd_analog_priv {
    287. 

  287. 	u16 pmic_rev;
    288. 

  288. 	u16 codec_version;
    289. 

  289. 	bool	mbhc_btn_enabled;
    290. 

  290. 	/* special event to detect accessory type */
    291. 

  291. 	int	mbhc_btn0_released;
    292. 

  292. 	bool	detect_accessory_type;
    293. 

  293. 	struct clk *mclk;
    294. 

  294. 	struct snd_soc_component *component;
    295. 

  295. 	struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
    296. 

  296. 	struct snd_soc_jack *jack;
    297. 

  297. 	bool hphl_jack_type_normally_open;
    298. 

  298. 	bool gnd_jack_type_normally_open;
    299. 

  299. 	/* Voltage threshold when internal current source of 100uA is used */
    300. 

  300. 	u32 vref_btn_cs[MBHC_MAX_BUTTONS];
    301. 

  301. 	/* Voltage threshold when microphone bias is ON */
    302. 

  302. 	u32 vref_btn_micb[MBHC_MAX_BUTTONS];
    303. 

  303. 	unsigned int micbias1_cap_mode;
    304. 

  304. 	unsigned int micbias2_cap_mode;
    305. 

  305. 	unsigned int micbias_mv;
    306. 

  306. };
    307. 

  307. 

  308. static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
    309. 

  309. static const char *const rdac2_mux_text[] = { "ZERO", "RX2", "RX1" };
    310. 

  310. static const char *const hph_text[] = { "ZERO", "Switch", };
    311. 

  311. 

  312. static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
    313. 

  313. 					ARRAY_SIZE(hph_text), hph_text);
    314. 

  314. 

  315. static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
    316. 

  316. static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
    317. 

  317. 

  318. /* ADC2 MUX */
    319. 

  319. static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
    320. 

  320. 			ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
    321. 

  321. 

  322. /* RDAC2 MUX */
    323. 

  323. static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
    324. 

  324. 			CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 3, rdac2_mux_text);
    325. 

  325. 

  326. static const struct snd_kcontrol_new spkr_switch[] = {
    327. 

  327. 	SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
    328. 

  328. };
    329. 

  329. 

  330. static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
    331. 

  331. 					"RDAC2 MUX Mux", rdac2_mux_enum);
    332. 

  332. static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
    333. 

  333. 					"ADC2 MUX Mux", adc2_enum);
    334. 

  334. 

  335. /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
    336. 

  336. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
    337. 

  337. 

  338. static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
    339. 

  339. 	SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
    340. 

  340. 	SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
    341. 

  341. 	SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
    342. 

  342. };
    343. 

  343. 

  344. static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
    345. 

  345. {
    346. 

  346. 	struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
    347. 

  347. 

  348. 	snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
    349. 

  349. 			    MICB_1_CTL_EXT_PRECHARG_EN_MASK |
    350. 

  350. 			    MICB_1_CTL_INT_PRECHARG_BYP_MASK,
    351. 

  351. 			    MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
    352. 

  352. 			    | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
    353. 

  353. 

  354. 	if (wcd->micbias_mv) {
    355. 

  355. 		snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
    356. 

  356. 				    MICB_1_VAL_MICB_OUT_VAL_MASK,
    357. 

  357. 				    MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
    358. 

  358. 		/*
    359. 

  359. 		 * Special headset needs MICBIAS as 2.7V so wait for
    360. 

  360. 		 * 50 msec for the MICBIAS to reach 2.7 volts.
    361. 

  361. 		 */
    362. 

  362. 		if (wcd->micbias_mv >= 2700)
    363. 

  363. 			msleep(50);
    364. 

  364. 	}
    365. 

  365. 

  366. 	snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
    367. 

  367. 			    MICB_1_CTL_EXT_PRECHARG_EN_MASK |
    368. 

  368. 			    MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
    369. 

  369. 

  370. }
    371. 

  371. 

  372. static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_component
    373. 

  373. 						 *component, int event,
    374. 

  374. 						 int reg, unsigned int cap_mode)
    375. 

  375. {
    376. 

  376. 	switch (event) {
    377. 

  377. 	case SND_SOC_DAPM_POST_PMU:
    378. 

  378. 		pm8916_wcd_analog_micbias_enable(component);
    379. 

  379. 		snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
    380. 

  380. 				    MICB_1_EN_BYP_CAP_MASK, cap_mode);
    381. 

  381. 		break;
    382. 

  382. 	}
    383. 

  383. 

  384. 	return 0;
    385. 

  385. }
    386. 

  386. 

  387. static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_component
    388. 

  388. 						 *component, int event,
    389. 

  389. 						 int reg, u32 cap_mode)
    390. 

  390. {
    391. 

  391. 

  392. 	switch (event) {
    393. 

  393. 	case SND_SOC_DAPM_PRE_PMU:
    394. 

  394. 		snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
    395. 

  395. 				    MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
    396. 

  396. 				    MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
    397. 

  397. 		snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0);
    398. 

  398. 		snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
    399. 

  399. 				    MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
    400. 

  400. 				    MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
    401. 

  401. 

  402. 		break;
    403. 

  403. 	case SND_SOC_DAPM_POST_PMU:
    404. 

  404. 		pm8916_wcd_analog_micbias_enable(component);
    405. 

  405. 		snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
    406. 

  406. 				    MICB_1_EN_BYP_CAP_MASK, cap_mode);
    407. 

  407. 		break;
    408. 

  408. 	}
    409. 

  409. 

  410. 	return 0;
    411. 

  411. }
    412. 

  412. 

  413. static int pm8916_wcd_analog_enable_micbias_ext1(struct
    414. 

  414. 						  snd_soc_dapm_widget
    415. 

  415. 						  *w, struct snd_kcontrol
    416. 

  416. 						  *kcontrol, int event)
    417. 

  417. {
    418. 

  418. 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
    419. 

  419. 	struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
    420. 

  420. 

  421. 	return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg,
    422. 

  422. 						     wcd->micbias1_cap_mode);
    423. 

  423. }
    424. 

  424. 

  425. static int pm8916_wcd_analog_enable_micbias_ext2(struct
    426. 

  426. 						  snd_soc_dapm_widget
    427. 

  427. 						  *w, struct snd_kcontrol
    428. 

  428. 						  *kcontrol, int event)
    429. 

  429. {
    430. 

  430. 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
    431. 

  431. 	struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
    432. 

  432. 

  433. 	return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg,
    434. 

  434. 						     wcd->micbias2_cap_mode);
    435. 

  435. 

  436. }
    437. 

  437. 

  438. static int pm8916_wcd_analog_enable_micbias_int1(struct
    439. 

  439. 						  snd_soc_dapm_widget
    440. 

  440. 						  *w, struct snd_kcontrol
    441. 

  441. 						  *kcontrol, int event)
    442. 

  442. {
    443. 

  443. 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
    444. 

  444. 	struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
    445. 

  445. 

  446. 	return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg,
    447. 

  447. 						     wcd->micbias1_cap_mode);
    448. 

  448. }
    449. 

  449. 

  450. static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
    451. 

  451. 				      bool micbias2_enabled)
    452. 

  452. {
    453. 

  453. 	struct snd_soc_component *component = priv->component;
    454. 

  454. 	u32 coarse, fine, reg_val, reg_addr;
    455. 

  455. 	int *vrefs, i;
    456. 

  456. 

  457. 	if (!micbias2_enabled) { /* use internal 100uA Current source */
    458. 

  458. 		/* Enable internal 2.2k Internal Rbias Resistor */
    459. 

  459. 		snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
    460. 

  460. 				    MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
    461. 

  461. 				    MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
    462. 

  462. 		/* Remove pull down on MIC BIAS2 */
    463. 

  463. 		snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
    464. 

  464. 				   CDC_A_MICB_2_PULL_DOWN_EN_MASK,
    465. 

  465. 				   0);
    466. 

  466. 		/* enable 100uA internal current source */
    467. 

  467. 		snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
    468. 

  468. 				    CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
    469. 

  469. 				    CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
    470. 

  470. 	}
    471. 

  471. 	snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
    472. 

  472. 			CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
    473. 

  473. 			CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
    474. 

  474. 

  475. 	if (micbias2_enabled)
    476. 

  476. 		vrefs = &priv->vref_btn_micb[0];
    477. 

  477. 	else
    478. 

  478. 		vrefs = &priv->vref_btn_cs[0];
    479. 

  479. 

  480. 	/* program vref ranges for all the buttons */
    481. 

  481. 	reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
    482. 

  482. 	for (i = 0; i <  MBHC_MAX_BUTTONS; i++) {
    483. 

  483. 		/* split mv in to coarse parts of 100mv & fine parts of 12mv */
    484. 

  484. 		coarse = (vrefs[i] / 100);
    485. 

  485. 		fine = ((vrefs[i] % 100) / 12);
    486. 

  486. 		reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
    487. 

  487. 			 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
    488. 

  488. 		snd_soc_component_update_bits(component, reg_addr,
    489. 

  489. 			       CDC_A_MBHC_BTN_VREF_MASK,
    490. 

  490. 			       reg_val);
    491. 

  491. 		reg_addr++;
    492. 

  492. 	}
    493. 

  493. 

  494. 	return 0;
    495. 

  495. }
    496. 

  496. 

  497. static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
    498. 

  498. {
    499. 

  499. 	struct snd_soc_component *component = wcd->component;
    500. 

  500. 	bool micbias_enabled = false;
    501. 

  501. 	u32 plug_type = 0;
    502. 

  502. 	u32 int_en_mask;
    503. 

  503. 

  504. 	snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
    505. 

  505. 		      CDC_A_MBHC_DET_CTL_L_DET_EN |
    506. 

  506. 		      CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
    507. 

  507. 		      CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
    508. 

  508. 		      CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
    509. 

  509. 

  510. 	if (wcd->hphl_jack_type_normally_open)
    511. 

  511. 		plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
    512. 

  512. 

  513. 	if (wcd->gnd_jack_type_normally_open)
    514. 

  514. 		plug_type |= CDC_A_GND_PLUG_TYPE_NO;
    515. 

  515. 

  516. 	snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
    517. 

  517. 		      CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
    518. 

  518. 		      CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
    519. 

  519. 		      plug_type |
    520. 

  520. 		      CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
    521. 

  521. 

  522. 

  523. 	snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
    524. 

  524. 		      CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
    525. 

  525. 		      CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
    526. 

  526. 

  527. 	/* enable MBHC clock */
    528. 

  528. 	snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
    529. 

  529. 			    DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
    530. 

  530. 			    DIG_CLK_CTL_D_MBHC_CLK_EN);
    531. 

  531. 

  532. 	if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
    533. 

  533. 		micbias_enabled = true;
    534. 

  534. 

  535. 	pm8916_mbhc_configure_bias(wcd, micbias_enabled);
    536. 

  536. 

  537. 	int_en_mask = MBHC_SWITCH_INT;
    538. 

  538. 	if (wcd->mbhc_btn_enabled)
    539. 

  539. 		int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
    540. 

  540. 

  541. 	snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
    542. 

  542. 	snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
    543. 

  543. 	wcd->mbhc_btn0_released = false;
    544. 

  544. 	wcd->detect_accessory_type = true;
    545. 

  545. }
    546. 

  546. 

  547. static int pm8916_wcd_analog_enable_micbias_int2(struct
    548. 

  548. 						  snd_soc_dapm_widget
    549. 

  549. 						  *w, struct snd_kcontrol
    550. 

  550. 						  *kcontrol, int event)
    551. 

  551. {
    552. 

  552. 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
    553. 

  553. 	struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
    554. 

  554. 

  555. 	switch (event) {
    556. 

  556. 	case SND_SOC_DAPM_POST_PMU:
    557. 

  557. 		pm8916_mbhc_configure_bias(wcd, true);
    558. 

  558. 		break;
    559. 

  559. 	case SND_SOC_DAPM_POST_PMD:
    560. 

  560. 		pm8916_mbhc_configure_bias(wcd, false);
    561. 

  561. 		break;
    562. 

  562. 	}
    563. 

  563. 

  564. 	return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg,
    565. 

  565. 						     wcd->micbias2_cap_mode);
    566. 

  566. }
    567. 

  567. 

  568. static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
    569. 

  569. 					 struct snd_kcontrol *kcontrol,
    570. 

  570. 					 int event)
    571. 

  571. {
    572. 

  572. 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
    573. 

  573. 	u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
    574. 

  574. 	u8 init_bit_shift;
    575. 

  575. 

  576. 	if (w->reg == CDC_A_TX_1_EN)
    577. 

  577. 		init_bit_shift = 5;
    578. 

  578. 	else
    579. 

  579. 		init_bit_shift = 4;
    580. 

  580. 

  581. 	switch (event) {
    582. 

  582. 	case SND_SOC_DAPM_PRE_PMU:
    583. 

  583. 		if (w->reg == CDC_A_TX_2_EN)
    584. 

  584. 			snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
    585. 

  585. 					    MICB_1_CTL_CFILT_REF_SEL_MASK,
    586. 

  586. 					    MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
    587. 

  587. 		/*
    588. 

  588. 		 * Add delay of 10 ms to give sufficient time for the voltage
    589. 

  589. 		 * to shoot up and settle so that the txfe init does not
    590. 

  590. 		 * happen when the input voltage is changing too much.
    591. 

  591. 		 */
    592. 

  592. 		usleep_range(10000, 10010);
    593. 

  593. 		snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
    594. 

  594. 				    1 << init_bit_shift);
    595. 

  595. 		switch (w->reg) {
    596. 

  596. 		case CDC_A_TX_1_EN:
    597. 

  597. 			snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
    598. 

  598. 					    CONN_TX1_SERIAL_TX1_MUX,
    599. 

  599. 					    CONN_TX1_SERIAL_TX1_ADC_1);
    600. 

  600. 			break;
    601. 

  601. 		case CDC_A_TX_2_EN:
    602. 

  602. 		case CDC_A_TX_3_EN:
    603. 

  603. 			snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
    604. 

  604. 					    CONN_TX2_SERIAL_TX2_MUX,
    605. 

  605. 					    CONN_TX2_SERIAL_TX2_ADC_2);
    606. 

  606. 			break;
    607. 

  607. 		}
    608. 

  608. 		break;
    609. 

  609. 	case SND_SOC_DAPM_POST_PMU:
    610. 

  610. 		/*
    611. 

  611. 		 * Add delay of 12 ms before deasserting the init
    612. 

  612. 		 * to reduce the tx pop
    613. 

  613. 		 */
    614. 

  614. 		usleep_range(12000, 12010);
    615. 

  615. 		snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
    616. 

  616. 		break;
    617. 

  617. 	case SND_SOC_DAPM_POST_PMD:
    618. 

  618. 		switch (w->reg) {
    619. 

  619. 		case CDC_A_TX_1_EN:
    620. 

  620. 			snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
    621. 

  621. 					    CONN_TX1_SERIAL_TX1_MUX,
    622. 

  622. 					    CONN_TX1_SERIAL_TX1_ZERO);
    623. 

  623. 			break;
    624. 

  624. 		case CDC_A_TX_2_EN:
    625. 

  625. 			snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
    626. 

  626. 					    MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
    627. 

  627. 			/* fall through */
    628. 

  628. 		case CDC_A_TX_3_EN:
    629. 

  629. 			snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
    630. 

  630. 					    CONN_TX2_SERIAL_TX2_MUX,
    631. 

  631. 					    CONN_TX2_SERIAL_TX2_ZERO);
    632. 

  632. 			break;
    633. 

  633. 		}
    634. 

  634. 

  635. 

  636. 		break;
    637. 

  637. 	}
    638. 

  638. 	return 0;
    639. 

  639. }
    640. 

  640. 

  641. static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
    642. 

  642. 					    struct snd_kcontrol *kcontrol,
    643. 

  643. 					    int event)
    644. 

  644. {
    645. 

  645. 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
    646. 

  646. 

  647. 	switch (event) {
    648. 

  648. 	case SND_SOC_DAPM_PRE_PMU:
    649. 

  649. 		snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
    650. 

  650. 				    SPKR_PWRSTG_CTL_DAC_EN_MASK |
    651. 

  651. 				    SPKR_PWRSTG_CTL_BBM_MASK |
    652. 

  652. 				    SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
    653. 

  653. 				    SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
    654. 

  654. 				    SPKR_PWRSTG_CTL_DAC_EN|
    655. 

  655. 				    SPKR_PWRSTG_CTL_BBM_EN |
    656. 

  656. 				    SPKR_PWRSTG_CTL_HBRDGE_EN |
    657. 

  657. 				    SPKR_PWRSTG_CTL_CLAMP_EN);
    658. 

  658. 

  659. 		snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
    660. 

  660. 				    RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
    661. 

  661. 				    RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
    662. 

  662. 		break;
    663. 

  663. 	case SND_SOC_DAPM_POST_PMU:
    664. 

  664. 		snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
    665. 

  665. 				    SPKR_DRV_CTL_DEF_MASK,
    666. 

  666. 				    SPKR_DRV_CTL_DEF_VAL);
    667. 

  667. 		snd_soc_component_update_bits(component, w->reg,
    668. 

  668. 				    SPKR_DRV_CLASSD_PA_EN_MASK,
    669. 

  669. 				    SPKR_DRV_CLASSD_PA_EN_ENABLE);
    670. 

  670. 		break;
    671. 

  671. 	case SND_SOC_DAPM_POST_PMD:
    672. 

  672. 		snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
    673. 

  673. 				    SPKR_PWRSTG_CTL_DAC_EN_MASK|
    674. 

  674. 				    SPKR_PWRSTG_CTL_BBM_MASK |
    675. 

  675. 				    SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
    676. 

  676. 				    SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
    677. 

  677. 

  678. 		snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
    679. 

  679. 				    SPKR_DAC_CTL_DAC_RESET_MASK,
    680. 

  680. 				    SPKR_DAC_CTL_DAC_RESET_NORMAL);
    681. 

  681. 		snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
    682. 

  682. 				    RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
    683. 

  683. 		break;
    684. 

  684. 	}
    685. 

  685. 	return 0;
    686. 

  686. }
    687. 

  687. 

  688. static const struct reg_default wcd_reg_defaults_2_0[] = {
    689. 

  689. 	{CDC_A_RX_COM_OCP_CTL, 0xD1},
    690. 

  690. 	{CDC_A_RX_COM_OCP_COUNT, 0xFF},
    691. 

  691. 	{CDC_D_SEC_ACCESS, 0xA5},
    692. 

  692. 	{CDC_D_PERPH_RESET_CTL3, 0x0F},
    693. 

  693. 	{CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
    694. 

  694. 	{CDC_A_NCP_FBCTRL, 0x28},
    695. 

  695. 	{CDC_A_SPKR_DRV_CTL, 0x69},
    696. 

  696. 	{CDC_A_SPKR_DRV_DBG, 0x01},
    697. 

  697. 	{CDC_A_BOOST_EN_CTL, 0x5F},
    698. 

  698. 	{CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
    699. 

  699. 	{CDC_A_SEC_ACCESS, 0xA5},
    700. 

  700. 	{CDC_A_PERPH_RESET_CTL3, 0x0F},
    701. 

  701. 	{CDC_A_CURRENT_LIMIT, 0x82},
    702. 

  702. 	{CDC_A_SPKR_DAC_CTL, 0x03},
    703. 

  703. 	{CDC_A_SPKR_OCP_CTL, 0xE1},
    704. 

  704. 	{CDC_A_MASTER_BIAS_CTL, 0x30},
    705. 

  705. };
    706. 

  706. 

  707. static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
    708. 

  708. {
    709. 

  709. 	struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
    710. 

  710. 	int err, reg;
    711. 

  711. 

  712. 	err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
    713. 

  713. 	if (err != 0) {
    714. 

  714. 		dev_err(component->dev, "failed to enable regulators (%d)\n", err);
    715. 

  715. 		return err;
    716. 

  716. 	}
    717. 

  717. 

  718. 	snd_soc_component_init_regmap(component,
    719. 

  719. 				  dev_get_regmap(component->dev->parent, NULL));
    720. 

  720. 	snd_soc_component_set_drvdata(component, priv);
    721. 

  721. 	priv->pmic_rev = snd_soc_component_read32(component, CDC_D_REVISION1);
    722. 

  722. 	priv->codec_version = snd_soc_component_read32(component, CDC_D_PERPH_SUBTYPE);
    723. 

  723. 

  724. 	dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
    725. 

  725. 		 priv->pmic_rev, priv->codec_version);
    726. 

  726. 

  727. 	snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
    728. 

  728. 	snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
    729. 

  729. 

  730. 	for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
    731. 

  731. 		snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
    732. 

  732. 			      wcd_reg_defaults_2_0[reg].def);
    733. 

  733. 

  734. 	priv->component = component;
    735. 

  735. 

  736. 	snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
    737. 

  737. 			    RST_CTL_DIG_SW_RST_N_MASK,
    738. 

  738. 			    RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
    739. 

  739. 

  740. 	pm8916_wcd_setup_mbhc(priv);
    741. 

  741. 

  742. 	return 0;
    743. 

  743. }
    744. 

  744. 

  745. static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
    746. 

  746. {
    747. 

  747. 	struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
    748. 

  748. 

  749. 	snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
    750. 

  750. 			    RST_CTL_DIG_SW_RST_N_MASK, 0);
    751. 

  751. 

  752. 	regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
    753. 

  753. 				      priv->supplies);
    754. 

  754. }
    755. 

  755. 

  756. static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
    757. 

  757. 

  758. 	{"PDM_RX1", NULL, "PDM Playback"},
    759. 

  759. 	{"PDM_RX2", NULL, "PDM Playback"},
    760. 

  760. 	{"PDM_RX3", NULL, "PDM Playback"},
    761. 

  761. 	{"PDM Capture", NULL, "PDM_TX"},
    762. 

  762. 

  763. 	/* ADC Connections */
    764. 

  764. 	{"PDM_TX", NULL, "ADC2"},
    765. 

  765. 	{"PDM_TX", NULL, "ADC3"},
    766. 

  766. 	{"ADC2", NULL, "ADC2 MUX"},
    767. 

  767. 	{"ADC3", NULL, "ADC2 MUX"},
    768. 

  768. 	{"ADC2 MUX", "INP2", "ADC2_INP2"},
    769. 

  769. 	{"ADC2 MUX", "INP3", "ADC2_INP3"},
    770. 

  770. 

  771. 	{"PDM_TX", NULL, "ADC1"},
    772. 

  772. 	{"ADC1", NULL, "AMIC1"},
    773. 

  773. 	{"ADC2_INP2", NULL, "AMIC2"},
    774. 

  774. 	{"ADC2_INP3", NULL, "AMIC3"},
    775. 

  775. 

  776. 	/* RDAC Connections */
    777. 

  777. 	{"HPHR DAC", NULL, "RDAC2 MUX"},
    778. 

  778. 	{"RDAC2 MUX", "RX1", "PDM_RX1"},
    779. 

  779. 	{"RDAC2 MUX", "RX2", "PDM_RX2"},
    780. 

  780. 	{"HPHL DAC", NULL, "PDM_RX1"},
    781. 

  781. 	{"PDM_RX1", NULL, "RXD1_CLK"},
    782. 

  782. 	{"PDM_RX2", NULL, "RXD2_CLK"},
    783. 

  783. 	{"PDM_RX3", NULL, "RXD3_CLK"},
    784. 

  784. 

  785. 	{"PDM_RX1", NULL, "RXD_PDM_CLK"},
    786. 

  786. 	{"PDM_RX2", NULL, "RXD_PDM_CLK"},
    787. 

  787. 	{"PDM_RX3", NULL, "RXD_PDM_CLK"},
    788. 

  788. 

  789. 	{"ADC1", NULL, "TXD_CLK"},
    790. 

  790. 	{"ADC2", NULL, "TXD_CLK"},
    791. 

  791. 	{"ADC3", NULL, "TXD_CLK"},
    792. 

  792. 

  793. 	{"ADC1", NULL, "TXA_CLK25"},
    794. 

  794. 	{"ADC2", NULL, "TXA_CLK25"},
    795. 

  795. 	{"ADC3", NULL, "TXA_CLK25"},
    796. 

  796. 

  797. 	{"PDM_RX1", NULL, "A_MCLK2"},
    798. 

  798. 	{"PDM_RX2", NULL, "A_MCLK2"},
    799. 

  799. 	{"PDM_RX3", NULL, "A_MCLK2"},
    800. 

  800. 

  801. 	{"PDM_TX", NULL, "A_MCLK2"},
    802. 

  802. 	{"A_MCLK2", NULL, "A_MCLK"},
    803. 

  803. 

  804. 	/* Headset (RX MIX1 and RX MIX2) */
    805. 

  805. 	{"HEADPHONE", NULL, "HPHL PA"},
    806. 

  806. 	{"HEADPHONE", NULL, "HPHR PA"},
    807. 

  807. 

  808. 	{"HPHL PA", NULL, "EAR_HPHL_CLK"},
    809. 

  809. 	{"HPHR PA", NULL, "EAR_HPHR_CLK"},
    810. 

  810. 

  811. 	{"CP", NULL, "NCP_CLK"},
    812. 

  812. 

  813. 	{"HPHL PA", NULL, "HPHL"},
    814. 

  814. 	{"HPHR PA", NULL, "HPHR"},
    815. 

  815. 	{"HPHL PA", NULL, "CP"},
    816. 

  816. 	{"HPHL PA", NULL, "RX_BIAS"},
    817. 

  817. 	{"HPHR PA", NULL, "CP"},
    818. 

  818. 	{"HPHR PA", NULL, "RX_BIAS"},
    819. 

  819. 	{"HPHL", "Switch", "HPHL DAC"},
    820. 

  820. 	{"HPHR", "Switch", "HPHR DAC"},
    821. 

  821. 

  822. 	{"RX_BIAS", NULL, "DAC_REF"},
    823. 

  823. 

  824. 	{"SPK_OUT", NULL, "SPK PA"},
    825. 

  825. 	{"SPK PA", NULL, "RX_BIAS"},
    826. 

  826. 	{"SPK PA", NULL, "SPKR_CLK"},
    827. 

  827. 	{"SPK PA", NULL, "SPK DAC"},
    828. 

  828. 	{"SPK DAC", "Switch", "PDM_RX3"},
    829. 

  829. 

  830. 	{"MIC BIAS Internal1", NULL, "INT_LDO_H"},
    831. 

  831. 	{"MIC BIAS Internal2", NULL, "INT_LDO_H"},
    832. 

  832. 	{"MIC BIAS External1", NULL, "INT_LDO_H"},
    833. 

  833. 	{"MIC BIAS External2", NULL, "INT_LDO_H"},
    834. 

  834. 	{"MIC BIAS Internal1", NULL, "vdd-micbias"},
    835. 

  835. 	{"MIC BIAS Internal2", NULL, "vdd-micbias"},
    836. 

  836. 	{"MIC BIAS External1", NULL, "vdd-micbias"},
    837. 

  837. 	{"MIC BIAS External2", NULL, "vdd-micbias"},
    838. 

  838. };
    839. 

  839. 

  840. static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
    841. 

  841. 

  842. 	SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
    843. 

  843. 	SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
    844. 

  844. 	SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
    845. 

  845. 	SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
    846. 

  846. 

  847. 	SND_SOC_DAPM_INPUT("AMIC1"),
    848. 

  848. 	SND_SOC_DAPM_INPUT("AMIC3"),
    849. 

  849. 	SND_SOC_DAPM_INPUT("AMIC2"),
    850. 

  850. 	SND_SOC_DAPM_OUTPUT("HEADPHONE"),
    851. 

  851. 

  852. 	/* RX stuff */
    853. 

  853. 	SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
    854. 

  854. 

  855. 	SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
    856. 

  856. 	SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
    857. 

  857. 	SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
    858. 

  858. 			   0),
    859. 

  859. 	SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
    860. 

  860. 	SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
    861. 

  861. 	SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
    862. 

  862. 			   0),
    863. 

  863. 	SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
    864. 

  864. 			   spkr_switch, ARRAY_SIZE(spkr_switch)),
    865. 

  865. 

  866. 	/* Speaker */
    867. 

  867. 	SND_SOC_DAPM_OUTPUT("SPK_OUT"),
    868. 

  868. 	SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
    869. 

  869. 			   6, 0, NULL, 0,
    870. 

  870. 			   pm8916_wcd_analog_enable_spk_pa,
    871. 

  871. 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
    872. 

  872. 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
    873. 

  873. 	SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
    874. 

  874. 	SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
    875. 

  875. 

  876. 	SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
    877. 

  877. 	SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
    878. 

  878. 

  879. 	/* TX */
    880. 

  880. 	SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0,
    881. 

  881. 			    pm8916_wcd_analog_enable_micbias_int1,
    882. 

  882. 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
    883. 

  883. 			    SND_SOC_DAPM_POST_PMD),
    884. 

  884. 	SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0,
    885. 

  885. 			    pm8916_wcd_analog_enable_micbias_int2,
    886. 

  886. 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
    887. 

  887. 			    SND_SOC_DAPM_POST_PMD),
    888. 

  888. 

  889. 	SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0,
    890. 

  890. 			    pm8916_wcd_analog_enable_micbias_ext1,
    891. 

  891. 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
    892. 

  892. 	SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0,
    893. 

  893. 			    pm8916_wcd_analog_enable_micbias_ext2,
    894. 

  894. 			    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
    895. 

  895. 

  896. 	SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
    897. 

  897. 			   pm8916_wcd_analog_enable_adc,
    898. 

  898. 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
    899. 

  899. 			   SND_SOC_DAPM_POST_PMD),
    900. 

  900. 	SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
    901. 

  901. 			   pm8916_wcd_analog_enable_adc,
    902. 

  902. 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
    903. 

  903. 			   SND_SOC_DAPM_POST_PMD),
    904. 

  904. 	SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
    905. 

  905. 			   pm8916_wcd_analog_enable_adc,
    906. 

  906. 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
    907. 

  907. 			   SND_SOC_DAPM_POST_PMD),
    908. 

  908. 

  909. 	SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
    910. 

  910. 	SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
    911. 

  911. 

  912. 	SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
    913. 

  913. 	SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
    914. 

  914. 

  915. 	/* Analog path clocks */
    916. 

  916. 	SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
    917. 

  917. 			    0),
    918. 

  918. 	SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
    919. 

  919. 			    0),
    920. 

  920. 	SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
    921. 

  921. 	SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
    922. 

  922. 

  923. 	/* Digital path clocks */
    924. 

  924. 

  925. 	SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
    926. 

  926. 	SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
    927. 

  927. 	SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
    928. 

  928. 

  929. 	SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
    930. 

  930. 	SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
    931. 

  931. 	SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
    932. 

  932. 			    0),
    933. 

  933. 

  934. 	/* System Clock source */
    935. 

  935. 	SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
    936. 

  936. 	/* TX ADC and RX DAC Clock source. */
    937. 

  937. 	SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
    938. 

  938. };
    939. 

  939. 

  940. static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
    941. 

  941. 				      struct snd_soc_jack *jack,
    942. 

  942. 				      void *data)
    943. 

  943. {
    944. 

  944. 	struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
    945. 

  945. 

  946. 	wcd->jack = jack;
    947. 

  947. 

  948. 	return 0;
    949. 

  949. }
    950. 

  950. 

  951. static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
    952. 

  952. {
    953. 

  953. 	struct pm8916_wcd_analog_priv *priv = arg;
    954. 

  954. 

  955. 	if (priv->detect_accessory_type) {
    956. 

  956. 		struct snd_soc_component *component = priv->component;
    957. 

  957. 		u32 val = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1);
    958. 

  958. 

  959. 		/* check if its BTN0 thats released */
    960. 

  960. 		if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
    961. 

  961. 			priv->mbhc_btn0_released = true;
    962. 

  962. 

  963. 	} else {
    964. 

  964. 		snd_soc_jack_report(priv->jack, 0, btn_mask);
    965. 

  965. 	}
    966. 

  966. 

  967. 	return IRQ_HANDLED;
    968. 

  968. }
    969. 

  969. 

  970. static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
    971. 

  971. {
    972. 

  972. 	struct pm8916_wcd_analog_priv *priv = arg;
    973. 

  973. 	struct snd_soc_component *component = priv->component;
    974. 

  974. 	u32 btn_result;
    975. 

  975. 

  976. 	btn_result = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1) &
    977. 

  977. 				  CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
    978. 

  978. 

  979. 	switch (btn_result) {
    980. 

  980. 	case 0xf:
    981. 

  981. 		snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
    982. 

  982. 		break;
    983. 

  983. 	case 0x7:
    984. 

  984. 		snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
    985. 

  985. 		break;
    986. 

  986. 	case 0x3:
    987. 

  987. 		snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
    988. 

  988. 		break;
    989. 

  989. 	case 0x1:
    990. 

  990. 		snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
    991. 

  991. 		break;
    992. 

  992. 	case 0x0:
    993. 

  993. 		/* handle BTN_0 specially for type detection */
    994. 

  994. 		if (!priv->detect_accessory_type)
    995. 

  995. 			snd_soc_jack_report(priv->jack,
    996. 

  996. 					    SND_JACK_BTN_0, btn_mask);
    997. 

  997. 		break;
    998. 

  998. 	default:
    999. 

  999. 		dev_err(component->dev,
    1000. 

  1000. 			"Unexpected button press result (%x)", btn_result);
    1001. 

  1001. 		break;
    1002. 

  1002. 	}
    1003. 

  1003. 

  1004. 	return IRQ_HANDLED;
    1005. 

  1005. }
    1006. 

  1006. 

  1007. static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
    1008. 

  1008. {
    1009. 

  1009. 	struct pm8916_wcd_analog_priv *priv = arg;
    1010. 

  1010. 	struct snd_soc_component *component = priv->component;
    1011. 

  1011. 	bool ins = false;
    1012. 

  1012. 

  1013. 	if (snd_soc_component_read32(component, CDC_A_MBHC_DET_CTL_1) &
    1014. 

  1014. 				CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
    1015. 

  1015. 		ins = true;
    1016. 

  1016. 

  1017. 	/* Set the detection type appropriately */
    1018. 

  1018. 	snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
    1019. 

  1019. 			    CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
    1020. 

  1020. 			    (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
    1021. 

  1021. 

  1022. 

  1023. 	if (ins) { /* hs insertion */
    1024. 

  1024. 		bool micbias_enabled = false;
    1025. 

  1025. 

  1026. 		if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) &
    1027. 

  1027. 				CDC_A_MICB_2_EN_ENABLE)
    1028. 

  1028. 			micbias_enabled = true;
    1029. 

  1029. 

  1030. 		pm8916_mbhc_configure_bias(priv, micbias_enabled);
    1031. 

  1031. 

  1032. 		/*
    1033. 

  1033. 		 * if only a btn0 press event is receive just before
    1034. 

  1034. 		 * insert event then its a 3 pole headphone else if
    1035. 

  1035. 		 * both press and release event received then its
    1036. 

  1036. 		 * a headset.
    1037. 

  1037. 		 */
    1038. 

  1038. 		if (priv->mbhc_btn0_released)
    1039. 

  1039. 			snd_soc_jack_report(priv->jack,
    1040. 

  1040. 					    SND_JACK_HEADSET, hs_jack_mask);
    1041. 

  1041. 		else
    1042. 

  1042. 			snd_soc_jack_report(priv->jack,
    1043. 

  1043. 					    SND_JACK_HEADPHONE, hs_jack_mask);
    1044. 

  1044. 

  1045. 		priv->detect_accessory_type = false;
    1046. 

  1046. 

  1047. 	} else { /* removal */
    1048. 

  1048. 		snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
    1049. 

  1049. 		priv->detect_accessory_type = true;
    1050. 

  1050. 		priv->mbhc_btn0_released = false;
    1051. 

  1051. 	}
    1052. 

  1052. 

  1053. 	return IRQ_HANDLED;
    1054. 

  1054. }
    1055. 

  1055. 

  1056. static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
    1057. 

  1057. 	[0] = {
    1058. 

  1058. 	       .name = "pm8916_wcd_analog_pdm_rx",
    1059. 

  1059. 	       .id = 0,
    1060. 

  1060. 	       .playback = {
    1061. 

  1061. 			    .stream_name = "PDM Playback",
    1062. 

  1062. 			    .rates = MSM8916_WCD_ANALOG_RATES,
    1063. 

  1063. 			    .formats = MSM8916_WCD_ANALOG_FORMATS,
    1064. 

  1064. 			    .channels_min = 1,
    1065. 

  1065. 			    .channels_max = 3,
    1066. 

  1066. 			    },
    1067. 

  1067. 	       },
    1068. 

  1068. 	[1] = {
    1069. 

  1069. 	       .name = "pm8916_wcd_analog_pdm_tx",
    1070. 

  1070. 	       .id = 1,
    1071. 

  1071. 	       .capture = {
    1072. 

  1072. 			   .stream_name = "PDM Capture",
    1073. 

  1073. 			   .rates = MSM8916_WCD_ANALOG_RATES,
    1074. 

  1074. 			   .formats = MSM8916_WCD_ANALOG_FORMATS,
    1075. 

  1075. 			   .channels_min = 1,
    1076. 

  1076. 			   .channels_max = 4,
    1077. 

  1077. 			   },
    1078. 

  1078. 	       },
    1079. 

  1079. };
    1080. 

  1080. 

  1081. static const struct snd_soc_component_driver pm8916_wcd_analog = {
    1082. 

  1082. 	.probe			= pm8916_wcd_analog_probe,
    1083. 

  1083. 	.remove			= pm8916_wcd_analog_remove,
    1084. 

  1084. 	.set_jack		= pm8916_wcd_analog_set_jack,
    1085. 

  1085. 	.controls		= pm8916_wcd_analog_snd_controls,
    1086. 

  1086. 	.num_controls		= ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
    1087. 

  1087. 	.dapm_widgets		= pm8916_wcd_analog_dapm_widgets,
    1088. 

  1088. 	.num_dapm_widgets	= ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
    1089. 

  1089. 	.dapm_routes		= pm8916_wcd_analog_audio_map,
    1090. 

  1090. 	.num_dapm_routes	= ARRAY_SIZE(pm8916_wcd_analog_audio_map),
    1091. 

  1091. 	.idle_bias_on		= 1,
    1092. 

  1092. 	.use_pmdown_time	= 1,
    1093. 

  1093. 	.endianness		= 1,
    1094. 

  1094. 	.non_legacy_dai_naming	= 1,
    1095. 

  1095. };
    1096. 

  1096. 

  1097. static int pm8916_wcd_analog_parse_dt(struct device *dev,
    1098. 

  1098. 				       struct pm8916_wcd_analog_priv *priv)
    1099. 

  1099. {
    1100. 

  1100. 	int rval;
    1101. 

  1101. 

  1102. 	if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
    1103. 

  1103. 		priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
    1104. 

  1104. 	else
    1105. 

  1105. 		priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
    1106. 

  1106. 

  1107. 	if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
    1108. 

  1108. 		priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
    1109. 

  1109. 	else
    1110. 

  1110. 		priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
    1111. 

  1111. 

  1112. 	of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
    1113. 

  1113. 			     &priv->micbias_mv);
    1114. 

  1114. 

  1115. 	if (of_property_read_bool(dev->of_node,
    1116. 

  1116. 				  "qcom,hphl-jack-type-normally-open"))
    1117. 

  1117. 		priv->hphl_jack_type_normally_open = true;
    1118. 

  1118. 	else
    1119. 

  1119. 		priv->hphl_jack_type_normally_open = false;
    1120. 

  1120. 

  1121. 	if (of_property_read_bool(dev->of_node,
    1122. 

  1122. 				  "qcom,gnd-jack-type-normally-open"))
    1123. 

  1123. 		priv->gnd_jack_type_normally_open = true;
    1124. 

  1124. 	else
    1125. 

  1125. 		priv->gnd_jack_type_normally_open = false;
    1126. 

  1126. 

  1127. 	priv->mbhc_btn_enabled = true;
    1128. 

  1128. 	rval = of_property_read_u32_array(dev->of_node,
    1129. 

  1129. 					  "qcom,mbhc-vthreshold-low",
    1130. 

  1130. 					  &priv->vref_btn_cs[0],
    1131. 

  1131. 					  MBHC_MAX_BUTTONS);
    1132. 

  1132. 	if (rval < 0) {
    1133. 

  1133. 		priv->mbhc_btn_enabled = false;
    1134. 

  1134. 	} else {
    1135. 

  1135. 		rval = of_property_read_u32_array(dev->of_node,
    1136. 

  1136. 						  "qcom,mbhc-vthreshold-high",
    1137. 

  1137. 						  &priv->vref_btn_micb[0],
    1138. 

  1138. 						  MBHC_MAX_BUTTONS);
    1139. 

  1139. 		if (rval < 0)
    1140. 

  1140. 			priv->mbhc_btn_enabled = false;
    1141. 

  1141. 	}
    1142. 

  1142. 

  1143. 	if (!priv->mbhc_btn_enabled)
    1144. 

  1144. 		dev_err(dev,
    1145. 

  1145. 			"DT property missing, MBHC btn detection disabled\n");
    1146. 

  1146. 

  1147. 

  1148. 	return 0;
    1149. 

  1149. }
    1150. 

  1150. 

  1151. static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
    1152. 

  1152. {
    1153. 

  1153. 	struct pm8916_wcd_analog_priv *priv;
    1154. 

  1154. 	struct device *dev = &pdev->dev;
    1155. 

  1155. 	int ret, i, irq;
    1156. 

  1156. 

  1157. 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
    1158. 

  1158. 	if (!priv)
    1159. 

  1159. 		return -ENOMEM;
    1160. 

  1160. 

  1161. 	ret = pm8916_wcd_analog_parse_dt(dev, priv);
    1162. 

  1162. 	if (ret < 0)
    1163. 

  1163. 		return ret;
    1164. 

  1164. 

  1165. 	priv->mclk = devm_clk_get(dev, "mclk");
    1166. 

  1166. 	if (IS_ERR(priv->mclk)) {
    1167. 

  1167. 		dev_err(dev, "failed to get mclk\n");
    1168. 

  1168. 		return PTR_ERR(priv->mclk);
    1169. 

  1169. 	}
    1170. 

  1170. 

  1171. 	for (i = 0; i < ARRAY_SIZE(supply_names); i++)
    1172. 

  1172. 		priv->supplies[i].supply = supply_names[i];
    1173. 

  1173. 

  1174. 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
    1175. 

  1175. 				    priv->supplies);
    1176. 

  1176. 	if (ret) {
    1177. 

  1177. 		dev_err(dev, "Failed to get regulator supplies %d\n", ret);
    1178. 

  1178. 		return ret;
    1179. 

  1179. 	}
    1180. 

  1180. 

  1181. 	ret = clk_prepare_enable(priv->mclk);
    1182. 

  1182. 	if (ret < 0) {
    1183. 

  1183. 		dev_err(dev, "failed to enable mclk %d\n", ret);
    1184. 

  1184. 		return ret;
    1185. 

  1185. 	}
    1186. 

  1186. 

  1187. 	irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
    1188. 

  1188. 	if (irq < 0)
    1189. 

  1189. 		return irq;
    1190. 

  1190. 

  1191. 	ret = devm_request_threaded_irq(dev, irq, NULL,
    1192. 

  1192. 			       pm8916_mbhc_switch_irq_handler,
    1193. 

  1193. 			       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
    1194. 

  1194. 			       IRQF_ONESHOT,
    1195. 

  1195. 			       "mbhc switch irq", priv);
    1196. 

  1196. 	if (ret)
    1197. 

  1197. 		dev_err(dev, "cannot request mbhc switch irq\n");
    1198. 

  1198. 

  1199. 	if (priv->mbhc_btn_enabled) {
    1200. 

  1200. 		irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
    1201. 

  1201. 		if (irq < 0)
    1202. 

  1202. 			return irq;
    1203. 

  1203. 

  1204. 		ret = devm_request_threaded_irq(dev, irq, NULL,
    1205. 

  1205. 				       mbhc_btn_press_irq_handler,
    1206. 

  1206. 				       IRQF_TRIGGER_RISING |
    1207. 

  1207. 				       IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
    1208. 

  1208. 				       "mbhc btn press irq", priv);
    1209. 

  1209. 		if (ret)
    1210. 

  1210. 			dev_err(dev, "cannot request mbhc button press irq\n");
    1211. 

  1211. 

  1212. 		irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
    1213. 

  1213. 		if (irq < 0)
    1214. 

  1214. 			return irq;
    1215. 

  1215. 

  1216. 		ret = devm_request_threaded_irq(dev, irq, NULL,
    1217. 

  1217. 				       mbhc_btn_release_irq_handler,
    1218. 

  1218. 				       IRQF_TRIGGER_RISING |
    1219. 

  1219. 				       IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
    1220. 

  1220. 				       "mbhc btn release irq", priv);
    1221. 

  1221. 		if (ret)
    1222. 

  1222. 			dev_err(dev, "cannot request mbhc button release irq\n");
    1223. 

  1223. 

  1224. 	}
    1225. 

  1225. 

  1226. 	dev_set_drvdata(dev, priv);
    1227. 

  1227. 

  1228. 	return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
    1229. 

  1229. 				      pm8916_wcd_analog_dai,
    1230. 

  1230. 				      ARRAY_SIZE(pm8916_wcd_analog_dai));
    1231. 

  1231. }
    1232. 

  1232. 

  1233. static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
    1234. 

  1234. {
    1235. 

  1235. 	struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
    1236. 

  1236. 

  1237. 	clk_disable_unprepare(priv->mclk);
    1238. 

  1238. 

  1239. 	return 0;
    1240. 

  1240. }
    1241. 

  1241. 

  1242. static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
    1243. 

  1243. 	{ .compatible = "qcom,pm8916-wcd-analog-codec", },
    1244. 

  1244. 	{ }
    1245. 

  1245. };
    1246. 

  1246. 

  1247. MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
    1248. 

  1248. 

  1249. static struct platform_driver pm8916_wcd_analog_spmi_driver = {
    1250. 

  1250. 	.driver = {
    1251. 

  1251. 		   .name = "qcom,pm8916-wcd-spmi-codec",
    1252. 

  1252. 		   .of_match_table = pm8916_wcd_analog_spmi_match_table,
    1253. 

  1253. 	},
    1254. 

  1254. 	.probe = pm8916_wcd_analog_spmi_probe,
    1255. 

  1255. 	.remove = pm8916_wcd_analog_spmi_remove,
    1256. 

  1256. };
    1257. 

  1257. 

  1258. module_platform_driver(pm8916_wcd_analog_spmi_driver);
    1259. 

  1259. 

  1260. MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
    1261. 

  1261. MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
    1262. 

  1262. MODULE_LICENSE("GPL v2");
    1263. 

  1263.