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/sound/soc/codecs/msm8916-wcd-analog.c

https://codeberg.org/ddevault/linux
C | 1262 lines | 1028 code | 187 blank | 47 comment | 56 complexity | f560bb6a1cad0e89b06bcce91409c452 MD5 | raw file
Possible License(s): GPL-2.0
  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2016, The Linux Foundation. All rights reserved.
  3. #include <linux/module.h>
  4. #include <linux/err.h>
  5. #include <linux/kernel.h>
  6. #include <linux/delay.h>
  7. #include <linux/regulator/consumer.h>
  8. #include <linux/types.h>
  9. #include <linux/clk.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #include <sound/soc.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/tlv.h>
  17. #include <sound/jack.h>
  18. #define CDC_D_REVISION1 (0xf000)
  19. #define CDC_D_PERPH_SUBTYPE (0xf005)
  20. #define CDC_D_INT_EN_SET (0x015)
  21. #define CDC_D_INT_EN_CLR (0x016)
  22. #define MBHC_SWITCH_INT BIT(7)
  23. #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)
  24. #define MBHC_BUTTON_PRESS_DET BIT(5)
  25. #define MBHC_BUTTON_RELEASE_DET BIT(4)
  26. #define CDC_D_CDC_RST_CTL (0xf046)
  27. #define RST_CTL_DIG_SW_RST_N_MASK BIT(7)
  28. #define RST_CTL_DIG_SW_RST_N_RESET 0
  29. #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)
  30. #define CDC_D_CDC_TOP_CLK_CTL (0xf048)
  31. #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))
  32. #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)
  33. #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)
  34. #define CDC_D_CDC_ANA_CLK_CTL (0xf049)
  35. #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
  36. #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
  37. #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)
  38. #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)
  39. #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)
  40. #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)
  41. #define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
  42. #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
  43. #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)
  44. #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2)
  45. #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3)
  46. #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3)
  47. #define DIG_CLK_CTL_TXD_CLK_EN BIT(4)
  48. #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)
  49. #define DIG_CLK_CTL_NCP_CLK_EN BIT(6)
  50. #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)
  51. #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)
  52. #define CDC_D_CDC_CONN_TX1_CTL (0xf050)
  53. #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
  54. #define CONN_TX1_SERIAL_TX1_ADC_1 0x0
  55. #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
  56. #define CONN_TX1_SERIAL_TX1_ZERO 0x2
  57. #define CDC_D_CDC_CONN_TX2_CTL (0xf051)
  58. #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
  59. #define CONN_TX2_SERIAL_TX2_ADC_2 0x0
  60. #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
  61. #define CONN_TX2_SERIAL_TX2_ZERO 0x2
  62. #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
  63. #define CDC_D_CDC_CONN_RX1_CTL (0xf053)
  64. #define CDC_D_CDC_CONN_RX2_CTL (0xf054)
  65. #define CDC_D_CDC_CONN_RX3_CTL (0xf055)
  66. #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
  67. #define CDC_D_SEC_ACCESS (0xf0D0)
  68. #define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
  69. #define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
  70. #define CDC_A_REVISION1 (0xf100)
  71. #define CDC_A_REVISION2 (0xf101)
  72. #define CDC_A_REVISION3 (0xf102)
  73. #define CDC_A_REVISION4 (0xf103)
  74. #define CDC_A_PERPH_TYPE (0xf104)
  75. #define CDC_A_PERPH_SUBTYPE (0xf105)
  76. #define CDC_A_INT_RT_STS (0xf110)
  77. #define CDC_A_INT_SET_TYPE (0xf111)
  78. #define CDC_A_INT_POLARITY_HIGH (0xf112)
  79. #define CDC_A_INT_POLARITY_LOW (0xf113)
  80. #define CDC_A_INT_LATCHED_CLR (0xf114)
  81. #define CDC_A_INT_EN_SET (0xf115)
  82. #define CDC_A_INT_EN_CLR (0xf116)
  83. #define CDC_A_INT_LATCHED_STS (0xf118)
  84. #define CDC_A_INT_PENDING_STS (0xf119)
  85. #define CDC_A_INT_MID_SEL (0xf11A)
  86. #define CDC_A_INT_PRIORITY (0xf11B)
  87. #define CDC_A_MICB_1_EN (0xf140)
  88. #define MICB_1_EN_MICB_ENABLE BIT(7)
  89. #define MICB_1_EN_BYP_CAP_MASK BIT(6)
  90. #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)
  91. #define MICB_1_EN_EXT_BYP_CAP 0
  92. #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)
  93. #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)
  94. #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)
  95. #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
  96. #define MICB_1_EN_PULL_UP_EN_MASK BIT(4)
  97. #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
  98. #define MICB_1_EN_TX3_GND_SEL_TX_GND 0
  99. #define CDC_A_MICB_1_VAL (0xf141)
  100. #define MICB_MIN_VAL 1600
  101. #define MICB_STEP_SIZE 50
  102. #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)
  103. #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)
  104. #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
  105. #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
  106. #define CDC_A_MICB_1_CTL (0xf142)
  107. #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)
  108. #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)
  109. #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)
  110. #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)
  111. #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)
  112. #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)
  113. #define CDC_A_MICB_1_INT_RBIAS (0xf143)
  114. #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)
  115. #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)
  116. #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
  117. #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)
  118. #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)
  119. #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
  120. #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)
  121. #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)
  122. #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
  123. #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)
  124. #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)
  125. #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
  126. #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)
  127. #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)
  128. #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
  129. #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
  130. #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
  131. #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
  132. #define CDC_A_MICB_2_EN (0xf144)
  133. #define CDC_A_MICB_2_EN_ENABLE BIT(7)
  134. #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5)
  135. #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5)
  136. #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
  137. #define CDC_A_MASTER_BIAS_CTL (0xf146)
  138. #define CDC_A_MBHC_DET_CTL_1 (0xf147)
  139. #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7)
  140. #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6)
  141. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5)
  142. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
  143. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5)
  144. #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5)
  145. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4)
  146. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3)
  147. #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)
  148. #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2)
  149. #define CDC_A_MBHC_DET_CTL_2 (0xf150)
  150. #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6))
  151. #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)
  152. #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)
  153. #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4)
  154. #define CDC_A_GND_PLUG_TYPE_NO BIT(3)
  155. #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
  156. #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
  157. #define CDC_A_MBHC_FSM_CTL (0xf151)
  158. #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7)
  159. #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7)
  160. #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
  161. #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)
  162. #define CDC_A_MBHC_DBNC_TIMER (0xf152)
  163. #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3)
  164. #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
  165. #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
  166. #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
  167. #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
  168. #define CDC_A_MBHC_BTN3_CTL (0xf156)
  169. #define CDC_A_MBHC_BTN4_CTL (0xf157)
  170. #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2)
  171. #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)
  172. #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)
  173. #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)
  174. #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \
  175. CDC_A_MBHC_BTN_VREF_FINE_MASK)
  176. #define CDC_A_MBHC_RESULT_1 (0xf158)
  177. #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
  178. #define CDC_A_TX_1_EN (0xf160)
  179. #define CDC_A_TX_2_EN (0xf161)
  180. #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
  181. #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
  182. #define CDC_A_TX_1_2_ATEST_CTL (0xf164)
  183. #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
  184. #define CDC_A_TX_3_EN (0xf167)
  185. #define CDC_A_NCP_EN (0xf180)
  186. #define CDC_A_NCP_CLK (0xf181)
  187. #define CDC_A_NCP_FBCTRL (0xf183)
  188. #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)
  189. #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)
  190. #define CDC_A_NCP_BIAS (0xf184)
  191. #define CDC_A_NCP_VCTRL (0xf185)
  192. #define CDC_A_NCP_TEST (0xf186)
  193. #define CDC_A_NCP_CLIM_ADDR (0xf187)
  194. #define CDC_A_RX_CLOCK_DIVIDER (0xf190)
  195. #define CDC_A_RX_COM_OCP_CTL (0xf191)
  196. #define CDC_A_RX_COM_OCP_COUNT (0xf192)
  197. #define CDC_A_RX_COM_BIAS_DAC (0xf193)
  198. #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)
  199. #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)
  200. #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
  201. #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
  202. #define CDC_A_RX_HPH_BIAS_PA (0xf194)
  203. #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
  204. #define CDC_A_RX_HPH_BIAS_CNP (0xf196)
  205. #define CDC_A_RX_HPH_CNP_EN (0xf197)
  206. #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
  207. #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
  208. #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)
  209. #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
  210. #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)
  211. #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)
  212. #define CDC_A_RX_EAR_CTL (0xf19E)
  213. #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
  214. #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
  215. #define CDC_A_SPKR_DAC_CTL (0xf1B0)
  216. #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)
  217. #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
  218. #define CDC_A_SPKR_DRV_CTL (0xf1B2)
  219. #define SPKR_DRV_CTL_DEF_MASK 0xEF
  220. #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)
  221. #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)
  222. #define SPKR_DRV_CAL_EN BIT(6)
  223. #define SPKR_DRV_SETTLE_EN BIT(5)
  224. #define SPKR_DRV_FW_EN BIT(3)
  225. #define SPKR_DRV_BOOST_SET BIT(2)
  226. #define SPKR_DRV_CMFB_SET BIT(1)
  227. #define SPKR_DRV_GAIN_SET BIT(0)
  228. #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \
  229. SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
  230. SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
  231. SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET)
  232. #define CDC_A_SPKR_OCP_CTL (0xf1B4)
  233. #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
  234. #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
  235. #define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
  236. #define SPKR_PWRSTG_CTL_MASK 0xE0
  237. #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)
  238. #define SPKR_PWRSTG_CTL_BBM_EN BIT(7)
  239. #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)
  240. #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)
  241. #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)
  242. #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)
  243. #define CDC_A_SPKR_DRV_DBG (0xf1B7)
  244. #define CDC_A_CURRENT_LIMIT (0xf1C0)
  245. #define CDC_A_BOOST_EN_CTL (0xf1C3)
  246. #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
  247. #define CDC_A_SEC_ACCESS (0xf1D0)
  248. #define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
  249. #define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
  250. #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  251. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
  252. #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  253. SNDRV_PCM_FMTBIT_S32_LE)
  254. static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
  255. SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4;
  256. static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;
  257. static const char * const supply_names[] = {
  258. "vdd-cdc-io",
  259. "vdd-cdc-tx-rx-cx",
  260. };
  261. #define MBHC_MAX_BUTTONS (5)
  262. struct pm8916_wcd_analog_priv {
  263. u16 pmic_rev;
  264. u16 codec_version;
  265. bool mbhc_btn_enabled;
  266. /* special event to detect accessory type */
  267. int mbhc_btn0_released;
  268. bool detect_accessory_type;
  269. struct clk *mclk;
  270. struct snd_soc_component *component;
  271. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  272. struct snd_soc_jack *jack;
  273. bool hphl_jack_type_normally_open;
  274. bool gnd_jack_type_normally_open;
  275. /* Voltage threshold when internal current source of 100uA is used */
  276. u32 vref_btn_cs[MBHC_MAX_BUTTONS];
  277. /* Voltage threshold when microphone bias is ON */
  278. u32 vref_btn_micb[MBHC_MAX_BUTTONS];
  279. unsigned int micbias1_cap_mode;
  280. unsigned int micbias2_cap_mode;
  281. unsigned int micbias_mv;
  282. };
  283. static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" };
  284. static const char *const rdac2_mux_text[] = { "ZERO", "RX2", "RX1" };
  285. static const char *const hph_text[] = { "ZERO", "Switch", };
  286. static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(
  287. ARRAY_SIZE(hph_text), hph_text);
  288. static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum);
  289. static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum);
  290. /* ADC2 MUX */
  291. static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(
  292. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  293. /* RDAC2 MUX */
  294. static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(
  295. CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 3, rdac2_mux_text);
  296. static const struct snd_kcontrol_new spkr_switch[] = {
  297. SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
  298. };
  299. static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM(
  300. "RDAC2 MUX Mux", rdac2_mux_enum);
  301. static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM(
  302. "ADC2 MUX Mux", adc2_enum);
  303. /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
  304. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
  305. static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {
  306. SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
  307. SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
  308. SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
  309. };
  310. static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)
  311. {
  312. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  313. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  314. MICB_1_CTL_EXT_PRECHARG_EN_MASK |
  315. MICB_1_CTL_INT_PRECHARG_BYP_MASK,
  316. MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL
  317. | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE);
  318. if (wcd->micbias_mv) {
  319. snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL,
  320. MICB_1_VAL_MICB_OUT_VAL_MASK,
  321. MICB_VOLTAGE_REGVAL(wcd->micbias_mv));
  322. /*
  323. * Special headset needs MICBIAS as 2.7V so wait for
  324. * 50 msec for the MICBIAS to reach 2.7 volts.
  325. */
  326. if (wcd->micbias_mv >= 2700)
  327. msleep(50);
  328. }
  329. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  330. MICB_1_CTL_EXT_PRECHARG_EN_MASK |
  331. MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0);
  332. }
  333. static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_component
  334. *component, int event,
  335. int reg, unsigned int cap_mode)
  336. {
  337. switch (event) {
  338. case SND_SOC_DAPM_POST_PMU:
  339. pm8916_wcd_analog_micbias_enable(component);
  340. snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
  341. MICB_1_EN_BYP_CAP_MASK, cap_mode);
  342. break;
  343. }
  344. return 0;
  345. }
  346. static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_component
  347. *component, int event,
  348. int reg, u32 cap_mode)
  349. {
  350. switch (event) {
  351. case SND_SOC_DAPM_PRE_PMU:
  352. snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
  353. MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
  354. MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
  355. snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0);
  356. snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
  357. MICB_1_EN_OPA_STG2_TAIL_CURR_MASK,
  358. MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA);
  359. break;
  360. case SND_SOC_DAPM_POST_PMU:
  361. pm8916_wcd_analog_micbias_enable(component);
  362. snd_soc_component_update_bits(component, CDC_A_MICB_1_EN,
  363. MICB_1_EN_BYP_CAP_MASK, cap_mode);
  364. break;
  365. }
  366. return 0;
  367. }
  368. static int pm8916_wcd_analog_enable_micbias_ext1(struct
  369. snd_soc_dapm_widget
  370. *w, struct snd_kcontrol
  371. *kcontrol, int event)
  372. {
  373. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  374. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  375. return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg,
  376. wcd->micbias1_cap_mode);
  377. }
  378. static int pm8916_wcd_analog_enable_micbias_ext2(struct
  379. snd_soc_dapm_widget
  380. *w, struct snd_kcontrol
  381. *kcontrol, int event)
  382. {
  383. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  384. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  385. return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg,
  386. wcd->micbias2_cap_mode);
  387. }
  388. static int pm8916_wcd_analog_enable_micbias_int1(struct
  389. snd_soc_dapm_widget
  390. *w, struct snd_kcontrol
  391. *kcontrol, int event)
  392. {
  393. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  394. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  395. return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg,
  396. wcd->micbias1_cap_mode);
  397. }
  398. static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,
  399. bool micbias2_enabled)
  400. {
  401. struct snd_soc_component *component = priv->component;
  402. u32 coarse, fine, reg_val, reg_addr;
  403. int *vrefs, i;
  404. if (!micbias2_enabled) { /* use internal 100uA Current source */
  405. /* Enable internal 2.2k Internal Rbias Resistor */
  406. snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS,
  407. MICB_1_INT_TX2_INT_RBIAS_EN_MASK,
  408. MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE);
  409. /* Remove pull down on MIC BIAS2 */
  410. snd_soc_component_update_bits(component, CDC_A_MICB_2_EN,
  411. CDC_A_MICB_2_PULL_DOWN_EN_MASK,
  412. 0);
  413. /* enable 100uA internal current source */
  414. snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
  415. CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK,
  416. CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA);
  417. }
  418. snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL,
  419. CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK,
  420. CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN);
  421. if (micbias2_enabled)
  422. vrefs = &priv->vref_btn_micb[0];
  423. else
  424. vrefs = &priv->vref_btn_cs[0];
  425. /* program vref ranges for all the buttons */
  426. reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0;
  427. for (i = 0; i < MBHC_MAX_BUTTONS; i++) {
  428. /* split mv in to coarse parts of 100mv & fine parts of 12mv */
  429. coarse = (vrefs[i] / 100);
  430. fine = ((vrefs[i] % 100) / 12);
  431. reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) |
  432. (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT);
  433. snd_soc_component_update_bits(component, reg_addr,
  434. CDC_A_MBHC_BTN_VREF_MASK,
  435. reg_val);
  436. reg_addr++;
  437. }
  438. return 0;
  439. }
  440. static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)
  441. {
  442. struct snd_soc_component *component = wcd->component;
  443. bool micbias_enabled = false;
  444. u32 plug_type = 0;
  445. u32 int_en_mask;
  446. snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1,
  447. CDC_A_MBHC_DET_CTL_L_DET_EN |
  448. CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION |
  449. CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO |
  450. CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN);
  451. if (wcd->hphl_jack_type_normally_open)
  452. plug_type |= CDC_A_HPHL_PLUG_TYPE_NO;
  453. if (wcd->gnd_jack_type_normally_open)
  454. plug_type |= CDC_A_GND_PLUG_TYPE_NO;
  455. snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2,
  456. CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 |
  457. CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD |
  458. plug_type |
  459. CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN);
  460. snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER,
  461. CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS |
  462. CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS);
  463. /* enable MBHC clock */
  464. snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL,
  465. DIG_CLK_CTL_D_MBHC_CLK_EN_MASK,
  466. DIG_CLK_CTL_D_MBHC_CLK_EN);
  467. if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)
  468. micbias_enabled = true;
  469. pm8916_mbhc_configure_bias(wcd, micbias_enabled);
  470. int_en_mask = MBHC_SWITCH_INT;
  471. if (wcd->mbhc_btn_enabled)
  472. int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET;
  473. snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0);
  474. snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask);
  475. wcd->mbhc_btn0_released = false;
  476. wcd->detect_accessory_type = true;
  477. }
  478. static int pm8916_wcd_analog_enable_micbias_int2(struct
  479. snd_soc_dapm_widget
  480. *w, struct snd_kcontrol
  481. *kcontrol, int event)
  482. {
  483. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  484. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  485. switch (event) {
  486. case SND_SOC_DAPM_POST_PMU:
  487. pm8916_mbhc_configure_bias(wcd, true);
  488. break;
  489. case SND_SOC_DAPM_POST_PMD:
  490. pm8916_mbhc_configure_bias(wcd, false);
  491. break;
  492. }
  493. return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg,
  494. wcd->micbias2_cap_mode);
  495. }
  496. static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,
  497. struct snd_kcontrol *kcontrol,
  498. int event)
  499. {
  500. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  501. u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2;
  502. u8 init_bit_shift;
  503. if (w->reg == CDC_A_TX_1_EN)
  504. init_bit_shift = 5;
  505. else
  506. init_bit_shift = 4;
  507. switch (event) {
  508. case SND_SOC_DAPM_PRE_PMU:
  509. if (w->reg == CDC_A_TX_2_EN)
  510. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  511. MICB_1_CTL_CFILT_REF_SEL_MASK,
  512. MICB_1_CTL_CFILT_REF_SEL_HPF_REF);
  513. /*
  514. * Add delay of 10 ms to give sufficient time for the voltage
  515. * to shoot up and settle so that the txfe init does not
  516. * happen when the input voltage is changing too much.
  517. */
  518. usleep_range(10000, 10010);
  519. snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift,
  520. 1 << init_bit_shift);
  521. switch (w->reg) {
  522. case CDC_A_TX_1_EN:
  523. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
  524. CONN_TX1_SERIAL_TX1_MUX,
  525. CONN_TX1_SERIAL_TX1_ADC_1);
  526. break;
  527. case CDC_A_TX_2_EN:
  528. case CDC_A_TX_3_EN:
  529. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
  530. CONN_TX2_SERIAL_TX2_MUX,
  531. CONN_TX2_SERIAL_TX2_ADC_2);
  532. break;
  533. }
  534. break;
  535. case SND_SOC_DAPM_POST_PMU:
  536. /*
  537. * Add delay of 12 ms before deasserting the init
  538. * to reduce the tx pop
  539. */
  540. usleep_range(12000, 12010);
  541. snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00);
  542. break;
  543. case SND_SOC_DAPM_POST_PMD:
  544. switch (w->reg) {
  545. case CDC_A_TX_1_EN:
  546. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL,
  547. CONN_TX1_SERIAL_TX1_MUX,
  548. CONN_TX1_SERIAL_TX1_ZERO);
  549. break;
  550. case CDC_A_TX_2_EN:
  551. snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL,
  552. MICB_1_CTL_CFILT_REF_SEL_MASK, 0);
  553. /* fall through */
  554. case CDC_A_TX_3_EN:
  555. snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL,
  556. CONN_TX2_SERIAL_TX2_MUX,
  557. CONN_TX2_SERIAL_TX2_ZERO);
  558. break;
  559. }
  560. break;
  561. }
  562. return 0;
  563. }
  564. static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,
  565. struct snd_kcontrol *kcontrol,
  566. int event)
  567. {
  568. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  569. switch (event) {
  570. case SND_SOC_DAPM_PRE_PMU:
  571. snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
  572. SPKR_PWRSTG_CTL_DAC_EN_MASK |
  573. SPKR_PWRSTG_CTL_BBM_MASK |
  574. SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
  575. SPKR_PWRSTG_CTL_CLAMP_EN_MASK,
  576. SPKR_PWRSTG_CTL_DAC_EN|
  577. SPKR_PWRSTG_CTL_BBM_EN |
  578. SPKR_PWRSTG_CTL_HBRDGE_EN |
  579. SPKR_PWRSTG_CTL_CLAMP_EN);
  580. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  581. RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK,
  582. RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE);
  583. break;
  584. case SND_SOC_DAPM_POST_PMU:
  585. snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL,
  586. SPKR_DRV_CTL_DEF_MASK,
  587. SPKR_DRV_CTL_DEF_VAL);
  588. snd_soc_component_update_bits(component, w->reg,
  589. SPKR_DRV_CLASSD_PA_EN_MASK,
  590. SPKR_DRV_CLASSD_PA_EN_ENABLE);
  591. break;
  592. case SND_SOC_DAPM_POST_PMD:
  593. snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL,
  594. SPKR_PWRSTG_CTL_DAC_EN_MASK|
  595. SPKR_PWRSTG_CTL_BBM_MASK |
  596. SPKR_PWRSTG_CTL_HBRDGE_EN_MASK |
  597. SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0);
  598. snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL,
  599. SPKR_DAC_CTL_DAC_RESET_MASK,
  600. SPKR_DAC_CTL_DAC_RESET_NORMAL);
  601. snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL,
  602. RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0);
  603. break;
  604. }
  605. return 0;
  606. }
  607. static const struct reg_default wcd_reg_defaults_2_0[] = {
  608. {CDC_A_RX_COM_OCP_CTL, 0xD1},
  609. {CDC_A_RX_COM_OCP_COUNT, 0xFF},
  610. {CDC_D_SEC_ACCESS, 0xA5},
  611. {CDC_D_PERPH_RESET_CTL3, 0x0F},
  612. {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
  613. {CDC_A_NCP_FBCTRL, 0x28},
  614. {CDC_A_SPKR_DRV_CTL, 0x69},
  615. {CDC_A_SPKR_DRV_DBG, 0x01},
  616. {CDC_A_BOOST_EN_CTL, 0x5F},
  617. {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
  618. {CDC_A_SEC_ACCESS, 0xA5},
  619. {CDC_A_PERPH_RESET_CTL3, 0x0F},
  620. {CDC_A_CURRENT_LIMIT, 0x82},
  621. {CDC_A_SPKR_DAC_CTL, 0x03},
  622. {CDC_A_SPKR_OCP_CTL, 0xE1},
  623. {CDC_A_MASTER_BIAS_CTL, 0x30},
  624. };
  625. static int pm8916_wcd_analog_probe(struct snd_soc_component *component)
  626. {
  627. struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
  628. int err, reg;
  629. err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
  630. if (err != 0) {
  631. dev_err(component->dev, "failed to enable regulators (%d)\n", err);
  632. return err;
  633. }
  634. snd_soc_component_init_regmap(component,
  635. dev_get_regmap(component->dev->parent, NULL));
  636. snd_soc_component_set_drvdata(component, priv);
  637. priv->pmic_rev = snd_soc_component_read32(component, CDC_D_REVISION1);
  638. priv->codec_version = snd_soc_component_read32(component, CDC_D_PERPH_SUBTYPE);
  639. dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n",
  640. priv->pmic_rev, priv->codec_version);
  641. snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01);
  642. snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01);
  643. for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)
  644. snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg,
  645. wcd_reg_defaults_2_0[reg].def);
  646. priv->component = component;
  647. snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
  648. RST_CTL_DIG_SW_RST_N_MASK,
  649. RST_CTL_DIG_SW_RST_N_REMOVE_RESET);
  650. pm8916_wcd_setup_mbhc(priv);
  651. return 0;
  652. }
  653. static void pm8916_wcd_analog_remove(struct snd_soc_component *component)
  654. {
  655. struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);
  656. snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL,
  657. RST_CTL_DIG_SW_RST_N_MASK, 0);
  658. regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
  659. priv->supplies);
  660. }
  661. static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {
  662. {"PDM_RX1", NULL, "PDM Playback"},
  663. {"PDM_RX2", NULL, "PDM Playback"},
  664. {"PDM_RX3", NULL, "PDM Playback"},
  665. {"PDM Capture", NULL, "PDM_TX"},
  666. /* ADC Connections */
  667. {"PDM_TX", NULL, "ADC2"},
  668. {"PDM_TX", NULL, "ADC3"},
  669. {"ADC2", NULL, "ADC2 MUX"},
  670. {"ADC3", NULL, "ADC2 MUX"},
  671. {"ADC2 MUX", "INP2", "ADC2_INP2"},
  672. {"ADC2 MUX", "INP3", "ADC2_INP3"},
  673. {"PDM_TX", NULL, "ADC1"},
  674. {"ADC1", NULL, "AMIC1"},
  675. {"ADC2_INP2", NULL, "AMIC2"},
  676. {"ADC2_INP3", NULL, "AMIC3"},
  677. /* RDAC Connections */
  678. {"HPHR DAC", NULL, "RDAC2 MUX"},
  679. {"RDAC2 MUX", "RX1", "PDM_RX1"},
  680. {"RDAC2 MUX", "RX2", "PDM_RX2"},
  681. {"HPHL DAC", NULL, "PDM_RX1"},
  682. {"PDM_RX1", NULL, "RXD1_CLK"},
  683. {"PDM_RX2", NULL, "RXD2_CLK"},
  684. {"PDM_RX3", NULL, "RXD3_CLK"},
  685. {"PDM_RX1", NULL, "RXD_PDM_CLK"},
  686. {"PDM_RX2", NULL, "RXD_PDM_CLK"},
  687. {"PDM_RX3", NULL, "RXD_PDM_CLK"},
  688. {"ADC1", NULL, "TXD_CLK"},
  689. {"ADC2", NULL, "TXD_CLK"},
  690. {"ADC3", NULL, "TXD_CLK"},
  691. {"ADC1", NULL, "TXA_CLK25"},
  692. {"ADC2", NULL, "TXA_CLK25"},
  693. {"ADC3", NULL, "TXA_CLK25"},
  694. {"PDM_RX1", NULL, "A_MCLK2"},
  695. {"PDM_RX2", NULL, "A_MCLK2"},
  696. {"PDM_RX3", NULL, "A_MCLK2"},
  697. {"PDM_TX", NULL, "A_MCLK2"},
  698. {"A_MCLK2", NULL, "A_MCLK"},
  699. /* Headset (RX MIX1 and RX MIX2) */
  700. {"HEADPHONE", NULL, "HPHL PA"},
  701. {"HEADPHONE", NULL, "HPHR PA"},
  702. {"HPHL PA", NULL, "EAR_HPHL_CLK"},
  703. {"HPHR PA", NULL, "EAR_HPHR_CLK"},
  704. {"CP", NULL, "NCP_CLK"},
  705. {"HPHL PA", NULL, "HPHL"},
  706. {"HPHR PA", NULL, "HPHR"},
  707. {"HPHL PA", NULL, "CP"},
  708. {"HPHL PA", NULL, "RX_BIAS"},
  709. {"HPHR PA", NULL, "CP"},
  710. {"HPHR PA", NULL, "RX_BIAS"},
  711. {"HPHL", "Switch", "HPHL DAC"},
  712. {"HPHR", "Switch", "HPHR DAC"},
  713. {"RX_BIAS", NULL, "DAC_REF"},
  714. {"SPK_OUT", NULL, "SPK PA"},
  715. {"SPK PA", NULL, "RX_BIAS"},
  716. {"SPK PA", NULL, "SPKR_CLK"},
  717. {"SPK PA", NULL, "SPK DAC"},
  718. {"SPK DAC", "Switch", "PDM_RX3"},
  719. {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
  720. {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
  721. {"MIC BIAS External1", NULL, "INT_LDO_H"},
  722. {"MIC BIAS External2", NULL, "INT_LDO_H"},
  723. {"MIC BIAS Internal1", NULL, "vdd-micbias"},
  724. {"MIC BIAS Internal2", NULL, "vdd-micbias"},
  725. {"MIC BIAS External1", NULL, "vdd-micbias"},
  726. {"MIC BIAS External2", NULL, "vdd-micbias"},
  727. };
  728. static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {
  729. SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
  730. SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
  731. SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
  732. SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
  733. SND_SOC_DAPM_INPUT("AMIC1"),
  734. SND_SOC_DAPM_INPUT("AMIC3"),
  735. SND_SOC_DAPM_INPUT("AMIC2"),
  736. SND_SOC_DAPM_OUTPUT("HEADPHONE"),
  737. /* RX stuff */
  738. SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
  739. SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
  740. SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
  741. SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
  742. 0),
  743. SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
  744. SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
  745. SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
  746. 0),
  747. SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
  748. spkr_switch, ARRAY_SIZE(spkr_switch)),
  749. /* Speaker */
  750. SND_SOC_DAPM_OUTPUT("SPK_OUT"),
  751. SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL,
  752. 6, 0, NULL, 0,
  753. pm8916_wcd_analog_enable_spk_pa,
  754. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  755. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  756. SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
  757. SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
  758. SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
  759. SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
  760. /* TX */
  761. SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0,
  762. pm8916_wcd_analog_enable_micbias_int1,
  763. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  764. SND_SOC_DAPM_POST_PMD),
  765. SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0,
  766. pm8916_wcd_analog_enable_micbias_int2,
  767. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  768. SND_SOC_DAPM_POST_PMD),
  769. SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0,
  770. pm8916_wcd_analog_enable_micbias_ext1,
  771. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  772. SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0,
  773. pm8916_wcd_analog_enable_micbias_ext2,
  774. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  775. SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
  776. pm8916_wcd_analog_enable_adc,
  777. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  778. SND_SOC_DAPM_POST_PMD),
  779. SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
  780. pm8916_wcd_analog_enable_adc,
  781. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  782. SND_SOC_DAPM_POST_PMD),
  783. SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
  784. pm8916_wcd_analog_enable_adc,
  785. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  786. SND_SOC_DAPM_POST_PMD),
  787. SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  788. SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
  789. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
  790. SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
  791. /* Analog path clocks */
  792. SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
  793. 0),
  794. SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
  795. 0),
  796. SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
  797. SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
  798. /* Digital path clocks */
  799. SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
  800. SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
  801. SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
  802. SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
  803. SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
  804. SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
  805. 0),
  806. /* System Clock source */
  807. SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
  808. /* TX ADC and RX DAC Clock source. */
  809. SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
  810. };
  811. static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,
  812. struct snd_soc_jack *jack,
  813. void *data)
  814. {
  815. struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);
  816. wcd->jack = jack;
  817. return 0;
  818. }
  819. static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
  820. {
  821. struct pm8916_wcd_analog_priv *priv = arg;
  822. if (priv->detect_accessory_type) {
  823. struct snd_soc_component *component = priv->component;
  824. u32 val = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1);
  825. /* check if its BTN0 thats released */
  826. if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))
  827. priv->mbhc_btn0_released = true;
  828. } else {
  829. snd_soc_jack_report(priv->jack, 0, btn_mask);
  830. }
  831. return IRQ_HANDLED;
  832. }
  833. static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)
  834. {
  835. struct pm8916_wcd_analog_priv *priv = arg;
  836. struct snd_soc_component *component = priv->component;
  837. u32 btn_result;
  838. btn_result = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1) &
  839. CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK;
  840. switch (btn_result) {
  841. case 0xf:
  842. snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask);
  843. break;
  844. case 0x7:
  845. snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask);
  846. break;
  847. case 0x3:
  848. snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask);
  849. break;
  850. case 0x1:
  851. snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask);
  852. break;
  853. case 0x0:
  854. /* handle BTN_0 specially for type detection */
  855. if (!priv->detect_accessory_type)
  856. snd_soc_jack_report(priv->jack,
  857. SND_JACK_BTN_0, btn_mask);
  858. break;
  859. default:
  860. dev_err(component->dev,
  861. "Unexpected button press result (%x)", btn_result);
  862. break;
  863. }
  864. return IRQ_HANDLED;
  865. }
  866. static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)
  867. {
  868. struct pm8916_wcd_analog_priv *priv = arg;
  869. struct snd_soc_component *component = priv->component;
  870. bool ins = false;
  871. if (snd_soc_component_read32(component, CDC_A_MBHC_DET_CTL_1) &
  872. CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK)
  873. ins = true;
  874. /* Set the detection type appropriately */
  875. snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1,
  876. CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK,
  877. (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT));
  878. if (ins) { /* hs insertion */
  879. bool micbias_enabled = false;
  880. if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) &
  881. CDC_A_MICB_2_EN_ENABLE)
  882. micbias_enabled = true;
  883. pm8916_mbhc_configure_bias(priv, micbias_enabled);
  884. /*
  885. * if only a btn0 press event is receive just before
  886. * insert event then its a 3 pole headphone else if
  887. * both press and release event received then its
  888. * a headset.
  889. */
  890. if (priv->mbhc_btn0_released)
  891. snd_soc_jack_report(priv->jack,
  892. SND_JACK_HEADSET, hs_jack_mask);
  893. else
  894. snd_soc_jack_report(priv->jack,
  895. SND_JACK_HEADPHONE, hs_jack_mask);
  896. priv->detect_accessory_type = false;
  897. } else { /* removal */
  898. snd_soc_jack_report(priv->jack, 0, hs_jack_mask);
  899. priv->detect_accessory_type = true;
  900. priv->mbhc_btn0_released = false;
  901. }
  902. return IRQ_HANDLED;
  903. }
  904. static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {
  905. [0] = {
  906. .name = "pm8916_wcd_analog_pdm_rx",
  907. .id = 0,
  908. .playback = {
  909. .stream_name = "PDM Playback",
  910. .rates = MSM8916_WCD_ANALOG_RATES,
  911. .formats = MSM8916_WCD_ANALOG_FORMATS,
  912. .channels_min = 1,
  913. .channels_max = 3,
  914. },
  915. },
  916. [1] = {
  917. .name = "pm8916_wcd_analog_pdm_tx",
  918. .id = 1,
  919. .capture = {
  920. .stream_name = "PDM Capture",
  921. .rates = MSM8916_WCD_ANALOG_RATES,
  922. .formats = MSM8916_WCD_ANALOG_FORMATS,
  923. .channels_min = 1,
  924. .channels_max = 4,
  925. },
  926. },
  927. };
  928. static const struct snd_soc_component_driver pm8916_wcd_analog = {
  929. .probe = pm8916_wcd_analog_probe,
  930. .remove = pm8916_wcd_analog_remove,
  931. .set_jack = pm8916_wcd_analog_set_jack,
  932. .controls = pm8916_wcd_analog_snd_controls,
  933. .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
  934. .dapm_widgets = pm8916_wcd_analog_dapm_widgets,
  935. .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets),
  936. .dapm_routes = pm8916_wcd_analog_audio_map,
  937. .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map),
  938. .idle_bias_on = 1,
  939. .use_pmdown_time = 1,
  940. .endianness = 1,
  941. .non_legacy_dai_naming = 1,
  942. };
  943. static int pm8916_wcd_analog_parse_dt(struct device *dev,
  944. struct pm8916_wcd_analog_priv *priv)
  945. {
  946. int rval;
  947. if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap"))
  948. priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP;
  949. else
  950. priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
  951. if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap"))
  952. priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP;
  953. else
  954. priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP;
  955. of_property_read_u32(dev->of_node, "qcom,micbias-lvl",
  956. &priv->micbias_mv);
  957. if (of_property_read_bool(dev->of_node,
  958. "qcom,hphl-jack-type-normally-open"))
  959. priv->hphl_jack_type_normally_open = true;
  960. else
  961. priv->hphl_jack_type_normally_open = false;
  962. if (of_property_read_bool(dev->of_node,
  963. "qcom,gnd-jack-type-normally-open"))
  964. priv->gnd_jack_type_normally_open = true;
  965. else
  966. priv->gnd_jack_type_normally_open = false;
  967. priv->mbhc_btn_enabled = true;
  968. rval = of_property_read_u32_array(dev->of_node,
  969. "qcom,mbhc-vthreshold-low",
  970. &priv->vref_btn_cs[0],
  971. MBHC_MAX_BUTTONS);
  972. if (rval < 0) {
  973. priv->mbhc_btn_enabled = false;
  974. } else {
  975. rval = of_property_read_u32_array(dev->of_node,
  976. "qcom,mbhc-vthreshold-high",
  977. &priv->vref_btn_micb[0],
  978. MBHC_MAX_BUTTONS);
  979. if (rval < 0)
  980. priv->mbhc_btn_enabled = false;
  981. }
  982. if (!priv->mbhc_btn_enabled)
  983. dev_err(dev,
  984. "DT property missing, MBHC btn detection disabled\n");
  985. return 0;
  986. }
  987. static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)
  988. {
  989. struct pm8916_wcd_analog_priv *priv;
  990. struct device *dev = &pdev->dev;
  991. int ret, i, irq;
  992. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  993. if (!priv)
  994. return -ENOMEM;
  995. ret = pm8916_wcd_analog_parse_dt(dev, priv);
  996. if (ret < 0)
  997. return ret;
  998. priv->mclk = devm_clk_get(dev, "mclk");
  999. if (IS_ERR(priv->mclk)) {
  1000. dev_err(dev, "failed to get mclk\n");
  1001. return PTR_ERR(priv->mclk);
  1002. }
  1003. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  1004. priv->supplies[i].supply = supply_names[i];
  1005. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
  1006. priv->supplies);
  1007. if (ret) {
  1008. dev_err(dev, "Failed to get regulator supplies %d\n", ret);
  1009. return ret;
  1010. }
  1011. ret = clk_prepare_enable(priv->mclk);
  1012. if (ret < 0) {
  1013. dev_err(dev, "failed to enable mclk %d\n", ret);
  1014. return ret;
  1015. }
  1016. irq = platform_get_irq_byname(pdev, "mbhc_switch_int");
  1017. if (irq < 0)
  1018. return irq;
  1019. ret = devm_request_threaded_irq(dev, irq, NULL,
  1020. pm8916_mbhc_switch_irq_handler,
  1021. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
  1022. IRQF_ONESHOT,
  1023. "mbhc switch irq", priv);
  1024. if (ret)
  1025. dev_err(dev, "cannot request mbhc switch irq\n");
  1026. if (priv->mbhc_btn_enabled) {
  1027. irq = platform_get_irq_byname(pdev, "mbhc_but_press_det");
  1028. if (irq < 0)
  1029. return irq;
  1030. ret = devm_request_threaded_irq(dev, irq, NULL,
  1031. mbhc_btn_press_irq_handler,
  1032. IRQF_TRIGGER_RISING |
  1033. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1034. "mbhc btn press irq", priv);
  1035. if (ret)
  1036. dev_err(dev, "cannot request mbhc button press irq\n");
  1037. irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det");
  1038. if (irq < 0)
  1039. return irq;
  1040. ret = devm_request_threaded_irq(dev, irq, NULL,
  1041. mbhc_btn_release_irq_handler,
  1042. IRQF_TRIGGER_RISING |
  1043. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1044. "mbhc btn release irq", priv);
  1045. if (ret)
  1046. dev_err(dev, "cannot request mbhc button release irq\n");
  1047. }
  1048. dev_set_drvdata(dev, priv);
  1049. return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,
  1050. pm8916_wcd_analog_dai,
  1051. ARRAY_SIZE(pm8916_wcd_analog_dai));
  1052. }
  1053. static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev)
  1054. {
  1055. struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev);
  1056. clk_disable_unprepare(priv->mclk);
  1057. return 0;
  1058. }
  1059. static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {
  1060. { .compatible = "qcom,pm8916-wcd-analog-codec", },
  1061. { }
  1062. };
  1063. MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table);
  1064. static struct platform_driver pm8916_wcd_analog_spmi_driver = {
  1065. .driver = {
  1066. .name = "qcom,pm8916-wcd-spmi-codec",
  1067. .of_match_table = pm8916_wcd_analog_spmi_match_table,
  1068. },
  1069. .probe = pm8916_wcd_analog_spmi_probe,
  1070. .remove = pm8916_wcd_analog_spmi_remove,
  1071. };
  1072. module_platform_driver(pm8916_wcd_analog_spmi_driver);
  1073. MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
  1074. MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver");
  1075. MODULE_LICENSE("GPL v2");