/drm/trunk/release/rtl/lib_rtl_rs/lib_rtl_rs/simple_chen_cell_rtl/_primary.vhd

 1library verilog;
 2use verilog.vl_types.all;
 3entity simple_chen_cell_rtl is
 4    port(
 5        clk             : in     vl_logic;
 6        rst             : in     vl_logic;
 7        clk_ena         : in     vl_logic;
 8        signal_2        : in     vl_logic;
 9        alpha2I         : in     vl_logic_vector(7 downto 0);
10        siomI           : in     vl_logic_vector(7 downto 0);
11        acc_r           : out    vl_logic_vector(7 downto 0)
12    );
13end simple_chen_cell_rtl;