PageRenderTime 15ms CodeModel.GetById 13ms app.highlight 1ms RepoModel.GetById 0ms app.codeStats 0ms

/drm/trunk/release/rtl/lib_rtl/lib_rtl/v_shift_registers/_primary.vhd

http://github.com/zaqwes8811/decoder-reed-solomon
VHDL | 15 lines | 15 code | 0 blank | 0 comment | 0 complexity | c04c83ea9f1179268be259ea89cc324a MD5 | raw file
 1library verilog;
 2use verilog.vl_types.all;
 3entity v_shift_registers is
 4    generic(
 5        DELAY           : integer := 1;
 6        WIDTH           : integer := 8
 7    );
 8    port(
 9        clk             : in     vl_logic;
10        rst             : in     vl_logic;
11        clk_ena         : in     vl_logic;
12        si              : in     vl_logic_vector;
13        so              : out    vl_logic_vector
14    );
15end v_shift_registers;