library verilog;
use verilog.vl_types.all;
entity v_shift_registers is
    generic(
        DELAY           : integer := 1;
        WIDTH           : integer := 8
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        clk_ena         : in     vl_logic;
        si              : in     vl_logic_vector;
        so              : out    vl_logic_vector
    );
end v_shift_registers;