/drm/trunk/release/rtl/lib_rtl/lib_rtl/zero_detect_owire/_primary.vhd

http://github.com/zaqwes8811/decoder-reed-solomon · VHDL · 8 lines · 8 code · 0 blank · 0 comment · 0 complexity · 4b58951526bf5d600bfacd09489abf2e MD5 · raw file

  1. library verilog;
  2. use verilog.vl_types.all;
  3. entity zero_detect_owire is
  4. port(
  5. \in\ : in vl_logic_vector(7 downto 0);
  6. \out\ : out vl_logic
  7. );
  8. end zero_detect_owire;