/drm/trunk/release/rtl/lib_rtl/lib_rtl/zero_detect_owire/_primary.vhd
http://github.com/zaqwes8811/decoder-reed-solomon · VHDL · 8 lines · 8 code · 0 blank · 0 comment · 0 complexity · 4b58951526bf5d600bfacd09489abf2e MD5 · raw file
- library verilog;
- use verilog.vl_types.all;
- entity zero_detect_owire is
- port(
- \in\ : in vl_logic_vector(7 downto 0);
- \out\ : out vl_logic
- );
- end zero_detect_owire;