/drm/trunk/release/rtl/lib_rtl/lib_rtl/register_pe/_primary.vhd

 1library verilog;
 2use verilog.vl_types.all;
 3entity register_pe is
 4    port(
 5        clk             : in     vl_logic;
 6        rst             : in     vl_logic;
 7        clk_ena         : in     vl_logic;
 8        load            : in     vl_logic;
 9        datain          : in     vl_logic_vector(7 downto 0);
10        dforload        : in     vl_logic_vector(7 downto 0);
11        dataout         : out    vl_logic_vector(7 downto 0)
12    );
13end register_pe;