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/drm/trunk/release/rtl/lib_rtl/lib_rtl/register_pe/_primary.vhd

http://github.com/zaqwes8811/decoder-reed-solomon
VHDL | 13 lines | 13 code | 0 blank | 0 comment | 0 complexity | b0c0e39c755716f51b14d281b2abd05c MD5 | raw file
 1library verilog;
 2use verilog.vl_types.all;
 3entity register_pe is
 4    port(
 5        clk             : in     vl_logic;
 6        rst             : in     vl_logic;
 7        clk_ena         : in     vl_logic;
 8        load            : in     vl_logic;
 9        datain          : in     vl_logic_vector(7 downto 0);
10        dforload        : in     vl_logic_vector(7 downto 0);
11        dataout         : out    vl_logic_vector(7 downto 0)
12    );
13end register_pe;