library verilog;
use verilog.vl_types.all;
entity register_pe is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        clk_ena         : in     vl_logic;
        load            : in     vl_logic;
        datain          : in     vl_logic_vector(7 downto 0);
        dforload        : in     vl_logic_vector(7 downto 0);
        dataout         : out    vl_logic_vector(7 downto 0)
    );
end register_pe;