/drm/trunk/release/rtl/lib_rtl/lib_rtl/rom_init_rtl/_primary.vhd

 1library verilog;
 2use verilog.vl_types.all;
 3entity rom_init_rtl is
 4    generic(
 5        DATA_WIDTH      : integer := 8;
 6        ADDR_WIDTH      : integer := 8
 7    );
 8    port(
 9        clk             : in     vl_logic;
10        clk_ena         : in     vl_logic;
11        addr_a          : in     vl_logic_vector;
12        q_a             : out    vl_logic_vector
13    );
14end rom_init_rtl;