PageRenderTime 32ms CodeModel.GetById 31ms app.highlight 0ms RepoModel.GetById 1ms app.codeStats 0ms

/drm/trunk/release/rtl/lib_rtl/lib_rtl/rom_init_rtl/_primary.vhd

http://github.com/zaqwes8811/decoder-reed-solomon
VHDL | 14 lines | 14 code | 0 blank | 0 comment | 0 complexity | 9825c6d882f5f6a0a91c69bce77695ec MD5 | raw file
 1library verilog;
 2use verilog.vl_types.all;
 3entity rom_init_rtl is
 4    generic(
 5        DATA_WIDTH      : integer := 8;
 6        ADDR_WIDTH      : integer := 8
 7    );
 8    port(
 9        clk             : in     vl_logic;
10        clk_ena         : in     vl_logic;
11        addr_a          : in     vl_logic_vector;
12        q_a             : out    vl_logic_vector
13    );
14end rom_init_rtl;