/drm/trunk/release/rtl/rtl_top/gl_rtl.v
V | 85 lines | 60 code | 5 blank | 20 comment | 0 complexity | 12900b134795022c7ddb3af2721a3e57 MD5 | raw file
1/** 2 file : gl_rtl.v 3 4 abs. : ?? ??????????? ?? ?????? ???????? 5 ?????, ????? ? ???????? ?????? ???? ?????? ???? ????????? 6 ??????????, ??????? ????? ????? ??????????. 7*/ 8 9`include "vc_top.v" 10module gl_rtl(clk, rst, // global in 11 // enabling 12 clk_ena, // global in 13 clk_ena_low, 14 // out. cont. 15 ecc_master, 16 rs_master, // 17 // stream 18 iword, oword, mask, 19 numerr, 20 // point. 21 ipointer, 22 opointer); 23 input clk, rst, clk_ena; 24 /// /// /// 25 output clk_ena_low, ecc_master, rs_master; 26 output [(`WIDTH)-1:0] iword, oword, mask; 27 output [(`DEGREE_BUS)-1+1:0] numerr; 28 output [(`WIDTH)-1:0] ipointer, opointer; 29 30 /// /// local /// /// 31 wire clk_ena_low; // ??????? ??????? 32 wire clk_ena_high; // ??????? ??????? 33 assign clk_ena_high = clk_ena; 34 35 // sinks // 36 wire rs_master; // ????????? ?????? ?? master 37 wire ecc_master; 38 wire [`DEGREE_BUS-1:0] degree; // ??????? 39 wire [`DEGREE_BUS-1+1:0] numerr; // ??????? 40 wire fail; 41 wire [`WIDTH-1:0] oword; 42 wire [`WIDTH-1:0] iword; 43 wire [`WIDTH-1:0] mask; 44 wire [`WIDTH-1:0] opointer; 45 46 /// /// connect /// /// 47 // ImiEcc // ???????? ?????? (????? ? ?????????????? ???????(???? ????? ??? 48 // ? ?????? ? ????? ...2word.v)) 49 rs_imiecc_rtl 50 rs_imiecc( 51 .clk(clk), .rst(rst), 52 .clk_ena(clk_ena_low), 53 // control /// 54 // out 55 .ecc_master(ecc_master), // ?????? ?????? ?????? 56 .addr(ipointer), 57 // stream /// 58 .iword(iword) // ???????? ????? 59 ); 60 61 /// /// DRM-decoder /// /// 62 rs_drm_rtl_top 63 label_main( 64 .clk(clk), .rst(rst), 65 .clk_ena_low(clk_ena_low), // ????????? ??????? 66 .clk_ena_high(clk_ena_high), // ????????? 67 // cont. 68 .rs_slave(ecc_master), 69 .rs_master(rs_master), 70 // stream 71 .iword(iword), 72 // 73 .oword(oword), 74 .mask(mask), 75 .numerr(numerr)); 76 counters_mod_rtl#( // LOW 77 .ADDR_MOD(4), 78 .ADDR_WIDTH(3)) 79 div_low( 80 .clk(clk), .rst(rst), .clk_ena(clk_ena), 81 .q(addr_ncare), // ??? ????? ??? 82 .carry(clk_ena_low)); 83 //* / 84 assign opointer = ipointer; 85endmodule