//
// 4-bit Signed Up Counter with Asynchronous Reset and Modulo Maximum
// counters_rtl.v
//
`define ADDR_WIDTH 9
module counters_mod_rtl(clk, clk_ena, rst, q, carry);
  parameter ADDR_MOD = 9;
  /////
  input clk, clk_ena, rst;
  output [`ADDR_WIDTH-1:0] q;
  output carry;
  
  // local //
  reg [`ADDR_WIDTH-1:0] cnt;
  reg carry_tmp;
  // logic //////
  always @ (posedge clk or posedge rst)
    begin
    if(rst)
      cnt <= 0;
    else if(clk_ena)
      cnt <= (cnt + 1)%ADDR_MOD;  // ??? ?????????? ??????? ?????????
  end
  // ????. ????? - ???????
  always @ (cnt)
    begin
    if(cnt == ADDR_MOD-1)
      carry_tmp = 'b1;
    else 
      carry_tmp = 'b0;  // ??? ?????????? ??????? ?????????
  end
  //
  assign q = cnt;
  assign carry = carry_tmp;
endmodule
// ??????? ??? ?????? ????????
module counters_mod_nocarry_rtl(clk, clk_ena, rst, q);
  parameter ADDR_MOD = 9;
  /////
  input clk, clk_ena, rst;
  output [`ADDR_WIDTH-1:0] q;
  //output carry;
  
  // local //
  reg [`ADDR_WIDTH-1:0] cnt;
  reg [`ADDR_WIDTH-1:0] cnt_tmp;
  reg carry_tmp;
  // logic //////
  always @ (posedge clk or posedge rst)
    begin
    if(rst) begin
      cnt <= 0;
	  cnt_tmp <= 0;
	end
    else if(clk_ena) begin
      cnt <= (cnt + 0)%ADDR_MOD;  // ??? ?????????? ??????? ?????????
	  cnt_tmp <= cnt;
	end
  end
  // ????. ????? - ???????
  /*always @ (cnt)
    begin
    if(cnt == ADDR_MOD-1)
      carry_tmp = 'b1;
    else 
      carry_tmp = 'b0;  // ??? ?????????? ??????? ?????????
  end*/
  //
  assign q = cnt_tmp;
  //assign carry = carry_tmp;
endmodule