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/drm/trunk/debug/subblocks/kes_pf_save/vlib_counters.v

http://github.com/zaqwes8811/decoder-reed-solomon
V | 71 lines | 51 code | 2 blank | 18 comment | 3 complexity | f8d5f00f54c9888c69a79f3d56019fa9 MD5 | raw file
 1//
 2// 4-bit Signed Up Counter with Asynchronous Reset and Modulo Maximum
 3// counters_rtl.v
 4//
 5`define ADDR_WIDTH 9
 6module counters_mod_rtl(clk, clk_ena, rst, q, carry);
 7  parameter ADDR_MOD = 9;
 8  /////
 9  input clk, clk_ena, rst;
10  output [`ADDR_WIDTH-1:0] q;
11  output carry;
12  
13  // local //
14  reg [`ADDR_WIDTH-1:0] cnt;
15  reg carry_tmp;
16  // logic //////
17  always @ (posedge clk or posedge rst)
18    begin
19    if(rst)
20      cnt <= 0;
21    else if(clk_ena)
22      cnt <= (cnt + 1)%ADDR_MOD;  // ??? ?????????? ??????? ?????????
23  end
24  // ????. ????? - ???????
25  always @ (cnt)
26    begin
27    if(cnt == ADDR_MOD-1)
28      carry_tmp = 'b1;
29    else 
30      carry_tmp = 'b0;  // ??? ?????????? ??????? ?????????
31  end
32  //
33  assign q = cnt;
34  assign carry = carry_tmp;
35endmodule
36// ??????? ??? ?????? ????????
37module counters_mod_nocarry_rtl(clk, clk_ena, rst, q);
38  parameter ADDR_MOD = 9;
39  /////
40  input clk, clk_ena, rst;
41  output [`ADDR_WIDTH-1:0] q;
42  //output carry;
43  
44  // local //
45  reg [`ADDR_WIDTH-1:0] cnt;
46  reg [`ADDR_WIDTH-1:0] cnt_tmp;
47  reg carry_tmp;
48  // logic //////
49  always @ (posedge clk or posedge rst)
50    begin
51    if(rst) begin
52      cnt <= 0;
53	  cnt_tmp <= 0;
54	end
55    else if(clk_ena) begin
56      cnt <= (cnt + 0)%ADDR_MOD;  // ??? ?????????? ??????? ?????????
57	  cnt_tmp <= cnt;
58	end
59  end
60  // ????. ????? - ???????
61  /*always @ (cnt)
62    begin
63    if(cnt == ADDR_MOD-1)
64      carry_tmp = 'b1;
65    else 
66      carry_tmp = 'b0;  // ??? ?????????? ??????? ?????????
67  end*/
68  //
69  assign q = cnt_tmp;
70  //assign carry = carry_tmp;
71endmodule