/drm/trunk/debug/lib_rtl/simple_vlog_lib/pxor_3w2w1/_primary.vhd
VHDL | 14 lines | 14 code | 0 blank | 0 comment | 0 complexity | fc9874d111065c34e8782ee786b25e15 MD5 | raw file
1library verilog; 2use verilog.vl_types.all; 3entity pxor_3w2w1 is 4 generic( 5 WIDTH : integer := 8 6 ); 7 port( 8 clk : in vl_logic; 9 rst : in vl_logic; 10 clk_ena : in vl_logic; 11 pbus_in : in vl_logic_vector; 12 busout : out vl_logic_vector 13 ); 14end pxor_3w2w1;