library verilog;
use verilog.vl_types.all;
entity pxor_3w2w1 is
    generic(
        WIDTH           : integer := 8
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        clk_ena         : in     vl_logic;
        pbus_in         : in     vl_logic_vector;
        busout          : out    vl_logic_vector
    );
end pxor_3w2w1;