/**
  file : dvbt_tb_uni.v
  
  abs. : ???????? ????? ??? ??????? ???????????
  
*/

`include "vc_top.v"
module dvbt_tb_uni;
  // stimuls //
  reg clk, rst;
  wire clk_ena;
   assign clk_ena = 1;  // ????? ???? ??? ?????????

  /// sinks ///
  wire clk_ena_low, ecc_master, rs_master;
  wire [(`WIDTH)-1:0] iword, oword, mask;
  wire [(`DEGREE_BUS)-1+1:0] numerr;
  wire [(`WIDTH)-1:0] ipointer, opointer;
  
  /// /// DUT /// ///
  gl_rtl
    DUT(
      .clk(clk), .rst(rst),  // global in
      // enabling
      .clk_ena(clk_ena),  // global in
      .clk_ena_low(clk_ena_low),
      // out. cont.
      .ecc_master(ecc_master),
      .rs_master(rs_master),  // 
      // stream
      .iword(iword), .oword(oword), .mask(mask),
      .numerr(numerr),
      // point.
	  .ipointer(ipointer),
      .opointer(opointer));
  
  /// /// ///
  initial begin 
    clk = 0;  rst = 0;
    #2; rst = 1;  #3; rst = 0;
  end
  // main clk 
  always #(`hTns) clk = ~clk;  // ???????? ????????? 
endmodule