/* 
  File : rtl_gmult.v  // ????????
  Author : Lugansky Igor
  Date : 4/03/11
  Version : 0.1
  Abstract : ??????????-????????-??????????
             ? ???€? ?????(2^WIGHT)
 
  
 Modification History:
 Date      By    Version Change Description
 gmac_rtl(
  .clk(), .clk_ena_mac(), .aclr_mac(),  
  .clk_ena_oreg(), 
  .sinp(), .minp(),  
  .gmacout()
);
 */
 
/**
  –??????? ??????€???€ ?????????, ?? ???????? ?? ?????? ????????? ???????, 
  ??????? ???????????€ ???????? ?????????€ ?????.

*/

`include "vc_top.v"
module gmac_new2_rtl( 
  clk, rst, clk_ena, signal_2, 
  alpha2I, 
  siomI,  // ?????????????? ???? 
  acc_r
);
  //parameter WIDTH = 8;  // ?????? ???
  input clk, rst, clk_ena;
  // control
  input signal_2;  // ???? ?? ?????? ?????????????
  // data
  input [`WIDTH-1:0] alpha2I;
  input [`WIDTH-1:0] siomI;  // sigma or omega i
  output[`WIDTH-1:0] acc_r;
  
  // local ////
  wire [`WIDTH-1:0] outgmult2;  // ????? ??????? ?????????€ 
  reg [`WIDTH-1:0] outmux2;  // ????? ??????? ??????????????
  reg [`WIDTH-1:0] acc_r_tmp;  // ????????????? ???????
  wire [`WIDTH-1:0] acc_r_tmp_tmp;  // ????????????? ???????
  
  // connecting //////
  // ?????????? ???????????????????????
  generate if(`WIDTH == 8) begin
    gmult8_rtl label_1( 
      .a  (acc_r),  // ????? ?????????€ 
      .b  (alpha2I),  // ??€?? ?? ????? 
      .c  (outgmult2));
    end 
  endgenerate
  
  // ???????-??????????
  a_dff #(.WIDTH(`WIDTH)) label_2(
    .clk(clk), .aclr(rst), .ena(clk_ena), 
	.data(acc_r_tmp), 
	.q(acc_r));
	
  // mux2bus->1bus
  mux2bus #(.WIDTH(`WIDTH)) label_3(
    .sel(signal_2), 
	.A0(outgmult2), 
	.A1('b0),  // ????? ???? 
	.Z(acc_r_tmp_tmp));
  // logic ///
  always @(acc_r_tmp_tmp or siomI)  // xor ?? ?????(????????)
    begin
	  acc_r_tmp = acc_r_tmp_tmp^siomI;
  end
endmodule
/*
/////////////////
module gmac_new_rtl( 
  clk, rst,
  // control
  signal_1,  // ???? ?? ?????????????
  signal_2,
  // data
  alphaI,
  alpha2I,
  siomI,  // sigma or omega i
  resultI
);
  parameter WIDTH = 8  // ?????? ???
  input clk, rst,
  // control
  input signal_1,  // ???? ?? ?????????????
  input signal_2,
  // data
  input [WIDTH-1:0] alphaI;
  input [WIDTH-1:0] alpha2I;
  input [WIDTH-1:0] siomI;  // sigma or omega i
  output reg [WIDTH-1:0] resultI;
  
  // local /////
  wire [WIDTH-1:0] outgmult1;  // ????? ??????? ?????????€
  wire [WIDTH-1:0] outgmult2;  // ???????
  reg [WIDTH-1:0] outmux1;  // ????? ??????? ??????????????
  reg [WIDTH-1:0] acc_r;  // ????????????? ???????
  reg [WIDTH-1:0] acc_r_tmp;  // ????????????? ???????
  // ?????????? ??????????
  generate if(WIDTH == 8) begin
    gmult8_rtl label_1( 
      .a  (siomI),  // ??€?? ?? ?????
      .b  (outmux1), 
      .c  (outgmult1));
    gmult8_rtl label_2( 
      .a  (acc_r),  // ????? ?????????€ 
      .b  (alpha2I),  // ??€?? ?? ????? 
      .c  (outgmult2));
    end 
  endgenerate

  // logic //////
  // mux1
  always @(signal_1  or alphaI)
    begin
    if(signal_1 == 1)  outmux1 = 1;  else
      outmux1 = alphaI;
  end
  // mux2
  always @(signal_2 or outgmult1 or outgmult2)
    begin
    if(signal_2 == 1)
      acc_r_tmp <= outgmult1;
    else
      acc_r_tmp <= outgmult2;
  end
  // acc_r
  always @(posedge clk or posedge rst)
    begin
    if(rst == 1)
      acc_r <= 'd0;
    else
      acc_r <= acc_r_tmp;  // ??????????? ????? ??????????????
  end
  always @(posedge clk)// or posedge rst)
    begin  // ???? ?????? ???????????(??? ?????????€ ? ??????)
    resultI <= acc_r;
  end
endmodule

/////// old //////////
module gmac_rtl(
  clk, clk_ena_mac, aclr_mac,  
  clk_ena_oreg, 
  sinp, minp,  
  gmacout
);
  
  input clk;
  input clk_ena_mac;  // ?????????? ?????? ????????-?????????€  
  input aclr_mac;  // ????? ?????????€(?? ??????????), ? ?????? ???
  input clk_ena_oreg;  // ?????????? ???????????€ 
  
  // data
  input [`WIGHT-1:0] sinp;  // ?????? ?????? ?? ????????
  input [`WIGHT-1:0] minp;  // ?????? ?????? ?? ??????????
  output reg [`WIGHT-1:0] gmacout;  // ????? ?????????€
  
  // variable
  reg [`WIGHT-1:0] acc_r;  // ???????€???
  wire [`WIGHT-1:0] out_gmult;  //
   
  // connect gmult
  generate if(`WIGHT == 8)
  gmult8_rtl label_1(
    .a  (acc_r), 
    .b  (minp), 
    .c  (out_gmult)); 
  endgenerate
  // logic //////////////
  // ???????? ?? ??????? ? ??????????? ?????
  always @(posedge clk or posedge aclr_mac)  
    begin : akk
	  if(aclr_mac) begin
	    acc_r <= 'b0;  // ????????? ???????€????
	  end
	  else 
	  if(clk_ena_mac) begin 
		  acc_r <= out_gmult^sinp;
		end
  end
  always @(posedge clk)  // ???????? ??????? ??????????? ?????????
    if(clk_ena_oreg) begin : store
		gmacout <= acc_r;
	end  
endmodule*/