/dvbt/trunk/debug/lib_rtl_rs/gmac_cell_lib.v
Verilog | 193 lines | 37 code | 6 blank | 150 comment | 2 complexity | ce8e2fb89eea75aaf2a3021366f6f997 MD5 | raw file
1/* 2 File : rtl_gmult.v // ???????? 3 Author : Lugansky Igor 4 Date : 4/03/11 5 Version : 0.1 6 Abstract : ??????????-????????-?????????? 7 ? ???? ?????(2^WIGHT) 8 9 10 Modification History: 11 Date By Version Change Description 12 gmac_rtl( 13 .clk(), .clk_ena_mac(), .aclr_mac(), 14 .clk_ena_oreg(), 15 .sinp(), .minp(), 16 .gmacout() 17); 18 */ 19 20/** 21 ??????? ????????? ?????????, ?? ???????? ?? ?????? ????????? ???????, 22 ??????? ??????????? ???????? ????????? ?????. 23 24*/ 25 26`include "vc_top.v" 27module gmac_new2_rtl( 28 clk, rst, clk_ena, signal_2, 29 alpha2I, 30 siomI, // ?????????????? ???? 31 acc_r 32); 33 //parameter WIDTH = 8; // ?????? ??? 34 input clk, rst, clk_ena; 35 // control 36 input signal_2; // ???? ?? ?????? ????????????? 37 // data 38 input [`WIDTH-1:0] alpha2I; 39 input [`WIDTH-1:0] siomI; // sigma or omega i 40 output[`WIDTH-1:0] acc_r; 41 42 // local //// 43 wire [`WIDTH-1:0] outgmult2; // ????? ??????? ????????? 44 reg [`WIDTH-1:0] outmux2; // ????? ??????? ?????????????? 45 reg [`WIDTH-1:0] acc_r_tmp; // ????????????? ??????? 46 wire [`WIDTH-1:0] acc_r_tmp_tmp; // ????????????? ??????? 47 48 // connecting ////// 49 // ?????????? ??????????????????????? 50 generate if(`WIDTH == 8) begin 51 gmult8_rtl label_1( 52 .a (acc_r), // ????? ????????? 53 .b (alpha2I), // ???? ?? ????? 54 .c (outgmult2)); 55 end 56 endgenerate 57 58 // ???????-?????????? 59 a_dff #(.WIDTH(`WIDTH)) label_2( 60 .clk(clk), .aclr(rst), .ena(clk_ena), 61 .data(acc_r_tmp), 62 .q(acc_r)); 63 64 // mux2bus->1bus 65 mux2bus #(.WIDTH(`WIDTH)) label_3( 66 .sel(signal_2), 67 .A0(outgmult2), 68 .A1('b0), // ????? ???? 69 .Z(acc_r_tmp_tmp)); 70 // logic /// 71 always @(acc_r_tmp_tmp or siomI) // xor ?? ?????(????????) 72 begin 73 acc_r_tmp = acc_r_tmp_tmp^siomI; 74 end 75endmodule 76/* 77///////////////// 78module gmac_new_rtl( 79 clk, rst, 80 // control 81 signal_1, // ???? ?? ????????????? 82 signal_2, 83 // data 84 alphaI, 85 alpha2I, 86 siomI, // sigma or omega i 87 resultI 88); 89 parameter WIDTH = 8 // ?????? ??? 90 input clk, rst, 91 // control 92 input signal_1, // ???? ?? ????????????? 93 input signal_2, 94 // data 95 input [WIDTH-1:0] alphaI; 96 input [WIDTH-1:0] alpha2I; 97 input [WIDTH-1:0] siomI; // sigma or omega i 98 output reg [WIDTH-1:0] resultI; 99 100 // local ///// 101 wire [WIDTH-1:0] outgmult1; // ????? ??????? ????????? 102 wire [WIDTH-1:0] outgmult2; // ??????? 103 reg [WIDTH-1:0] outmux1; // ????? ??????? ?????????????? 104 reg [WIDTH-1:0] acc_r; // ????????????? ??????? 105 reg [WIDTH-1:0] acc_r_tmp; // ????????????? ??????? 106 // ?????????? ?????????? 107 generate if(WIDTH == 8) begin 108 gmult8_rtl label_1( 109 .a (siomI), // ???? ?? ????? 110 .b (outmux1), 111 .c (outgmult1)); 112 gmult8_rtl label_2( 113 .a (acc_r), // ????? ????????? 114 .b (alpha2I), // ???? ?? ????? 115 .c (outgmult2)); 116 end 117 endgenerate 118 119 // logic ////// 120 // mux1 121 always @(signal_1 or alphaI) 122 begin 123 if(signal_1 == 1) outmux1 = 1; else 124 outmux1 = alphaI; 125 end 126 // mux2 127 always @(signal_2 or outgmult1 or outgmult2) 128 begin 129 if(signal_2 == 1) 130 acc_r_tmp <= outgmult1; 131 else 132 acc_r_tmp <= outgmult2; 133 end 134 // acc_r 135 always @(posedge clk or posedge rst) 136 begin 137 if(rst == 1) 138 acc_r <= 'd0; 139 else 140 acc_r <= acc_r_tmp; // ??????????? ????? ?????????????? 141 end 142 always @(posedge clk)// or posedge rst) 143 begin // ???? ?????? ???????????(??? ????????? ? ??????) 144 resultI <= acc_r; 145 end 146endmodule 147 148/////// old ////////// 149module gmac_rtl( 150 clk, clk_ena_mac, aclr_mac, 151 clk_ena_oreg, 152 sinp, minp, 153 gmacout 154); 155 156 input clk; 157 input clk_ena_mac; // ?????????? ?????? ????????-????????? 158 input aclr_mac; // ????? ?????????(?? ??????????), ? ?????? ??? 159 input clk_ena_oreg; // ?????????? ??????????? 160 161 // data 162 input [`WIGHT-1:0] sinp; // ?????? ?????? ?? ???????? 163 input [`WIGHT-1:0] minp; // ?????? ?????? ?? ?????????? 164 output reg [`WIGHT-1:0] gmacout; // ????? ????????? 165 166 // variable 167 reg [`WIGHT-1:0] acc_r; // ?????????? 168 wire [`WIGHT-1:0] out_gmult; // 169 170 // connect gmult 171 generate if(`WIGHT == 8) 172 gmult8_rtl label_1( 173 .a (acc_r), 174 .b (minp), 175 .c (out_gmult)); 176 endgenerate 177 // logic ////////////// 178 // ???????? ?? ??????? ? ??????????? ????? 179 always @(posedge clk or posedge aclr_mac) 180 begin : akk 181 if(aclr_mac) begin 182 acc_r <= 'b0; // ????????? ??????????? 183 end 184 else 185 if(clk_ena_mac) begin 186 acc_r <= out_gmult^sinp; 187 end 188 end 189 always @(posedge clk) // ???????? ??????? ??????????? ????????? 190 if(clk_ena_oreg) begin : store 191 gmacout <= acc_r; 192 end 193endmodule*/