/*
   stage_wrapper_rtl.v
   Abstract: ???????? ??? ????? ??? ?????????????
    
  Connect:
  stage_wrapper_rtl label_sw(
   .clk(clk), .rst(rst), .clk_ena(clk_ena),
   
   // control ///
   // slave
   .first(first),
   // master
   .last(last),
   // dataflow ///
   // in
   .pin(pin), // ???????????? ???? ?????????
   // out
   .pout(pout)
 );
 */
`include "vconst.v"
 module stage_wrapper_rtl(
   clk, rst, clk_ena,
   
   // control ///
   // slave
   first,
   windows,
   // master
   last,
   // dataflow ///
   // in
   pin, // ???????????? ???? ?????????
   pin_latch,
   // out
   pout
 );
   input clk, rst, clk_ena;
   input first;
   output windows; 
   output last;
   input [`IN_WIDTH-1:0] pin;
   output [`IN_WIDTH-1:0] pin_latch;  // ????? ???????? ????????
   output [`OUT_WIDTH-1:0] pout;
     wire [`OUT_WIDTH-1:0] pre_pout;
	 
   // local ///
   wire [`IN_WIDTH-1:0] pin_mux;  // ????? ??????????????
   wire pre_last;
   
   // connect ///
   sm_wra_control #(
    .WIDTH(`WIDTH+1), 
    .MOD_COUNT(14)
  )label_sm(  // ???? ????????
    .clk(clk), .rst(rst), .clk_ena(clk_ena),
    // control ///
    // slave
    .first(first),  // ?????????? ???????? ? ???????? ??????? ??????? ?????
    .windows(windows),
    // master
    .last(pre_last)  // ?????????? ???????? ? ???? ???????? ???????
  );
  // ????? ??????
  // ????
  a_dff #(.WIDTH(`IN_WIDTH)) label_aff_in(
     .clk(clk), .aclr(rst), .ena(windows), 
	 .data(pin_mux), 
	 .q(pin_latch));  // ?????????? ?????? ??????????
  mux2bus #(.WIDTH(`IN_WIDTH)) label_mu(  // ??????? ????????????
    .sel(first), 
	.A0(pin_latch), .A1(pin), 
	.Z(pin_mux));
  // ???????????? ?????? ?????? ???? ?????? ??????????
  ///*
  a_dff #(.WIDTH(`OUT_WIDTH)) label_aff_out(
     .clk(clk), .aclr(rst), .ena(pre_last), 
	 .data(pre_pout), 
	 .q(pout)); 
	 //* / 
   /// *
   a_dff #(.WIDTH(1)) label_aff_out_ena(
     .clk(clk), .aclr(rst), .ena(clk_ena), //pre_last), 
	 .data(pre_last), 
	 .q(last));  //* /
	 //assign last = pre_last;
   // logic ///
   assign pre_pout = 11;  // ????????? ??????????
   //assign pout = 11;  // ????????? ??????????
   //
   // output
 endmodule
 
/*
  Abstract: slave-master control
  sm_control label_sm(
    .clk(clk), .rst(rst), .clk_ena(clk_ena),
    // control ///
    // slave
    .first(first),  // ?????????? ???????? ? ???????? ??????? ??????? ?????
  
    // master
    .last(last)  // ?????????? ???????? ? ???? ???????? ???????
  );
*/
module sm_wra_control(
  clk, rst, clk_ena,
  // control ///
  // slave
  first,  // ?????????? ???????? ? ???????? ??????? ??????? ?????
  windows,
  // master
  last  // ?????????? ???????? ? ???? ???????? ???????
);
  parameter WIDTH = 8;
  parameter MOD_COUNT = 14;
  input clk, rst, clk_ena;
  input first; 
  output windows; 
  output last;
  // local ///
  wire carry;  // ??????? ????????
  wire load;  // ??????? ???????? ??????
  wire [WIDTH-1:0] dfload; 
  wire oor_ena;
  wire adf_in;  // ???? ???????????? ????????
  wire adf_out;
  // connect ///
  counter_load #(.MOD_COUNT(MOD_COUNT)) label_cl(
    .clk(clk), .rst(rst), .clk_ena(windows),//1),//adf_out),  // ????????? ??????????
    // control /// 
    .load(first),  // ????????? ??????
    // out
    .carry(carry),  // ???????? ????????
    // datastream ///
    .dfload(dfload)  // data for load
  );
  ///*
  a_dff #(.WIDTH(WIDTH)) label_aff(
    .clk(clk), .aclr(rst), .ena(oor_ena), 
    .data(adf_in), 
    .q(adf_out));  // ?????????? ?????? ??????????
     //* /
   // logic ///
   assign dfload = 0;
   assign adf_in = ~carry|first;
   assign oor_ena = first|carry;
   // outputs
   assign last = carry;
   assign windows = first|adf_out ;//|carry;
endmodule