/dvbt/trunk/debug/rtl_template/xxx_wapper_rtl.v
Verilog | 36 lines | 13 code | 8 blank | 15 comment | 0 complexity | 0a03d18540b70577c0c608350da2d669 MD5 | raw file
1 /* 2 Abstract: ???????? ??? ????? 3 ??????????? ???? 4 */ 5 `include "vconst.v" 6 module kes_wapper_rtl( 7 clk, rst, clk_ena, 8 9 // control /// 10 // slave 11 12 // master 13 14 // dataflow /// 15 // in 16 psindroms, // ???????????? ???? ????????? 17 // out 18 plambda, 19 phomega 20 ); 21 22 // 23 wire plambda 24 wire [`WIDTH-1:0] ireg_out; // ????? ???????? ???????? 25 wire [`WIDTH-1:0] ireg_out; 26 // output 27 endmodule 28 29/* 30 Abstract: slave-master control 31*/ 32module sm_control(); 33 34endmodule 35 36