/dvbt/trunk/debug/subblocks/wrapper/stage_wrapper_rtl.v
Verilog | 153 lines | 81 code | 6 blank | 66 comment | 0 complexity | e9cb02a68fcad0370314e7a2b919dc66 MD5 | raw file
1 /* 2 stage_wrapper_rtl.v 3 Abstract: ???????? ??? ????? ??? ????????????? 4 5 Connect: 6 stage_wrapper_rtl label_sw( 7 .clk(clk), .rst(rst), .clk_ena(clk_ena), 8 9 // control /// 10 // slave 11 .first(first), 12 // master 13 .last(last), 14 // dataflow /// 15 // in 16 .pin(pin), // ???????????? ???? ????????? 17 // out 18 .pout(pout) 19 ); 20 */ 21`include "vconst.v" 22 module stage_wrapper_rtl( 23 clk, rst, clk_ena, 24 25 // control /// 26 // slave 27 first, 28 windows, 29 // master 30 last, 31 // dataflow /// 32 // in 33 pin, // ???????????? ???? ????????? 34 pin_latch, 35 // out 36 pout 37 ); 38 input clk, rst, clk_ena; 39 input first; 40 output windows; 41 output last; 42 input [`IN_WIDTH-1:0] pin; 43 output [`IN_WIDTH-1:0] pin_latch; // ????? ???????? ???????? 44 output [`OUT_WIDTH-1:0] pout; 45 wire [`OUT_WIDTH-1:0] pre_pout; 46 47 // local /// 48 wire [`IN_WIDTH-1:0] pin_mux; // ????? ?????????????? 49 wire pre_last; 50 51 // connect /// 52 sm_wra_control #( 53 .WIDTH(`WIDTH+1), 54 .MOD_COUNT(24) 55 )label_sm( // ???? ???????? 56 .clk(clk), .rst(rst), .clk_ena(clk_ena), 57 // control /// 58 // slave 59 .first(first), // ?????????? ???????? ? ???????? ??????? ??????? ????? 60 .windows(windows), 61 // master 62 .last(pre_last) // ?????????? ???????? ? ???? ???????? ??????? 63 ); 64 // ????? ?????? 65 // ???? 66 a_dff #(.WIDTH(`IN_WIDTH)) label_aff_in( 67 .clk(clk), .aclr(rst), .ena(windows), 68 .data(pin_mux), 69 .q(pin_latch)); // ?????????? ?????? ?????????? 70 mux2bus #(.WIDTH(`IN_WIDTH)) label_mu( // ??????? ???????????? 71 .sel(first), 72 .A0(pin_latch), .A1(pin), 73 .Z(pin_mux)); 74 // ???????????? ?????? ?????? ???? ?????? ?????????? 75 ///* 76 a_dff #(.WIDTH(`OUT_WIDTH)) label_aff_out( 77 .clk(clk), .aclr(rst), .ena(pre_last), 78 .data(pre_pout), 79 .q(pout)); 80 //* / 81 /// * 82 a_dff #(.WIDTH(1)) label_aff_out_ena( 83 .clk(clk), .aclr(rst), .ena(clk_ena), //pre_last), 84 .data(pre_last), 85 .q(last)); //* / 86 //assign last = pre_last; 87 // logic /// 88 assign pre_pout = 11; // ????????? ?????????? 89 //assign pout = 11; // ????????? ?????????? 90 // 91 // output 92 endmodule 93 94/* 95 Abstract: slave-master control 96 sm_control label_sm( 97 .clk(clk), .rst(rst), .clk_ena(clk_ena), 98 // control /// 99 // slave 100 .first(first), // ?????????? ???????? ? ???????? ??????? ??????? ????? 101 102 // master 103 .last(last) // ?????????? ???????? ? ???? ???????? ??????? 104 ); 105*/ 106module sm_wra_control( 107 clk, rst, clk_ena, 108 // control /// 109 // slave 110 first, // ?????????? ???????? ? ???????? ??????? ??????? ????? 111 windows, 112 // master 113 last // ?????????? ???????? ? ???? ???????? ??????? 114); 115 parameter WIDTH = 8; 116 parameter MOD_COUNT = 14; 117 input clk, rst, clk_ena; 118 input first; 119 output windows; 120 output last; 121 // local /// 122 wire carry; // ??????? ???????? 123 wire load; // ??????? ???????? ?????? 124 wire [WIDTH-1:0] dfload; 125 wire oor_ena; 126 wire adf_in; // ???? ???????????? ???????? 127 wire adf_out; 128 // connect /// 129 counter_load #(.MOD_COUNT(MOD_COUNT)) label_cl( 130 .clk(clk), .rst(rst), .clk_ena(windows),//1),//adf_out), // ????????? ?????????? 131 // control /// 132 .load(first), // ????????? ?????? 133 // out 134 .carry(carry), // ???????? ???????? 135 // datastream /// 136 .dfload(dfload) // data for load 137 ); 138 ///* 139 a_dff #(.WIDTH(WIDTH)) label_aff( 140 .clk(clk), .aclr(rst), .ena(oor_ena), 141 .data(adf_in), 142 .q(adf_out)); // ?????????? ?????? ?????????? 143 //* / 144 // logic /// 145 assign dfload = 0; 146 assign adf_in = ~carry|first; 147 assign oor_ena = first|carry; 148 // outputs 149 assign last = carry; 150 assign windows = first|adf_out ;//|carry; 151endmodule 152 153