/* 
  File : csee_block_tb.v (cseeblock.v)
  Author : Lugansky Igor
  Date : 4/03/11
  Version : 0.1
  Abstract : ??????????? - ??????? ?????? ? ?????? ?????????
             ????? ???????????? ?????, ? ????? ??????????? ?? 
             ????????????, ??? ??????? ??? ???????? ??????????????
  ????????: "High-Speed Low-Complexity Reed-Solomon Decoder
  using Pipelined Berlekamp-Massey Algorithm and Its
  Folded Architecture"
  Jeong-In Park, Kihoon Lee, Chang-Seok Choi, and Hanho Lee
  
  Modification History:
  Date      By    Version Change Description

 */
 
`timescale 1 ns / 100 ps
`include "vconst.v"
module csee_block_tb;
  reg [`WIDTH*(`ST+1)-1:0] plambda;  // ??????????? ?????????? ????????
  reg [`WIDTH*(`ST)-1:0] phomega;  
  reg clk, rst;
  reg signal_2; 
  // output 
  wire [`WIDTH-1:0] lam_value;
  wire [`WIDTH-1:0] xderx_value;
  wire [`WIDTH-1:0] ome_value;
  wire [`WIDTH-1:0] pow_add_value;
  //
  integer i;  

  /*
  csee_block_rtl label_1(
  .rst(rst), .clk(clk), .clk_ena('b1), 
  .active_csee(active_csee), 
  .plambda(plambda), .phomega(phomega),
  // ????? ???? ?? ???????????
  .signal_2(signal_2),
  .lam_value(lam_value),
  .xderx_value(xderx_value),
  .ome_value(ome_value),
  .pow_add_value(pow_add_value));
  //*/
  ///*
  csee_block_rtl csee_label(
    .rst(rst), .clk(clk), .clk_ena('b1), 
	
    // control ///
    .signal_2(signal_2),
	.active_csee(1), 
	
	// dataflow  ///
	// in
	.plambda(plambda), .phomega(phomega),
	
    // out
    .lam_value(lam_value),
    .xderx_value(xderx_value),
    .ome_value(ome_value),
    .pow_add_value(pow_add_value)
  ); //*/
 
  // logic //////
  initial 
    begin
    phomega = {8'd66,  8'd157,  8'd56,  8'd57,    
               8'd56,  8'd135,  8'd85,  8'd91};

	plambda = {8'd22,  8'd21, 8'd150, 8'd202,  // 255 39 [0(5)..2_1(end)]
	           8'd133, 8'd17, 8'd250, 8'd7, 8'd54};
   // control ////
    clk = 'b0;  rst = 0;
    i = 0; // ????? ????? ????? ?????
    #0;  rst = 1;  #5;  rst = 0;
  end
  initial 
    begin
    signal_2 = 0;
    #0;   signal_2 = 1;  #70;  signal_2 = 0; 
  end
  
  // ???????? ??????
  always #50 clk = ~clk;
  // ??????? ?? ?????
  always @(posedge clk)
    begin
    i = i+1;
  end
endmodule