/dvbt/trunk/debug/subblocks/csee_old/csee_block_tb.v
Verilog | 91 lines | 43 code | 8 blank | 40 comment | 0 complexity | a4d5429ffadabad91f46b1e66678f78b MD5 | raw file
1/* 2 File : csee_block_tb.v (cseeblock.v) 3 Author : Lugansky Igor 4 Date : 4/03/11 5 Version : 0.1 6 Abstract : ??????????? - ??????? ?????? ? ?????? ????????? 7 ????? ???????????? ?????, ? ????? ??????????? ?? 8 ????????????, ??? ??????? ??? ???????? ?????????????? 9 ????????: "High-Speed Low-Complexity Reed-Solomon Decoder 10 using Pipelined Berlekamp-Massey Algorithm and Its 11 Folded Architecture" 12 Jeong-In Park, Kihoon Lee, Chang-Seok Choi, and Hanho Lee 13 14 Modification History: 15 Date By Version Change Description 16 17 */ 18 19`timescale 1 ns / 100 ps 20`include "vconst.v" 21module csee_block_tb; 22 reg [`WIDTH*(`ST+1)-1:0] plambda; // ??????????? ?????????? ???????? 23 reg [`WIDTH*(`ST)-1:0] phomega; 24 reg clk, rst; 25 reg signal_2; 26 // output 27 wire [`WIDTH-1:0] lam_value; 28 wire [`WIDTH-1:0] xderx_value; 29 wire [`WIDTH-1:0] ome_value; 30 wire [`WIDTH-1:0] pow_add_value; 31 // 32 integer i; 33 34 /* 35 csee_block_rtl label_1( 36 .rst(rst), .clk(clk), .clk_ena('b1), 37 .active_csee(active_csee), 38 .plambda(plambda), .phomega(phomega), 39 // ????? ???? ?? ??????????? 40 .signal_2(signal_2), 41 .lam_value(lam_value), 42 .xderx_value(xderx_value), 43 .ome_value(ome_value), 44 .pow_add_value(pow_add_value)); 45 //*/ 46 ///* 47 csee_block_rtl csee_label( 48 .rst(rst), .clk(clk), .clk_ena('b1), 49 50 // control /// 51 .signal_2(signal_2), 52 .active_csee(1), 53 54 // dataflow /// 55 // in 56 .plambda(plambda), .phomega(phomega), 57 58 // out 59 .lam_value(lam_value), 60 .xderx_value(xderx_value), 61 .ome_value(ome_value), 62 .pow_add_value(pow_add_value) 63 ); //*/ 64 65 // logic ////// 66 initial 67 begin 68 phomega = {8'd66, 8'd157, 8'd56, 8'd57, 69 8'd56, 8'd135, 8'd85, 8'd91}; 70 71 plambda = {8'd22, 8'd21, 8'd150, 8'd202, // 255 39 [0(5)..2_1(end)] 72 8'd133, 8'd17, 8'd250, 8'd7, 8'd54}; 73 // control //// 74 clk = 'b0; rst = 0; 75 i = 0; // ????? ????? ????? ????? 76 #0; rst = 1; #5; rst = 0; 77 end 78 initial 79 begin 80 signal_2 = 0; 81 #0; signal_2 = 1; #70; signal_2 = 0; 82 end 83 84 // ???????? ?????? 85 always #50 clk = ~clk; 86 // ??????? ?? ????? 87 always @(posedge clk) 88 begin 89 i = i+1; 90 end 91endmodule