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/dvbt/trunk/debug/subblocks/csee_old/transcript

http://github.com/zaqwes8811/decoder-reed-solomon
#! | 206 lines | 206 code | 0 blank | 0 comment | 0 complexity | ae38e28eec3c19d50f25431227fd3af5 MD5 | raw file
  1# Reading G:/usr/msim81/modelsim_ae/tcl/vsim/pref.tcl 
  2do full_csee.do
  3# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
  4# -- Compiling module csee_block_rtl
  5# -- Compiling module csee_fsm
  6# 
  7# Top level modules:
  8# 	csee_block_rtl
  9# 	csee_fsm
 10# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
 11# -- Compiling module csee_block_tb
 12# 
 13# Top level modules:
 14# 	csee_block_tb
 15# vsim -L C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib -t ns work.csee_block_tb 
 16# Loading work.csee_block_tb
 17# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 18# No such file or directory. (errno = ENOENT)
 19# Loading work.csee_block_rtl
 20# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 21# No such file or directory. (errno = ENOENT)
 22# ** Error: (vsim-3033) csee_block_rtl.v(104): Instantiation of 'a_dff' failed. The design unit was not found.
 23#         Region: /csee_block_tb/csee_label
 24#         Searched libraries:
 25# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 26# No such file or directory. (errno = ENOENT)
 27#             G:\work\ip_reed_solomon\active\rtl_csee\work
 28# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 29# No such file or directory. (errno = ENOENT)
 30# ** Error: (vsim-3033) csee_block_rtl.v(108): Instantiation of 'mux2bus' failed. The design unit was not found.
 31#         Region: /csee_block_tb/csee_label
 32#         Searched libraries:
 33# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 34# No such file or directory. (errno = ENOENT)
 35#             G:\work\ip_reed_solomon\active\rtl_csee\work
 36# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 37# No such file or directory. (errno = ENOENT)
 38# ** Error: (vsim-3033) csee_block_rtl.v(135): Instantiation of 'a_dff' failed. The design unit was not found.
 39#         Region: /csee_block_tb/csee_label
 40#         Searched libraries:
 41# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 42# No such file or directory. (errno = ENOENT)
 43#             G:\work\ip_reed_solomon\active\rtl_csee\work
 44# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 45# No such file or directory. (errno = ENOENT)
 46# ** Error: (vsim-3033) csee_block_rtl.v(148): Instantiation of 'a_dff' failed. The design unit was not found.
 47#         Region: /csee_block_tb/csee_label
 48#         Searched libraries:
 49# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 50# No such file or directory. (errno = ENOENT)
 51#             G:\work\ip_reed_solomon\active\rtl_csee\work
 52# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 53# No such file or directory. (errno = ENOENT)
 54# ** Error: (vsim-3033) csee_block_rtl.v(152): Instantiation of 'mux2bus' failed. The design unit was not found.
 55#         Region: /csee_block_tb/csee_label
 56#         Searched libraries:
 57# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 58# No such file or directory. (errno = ENOENT)
 59#             G:\work\ip_reed_solomon\active\rtl_csee\work
 60# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 61# No such file or directory. (errno = ENOENT)
 62# ** Error: (vsim-3033) csee_block_rtl.v(190): Instantiation of 'simple_chen_cell_rtl' failed. The design unit was not found.
 63#         Region: /csee_block_tb/csee_label
 64#         Searched libraries:
 65# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 66# No such file or directory. (errno = ENOENT)
 67#             G:\work\ip_reed_solomon\active\rtl_csee\work
 68# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 69# No such file or directory. (errno = ENOENT)
 70# Loading work.shifter_buses
 71# ** Warning: (vsim-3009) [TSCALE] - Module 'shifter_buses' does not have a `timescale directive in effect, but previous modules do.
 72#         Region: /csee_block_tb/csee_label/label_sh_lam
 73# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 74# No such file or directory. (errno = ENOENT)
 75# ** Error: (vsim-3033) G:/work_i/reed_solomon/reed_solomon_jh/forge/csee_block_rtl.v(280): Instantiation of 'a_dff' failed. The design unit was not found.
 76#         Region: /csee_block_tb/csee_label/label_sh_lam
 77#         Searched libraries:
 78# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 79# No such file or directory. (errno = ENOENT)
 80#             G:\work\ip_reed_solomon\active\rtl_csee\work
 81# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 82# No such file or directory. (errno = ENOENT)
 83# ** Error: (vsim-3033) G:/work_i/reed_solomon/reed_solomon_jh/forge/csee_block_rtl.v(286): Instantiation of 'a_dff' failed. The design unit was not found.
 84#         Region: /csee_block_tb/csee_label/label_sh_lam
 85#         Searched libraries:
 86# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 87# No such file or directory. (errno = ENOENT)
 88#             G:\work\ip_reed_solomon\active\rtl_csee\work
 89# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 90# No such file or directory. (errno = ENOENT)
 91# Loading work.rom_init_rtl
 92# ** Warning: (vsim-3009) [TSCALE] - Module 'rom_init_rtl' does not have a `timescale directive in effect, but previous modules do.
 93#         Region: /csee_block_tb/csee_label/label_rom
 94# ** Error: (vsim-23) Unable to change to directory path "C:/home/igorya/work/reed_solomon/active/rt_lib/veri_lib".
 95# No such file or directory. (errno = ENOENT)
 96# Loading work.zero_detect
 97# ** Warning: (vsim-3009) [TSCALE] - Module 'zero_detect' does not have a `timescale directive in effect, but previous modules do.
 98#         Region: /csee_block_tb/csee_label/lebel_zero
 99# Error loading design
100# Error: Error loading design 
101#        Pausing macro execution 
102# MACRO ./full_csee.do PAUSED at line 4
103do full_csee.do
104# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
105# -- Compiling module csee_block_rtl
106# -- Compiling module csee_fsm
107# 
108# Top level modules:
109# 	csee_block_rtl
110# 	csee_fsm
111# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
112# -- Compiling module csee_block_tb
113# 
114# Top level modules:
115# 	csee_block_tb
116# vsim -L G:/work/ip_reed_solomon/active/rt_lib/veri_lib -t ns work.csee_block_tb 
117# Loading work.csee_block_tb
118# Loading work.csee_block_rtl
119# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.a_dff
120# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.mux2bus
121# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.simple_chen_cell_rtl
122# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.shifter_buses
123# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.rom_init_rtl
124# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.zero_detect
125# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.gmult8_rtl
126# ** Warning: (vsim-3017) csee_block_tb.v(63): [TFMPC] - Too few port connections. Expected 12, found 11.
127#         Region: /csee_block_tb/csee_label
128# ** Warning: (vsim-3015) csee_block_tb.v(63): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'clk_ena'.
129#         Region: /csee_block_tb/csee_label
130# ** Warning: (vsim-3015) csee_block_tb.v(63): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'active_csee'.
131#         Region: /csee_block_tb/csee_label
132# ** Warning: (vsim-3015) csee_block_rtl.v(190): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'alpha2I'.
133#         Region: /csee_block_tb/csee_label/label_add_mult
134# ** Warning: (vsim-3015) csee_block_rtl.v(190): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'siomI'.
135#         Region: /csee_block_tb/csee_label/label_add_mult
136# ** Error: No Design Loaded!
137# Error in macro ./full_csee.do line 17
138# No Design Loaded!
139#     while executing
140# "run 4500"
141do full_csee.do
142# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
143# -- Compiling module csee_block_rtl
144# -- Compiling module csee_fsm
145# 
146# Top level modules:
147# 	csee_block_rtl
148# 	csee_fsm
149# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
150# -- Compiling module csee_block_tb
151# 
152# Top level modules:
153# 	csee_block_tb
154# vsim -L G:/work/ip_reed_solomon/active/rt_lib/veri_lib -t ns work.csee_block_tb 
155# Loading work.csee_block_tb
156# Loading work.csee_block_rtl
157# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.a_dff
158# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.mux2bus
159# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.simple_chen_cell_rtl
160# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.shifter_buses
161# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.rom_init_rtl
162# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.zero_detect
163# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.gmult8_rtl
164# ** Warning: (vsim-3017) csee_block_tb.v(63): [TFMPC] - Too few port connections. Expected 12, found 11.
165#         Region: /csee_block_tb/csee_label
166# ** Warning: (vsim-3015) csee_block_tb.v(63): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'clk_ena'.
167#         Region: /csee_block_tb/csee_label
168# ** Warning: (vsim-3015) csee_block_tb.v(63): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'active_csee'.
169#         Region: /csee_block_tb/csee_label
170# ** Warning: (vsim-3015) csee_block_rtl.v(190): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'alpha2I'.
171#         Region: /csee_block_tb/csee_label/label_add_mult
172# ** Warning: (vsim-3015) csee_block_rtl.v(190): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'siomI'.
173#         Region: /csee_block_tb/csee_label/label_add_mult
174do full_csee.do
175# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
176# -- Compiling module csee_block_rtl
177# -- Compiling module csee_fsm
178# 
179# Top level modules:
180# 	csee_block_rtl
181# 	csee_fsm
182# Model Technology ModelSim ALTERA vlog 6.3g_p1 Compiler 2008.08 Aug 13 2008
183# -- Compiling module csee_block_tb
184# 
185# Top level modules:
186# 	csee_block_tb
187# vsim -L G:/work/ip_reed_solomon/active/rt_lib/veri_lib -t ns work.csee_block_tb 
188# Loading work.csee_block_tb
189# Loading work.csee_block_rtl
190# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.a_dff
191# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.mux2bus
192# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.simple_chen_cell_rtl
193# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.shifter_buses
194# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.rom_init_rtl
195# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.zero_detect
196# Loading G:/work/ip_reed_solomon/active/rt_lib/veri_lib.gmult8_rtl
197# ** Warning: (vsim-3017) csee_block_tb.v(63): [TFMPC] - Too few port connections. Expected 12, found 11.
198#         Region: /csee_block_tb/csee_label
199# ** Warning: (vsim-3015) csee_block_tb.v(63): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'clk_ena'.
200#         Region: /csee_block_tb/csee_label
201# ** Warning: (vsim-3015) csee_block_tb.v(63): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'active_csee'.
202#         Region: /csee_block_tb/csee_label
203# ** Warning: (vsim-3015) csee_block_rtl.v(190): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'alpha2I'.
204#         Region: /csee_block_tb/csee_label/label_add_mult
205# ** Warning: (vsim-3015) csee_block_rtl.v(190): [PCDPC] - Port size (8 or 8) does not match connection size (32) for port 'siomI'.
206#         Region: /csee_block_tb/csee_label/label_add_mult