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/src/testbench_txrx.vhdl

http://github.com/whois/ece446_project
VHDL | 92 lines | 68 code | 12 blank | 12 comment | 6 complexity | af840944657bb870a5c6c5f0d22e9dae MD5 | raw file
 1---------------------------------------------------------------------------
 2-- Author(s)   : Jay Mundrawala <mundra@ir.iit.edu>
 3-- 
 4-- File          : testbench_txrx.vhdl
 5-- Creation Date : 13/11/2009
 6-- Description: 
 7--
 8---------------------------------------------------------------------------
 9
10library IEEE;
11use IEEE.STD_LOGIC_1164.ALL;
12use IEEE.numeric_std.all;
13
14---------------------------------------------------------------------------
15Entity testbench_txrx is 
16---------------------------------------------------------------------------
17end entity;
18
19
20---------------------------------------------------------------------------
21Architecture testbench_txrx_1 of testbench_txrx is
22---------------------------------------------------------------------------
23    constant T_R : time := 10 ns;
24    constant T_T : time := 160 ns;
25    signal clk_r, clk_t, start, rdy_t, rdy_r, ferr : std_logic;
26    signal rx_d : std_logic := '1';
27    signal data : std_logic_vector(7 downto 0);
28    signal data_in : std_logic_vector(7 downto 0);
29begin
30    DUT0: entity work.receiver
31    port map(
32        clk   => clk_r,
33        rx_d  => rx_d,
34        reset => '0',
35
36        data  => data,
37        rdy   => rdy_r,
38        ferr  => ferr
39    );
40
41    DUT1: entity work.transmitter
42    port map(
43        clk   => clk_t,
44        start => start,
45        data  => data_in,
46        reset => '0',
47
48        tx_d  => rx_d,
49        rdy   => rdy_t 
50    );
51
52
53    process
54    begin
55        clk_r <= '0';
56        wait for T_R/2;
57        clk_r <= '1';
58        wait for T_R/2;
59    end process;
60    process
61    begin
62        clk_t <= '0';
63        wait for T_T/2;
64        clk_t <= '1';
65        wait for T_T/2;
66    end process;
67
68    process
69    begin
70        start <= '0';
71        data_in <= X"99";
72        wait for T_R*2;
73        start <= '1';
74        assert rdy_t = '1'
75            report "rdy_t changed too fast...the following TB will not work"
76            severity failure;
77        wait until rdy_t = '0';
78        wait until rdy_t = '1';
79        wait until rdy_r = '1' or ferr ='1';
80        assert ferr = '0'
81            report "Framing Error...Data will probably be bad"
82            severity error;
83        assert data = data_in
84            report "Data != Data_in"
85            severity error;
86        assert false
87            report "End of Simulation"
88            severity failure;
89    end process;
90	
91end architecture testbench_txrx_1;
92