/src/top.vhdl
VHDL | 86 lines | 63 code | 11 blank | 12 comment | 1 complexity | 5898cf596a816d4f0d0477474d1101d3 MD5 | raw file
1--------------------------------------------------------------------------- 2-- Author(s) : Jay Mundrawala <mundra@ir.iit.edu> 3-- 4-- File : top.vhdl 5-- Creation Date : 13/11/2009 6-- Description: 7-- 8--------------------------------------------------------------------------- 9 10library IEEE; 11use IEEE.STD_LOGIC_1164.ALL; 12use IEEE.numeric_std.all; 13 14--------------------------------------------------------------------------- 15Entity top is 16--------------------------------------------------------------------------- 17 port( 18 clk : in std_logic; 19 start : in std_logic; 20 data_in : in std_logic_vector(7 downto 0); 21 rx_data : out std_logic_vector(7 downto 0); 22 rx_d : in std_logic; 23 tx_d : out std_logic; 24 rdy_r : out std_logic; 25 rx_ferr: out std_logic; 26 rdy_t : out std_logic; 27 s : in std_logic; 28 reset : in std_logic 29 ); 30end entity; 31 32 33--------------------------------------------------------------------------- 34Architecture top_1 of top is 35--------------------------------------------------------------------------- 36 signal clk_rx : std_logic; 37 signal clk_tx : std_logic; 38 signal clk_1 : std_logic; 39 signal clk_10 : std_logic; 40 signal clk_16 : std_logic; 41 signal clk_160 : std_logic; 42begin 43 DUT0: entity work.receiver 44 port map( 45 clk => clk_rx, 46 rx_d => rx_d, 47 reset => reset, 48 49 data => rx_data, 50 rdy => rdy_r, 51 ferr => rx_ferr 52 ); 53 54 DUT1: entity work.transmitter 55 port map( 56 clk => clk_tx, 57 start => start, 58 data => data_in, 59 reset => reset, 60 61 tx_d => tx_d, 62 rdy => rdy_t 63 ); 64 65 CDIV: entity work.clock_gen 66 port map( 67 clk => clk, 68 out_clk1 => clk_1, 69 out_clk10 => clk_10, 70 out_clk16 => clk_16, 71 out_clk160 => clk_160 72 ); 73 74 process(s,clk_16,clk_1,clk_10,clk_160) 75 begin 76 if(s = '0') then 77 clk_rx <= clk_16; 78 clk_tx <= clk_1; 79 else 80 clk_rx <= clk_160; 81 clk_tx <= clk_10; 82 end if; 83 end process; 84 85end architecture top_1; 86