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/arch/arm/mach-msm/platsmp.c

https://github.com/AICP/kernel_asus_grouper
C | 173 lines | 89 code | 28 blank | 56 comment | 11 complexity | 8f3bda7f52591ef57f74b31f00fe0931 MD5 | raw file
  1/*
  2 *  Copyright (C) 2002 ARM Ltd.
  3 *  All Rights Reserved
  4 *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10
 11#include <linux/init.h>
 12#include <linux/errno.h>
 13#include <linux/delay.h>
 14#include <linux/device.h>
 15#include <linux/jiffies.h>
 16#include <linux/smp.h>
 17#include <linux/io.h>
 18
 19#include <asm/hardware/gic.h>
 20#include <asm/cacheflush.h>
 21#include <asm/cputype.h>
 22#include <asm/mach-types.h>
 23
 24#include <mach/msm_iomap.h>
 25
 26#include "scm-boot.h"
 27
 28#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
 29#define SCSS_CPU1CORE_RESET 0xD80
 30#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
 31
 32/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
 33#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
 34
 35extern void msm_secondary_startup(void);
 36/*
 37 * control for which core is the next to come out of the secondary
 38 * boot "holding pen".
 39 */
 40volatile int pen_release = -1;
 41
 42static DEFINE_SPINLOCK(boot_lock);
 43
 44static inline int get_core_count(void)
 45{
 46	/* 1 + the PART[1:0] field of MIDR */
 47	return ((read_cpuid_id() >> 4) & 3) + 1;
 48}
 49
 50void __cpuinit platform_secondary_init(unsigned int cpu)
 51{
 52	/* Configure edge-triggered PPIs */
 53	writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
 54
 55	/*
 56	 * if any interrupts are already enabled for the primary
 57	 * core (e.g. timer irq), then they will not have been enabled
 58	 * for us: do so
 59	 */
 60	gic_secondary_init(0);
 61
 62	/*
 63	 * let the primary processor know we're out of the
 64	 * pen, then head off into the C entry point
 65	 */
 66	pen_release = -1;
 67	smp_wmb();
 68
 69	/*
 70	 * Synchronise with the boot thread.
 71	 */
 72	spin_lock(&boot_lock);
 73	spin_unlock(&boot_lock);
 74}
 75
 76static __cpuinit void prepare_cold_cpu(unsigned int cpu)
 77{
 78	int ret;
 79	ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
 80				SCM_FLAG_COLDBOOT_CPU1);
 81	if (ret == 0) {
 82		void *sc1_base_ptr;
 83		sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
 84		if (sc1_base_ptr) {
 85			writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
 86			writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
 87			writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
 88			iounmap(sc1_base_ptr);
 89		}
 90	} else
 91		printk(KERN_DEBUG "Failed to set secondary core boot "
 92				  "address\n");
 93}
 94
 95int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 96{
 97	unsigned long timeout;
 98	static int cold_boot_done;
 99
100	/* Only need to bring cpu out of reset this way once */
101	if (cold_boot_done == false) {
102		prepare_cold_cpu(cpu);
103		cold_boot_done = true;
104	}
105
106	/*
107	 * set synchronisation state between this boot processor
108	 * and the secondary one
109	 */
110	spin_lock(&boot_lock);
111
112	/*
113	 * The secondary processor is waiting to be released from
114	 * the holding pen - release it, then wait for it to flag
115	 * that it has been released by resetting pen_release.
116	 *
117	 * Note that "pen_release" is the hardware CPU ID, whereas
118	 * "cpu" is Linux's internal ID.
119	 */
120	pen_release = cpu;
121	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
122	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
123
124	/*
125	 * Send the secondary CPU a soft interrupt, thereby causing
126	 * the boot monitor to read the system wide flags register,
127	 * and branch to the address found there.
128	 */
129	gic_raise_softirq(cpumask_of(cpu), 1);
130
131	timeout = jiffies + (1 * HZ);
132	while (time_before(jiffies, timeout)) {
133		smp_rmb();
134		if (pen_release == -1)
135			break;
136
137		udelay(10);
138	}
139
140	/*
141	 * now the secondary core is starting up let it run its
142	 * calibrations, then wait for it to finish
143	 */
144	spin_unlock(&boot_lock);
145
146	return pen_release != -1 ? -ENOSYS : 0;
147}
148
149/*
150 * Initialise the CPU possible map early - this describes the CPUs
151 * which may be present or become present in the system. The msm8x60
152 * does not support the ARM SCU, so just set the possible cpu mask to
153 * NR_CPUS.
154 */
155void __init smp_init_cpus(void)
156{
157	unsigned int i, ncores = get_core_count();
158
159	if (ncores > nr_cpu_ids) {
160		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
161			ncores, nr_cpu_ids);
162		ncores = nr_cpu_ids;
163	}
164
165	for (i = 0; i < ncores; i++)
166		set_cpu_possible(i, true);
167
168        set_smp_cross_call(gic_raise_softirq);
169}
170
171void __init platform_smp_prepare_cpus(unsigned int max_cpus)
172{
173}