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/arch/parisc/include/asm/superio.h

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
C Header | 85 lines | 56 code | 15 blank | 14 comment | 7 complexity | 26e4b9d7a4226165da46a605eae0de29 MD5 | raw file
 1#ifndef _PARISC_SUPERIO_H
 2#define _PARISC_SUPERIO_H
 3
 4#define IC_PIC1    0x20		/* PCI I/O address of master 8259 */
 5#define IC_PIC2    0xA0		/* PCI I/O address of slave */
 6
 7/* Config Space Offsets to configuration and base address registers */
 8#define SIO_CR     0x5A		/* Configuration Register */
 9#define SIO_ACPIBAR 0x88	/* ACPI BAR */
10#define SIO_FDCBAR 0x90		/* Floppy Disk Controller BAR */
11#define SIO_SP1BAR 0x94		/* Serial 1 BAR */
12#define SIO_SP2BAR 0x98		/* Serial 2 BAR */
13#define SIO_PPBAR  0x9C		/* Parallel BAR */
14
15#define TRIGGER_1  0x67		/* Edge/level trigger register 1 */
16#define TRIGGER_2  0x68		/* Edge/level trigger register 2 */
17
18/* Interrupt Routing Control registers */
19#define CFG_IR_SER    0x69	/* Serial 1 [0:3] and Serial 2 [4:7] */
20#define CFG_IR_PFD    0x6a	/* Parallel [0:3] and Floppy [4:7] */
21#define CFG_IR_IDE    0x6b	/* IDE1     [0:3] and IDE2 [4:7] */
22#define CFG_IR_INTAB  0x6c	/* PCI INTA [0:3] and INT B [4:7] */
23#define CFG_IR_INTCD  0x6d	/* PCI INTC [0:3] and INT D [4:7] */
24#define CFG_IR_PS2    0x6e	/* PS/2 KBINT [0:3] and Mouse [4:7] */
25#define CFG_IR_FXBUS  0x6f	/* FXIRQ[0] [0:3] and FXIRQ[1] [4:7] */
26#define CFG_IR_USB    0x70	/* FXIRQ[2] [0:3] and USB [4:7] */
27#define CFG_IR_ACPI   0x71	/* ACPI SCI [0:3] and reserved [4:7] */
28
29#define CFG_IR_LOW     CFG_IR_SER	/* Lowest interrupt routing reg */
30#define CFG_IR_HIGH    CFG_IR_ACPI	/* Highest interrupt routing reg */
31
32/* 8259 operational control words */
33#define OCW2_EOI   0x20		/* Non-specific EOI */
34#define OCW2_SEOI  0x60		/* Specific EOI */
35#define OCW3_IIR   0x0A		/* Read request register */
36#define OCW3_ISR   0x0B		/* Read service register */
37#define OCW3_POLL  0x0C		/* Poll the PIC for an interrupt vector */
38
39/* Interrupt lines. Only PIC1 is used */
40#define USB_IRQ    1		/* USB */
41#define SP1_IRQ    3		/* Serial port 1 */
42#define SP2_IRQ    4		/* Serial port 2 */
43#define PAR_IRQ    5		/* Parallel port */
44#define FDC_IRQ    6		/* Floppy controller */
45#define IDE_IRQ    7		/* IDE (pri+sec) */
46
47/* ACPI registers */
48#define USB_REG_CR	0x1f	/* USB Regulator Control Register */
49
50#define SUPERIO_NIRQS   8
51
52struct superio_device {
53	u32 fdc_base;
54	u32 sp1_base;
55	u32 sp2_base;
56	u32 pp_base;
57	u32 acpi_base;
58	int suckyio_irq_enabled;
59	struct pci_dev *lio_pdev;       /* pci device for legacy IO (fn 1) */
60	struct pci_dev *usb_pdev;       /* pci device for USB (fn 2) */
61};
62
63/*
64 * Does NS make a 87415 based plug in PCI card? If so, because of this
65 * macro we currently don't support it being plugged into a machine
66 * that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
67 *
68 * This could be fixed by checking to see if function 1 exists, and
69 * if it is SuperIO Legacy IO; but really now, is this combination
70 * going to EVER happen?
71 */
72
73#define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
74#define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
75#define SUPERIO_USB_FN 2 /* Function number of USB controller */
76
77#define is_superio_device(x) \
78	(((x)->vendor == PCI_VENDOR_ID_NS) && \
79	(  ((x)->device == PCI_DEVICE_ID_NS_87415) \
80	|| ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
81	|| ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )
82
83extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */
84
85#endif /* _PARISC_SUPERIO_H */