PageRenderTime 24ms CodeModel.GetById 12ms app.highlight 9ms RepoModel.GetById 1ms app.codeStats 1ms

/arch/arm/mach-exynos/clock-exynos4212.c

https://github.com/AICP/kernel_google_msm
C | 119 lines | 81 code | 24 blank | 14 comment | 1 complexity | bf4844bbe6a7ad7cbade700882569a67 MD5 | raw file
  1/*
  2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  3 *		http://www.samsung.com
  4 *
  5 * EXYNOS4212 - Clock support
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License version 2 as
  9 * published by the Free Software Foundation.
 10*/
 11
 12#include <linux/kernel.h>
 13#include <linux/err.h>
 14#include <linux/clk.h>
 15#include <linux/io.h>
 16#include <linux/syscore_ops.h>
 17
 18#include <plat/cpu-freq.h>
 19#include <plat/clock.h>
 20#include <plat/cpu.h>
 21#include <plat/pll.h>
 22#include <plat/s5p-clock.h>
 23#include <plat/clock-clksrc.h>
 24#include <plat/pm.h>
 25
 26#include <mach/hardware.h>
 27#include <mach/map.h>
 28#include <mach/regs-clock.h>
 29
 30#include "common.h"
 31#include "clock-exynos4.h"
 32
 33#ifdef CONFIG_PM_SLEEP
 34static struct sleep_save exynos4212_clock_save[] = {
 35	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
 36	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
 37	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
 38	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
 39};
 40#endif
 41
 42static struct clk *clk_src_mpll_user_list[] = {
 43	[0] = &clk_fin_mpll,
 44	[1] = &exynos4_clk_mout_mpll.clk,
 45};
 46
 47static struct clksrc_sources clk_src_mpll_user = {
 48	.sources	= clk_src_mpll_user_list,
 49	.nr_sources	= ARRAY_SIZE(clk_src_mpll_user_list),
 50};
 51
 52static struct clksrc_clk clk_mout_mpll_user = {
 53	.clk = {
 54		.name		= "mout_mpll_user",
 55	},
 56	.sources	= &clk_src_mpll_user,
 57	.reg_src	= { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 58};
 59
 60static struct clksrc_clk *sysclks[] = {
 61	&clk_mout_mpll_user,
 62};
 63
 64static struct clksrc_clk clksrcs[] = {
 65	/* nothing here yet */
 66};
 67
 68static struct clk init_clocks_off[] = {
 69	/* nothing here yet */
 70};
 71
 72#ifdef CONFIG_PM_SLEEP
 73static int exynos4212_clock_suspend(void)
 74{
 75	s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
 76
 77	return 0;
 78}
 79
 80static void exynos4212_clock_resume(void)
 81{
 82	s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
 83}
 84
 85#else
 86#define exynos4212_clock_suspend NULL
 87#define exynos4212_clock_resume NULL
 88#endif
 89
 90static struct syscore_ops exynos4212_clock_syscore_ops = {
 91	.suspend	= exynos4212_clock_suspend,
 92	.resume		= exynos4212_clock_resume,
 93};
 94
 95void __init exynos4212_register_clocks(void)
 96{
 97	int ptr;
 98
 99	/* usbphy1 is removed */
100	exynos4_clkset_group_list[4] = NULL;
101
102	/* mout_mpll_user is used */
103	exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
104	exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
105
106	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
107	exynos4_clk_mout_mpll.reg_src.shift = 12;
108	exynos4_clk_mout_mpll.reg_src.size = 1;
109
110	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
111		s3c_register_clksrc(sysclks[ptr], 1);
112
113	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
114
115	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
116	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
117
118	register_syscore_ops(&exynos4212_clock_syscore_ops);
119}