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/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h

https://github.com/AICP/kernel_asus_grouper
C Header | 137 lines | 73 code | 32 blank | 32 comment | 3 complexity | 2e57b9ccce44a9c089ef76a5e027f60a MD5 | raw file
  1/*
  2 * Copyright (C) 2007 Google, Inc.
  3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
  4 * Author: Brian Swetland <swetland@google.com>
  5 *
  6 * This software is licensed under the terms of the GNU General Public
  7 * License version 2, as published by the Free Software Foundation, and
  8 * may be copied, distributed, and modified under those terms.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 *
 15 *
 16 * The MSM peripherals are spread all over across 768MB of physical
 17 * space, which makes just having a simple IO_ADDRESS macro to slide
 18 * them into the right virtual location rough.  Instead, we will
 19 * provide a master phys->virt mapping for peripherals here.
 20 *
 21 */
 22
 23#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
 24#define __ASM_ARCH_MSM_IOMAP_8X50_H
 25
 26/* Physical base address and size of peripherals.
 27 * Ordered by the virtual base addresses they will be mapped at.
 28 *
 29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
 30 * instruction, otherwise entry-macro.S will not compile.
 31 *
 32 * If you add or remove entries here, you'll want to edit the
 33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
 34 * changes.
 35 *
 36 */
 37
 38#define MSM_VIC_BASE          IOMEM(0xE0000000)
 39#define MSM_VIC_PHYS          0xAC000000
 40#define MSM_VIC_SIZE          SZ_4K
 41
 42#define QSD8X50_CSR_PHYS      0xAC100000
 43#define QSD8X50_CSR_SIZE      SZ_4K
 44
 45#define MSM_DMOV_BASE         IOMEM(0xE0002000)
 46#define MSM_DMOV_PHYS         0xA9700000
 47#define MSM_DMOV_SIZE         SZ_4K
 48
 49#define QSD8X50_GPIO1_PHYS        0xA9000000
 50#define QSD8X50_GPIO1_SIZE        SZ_4K
 51
 52#define QSD8X50_GPIO2_PHYS        0xA9100000
 53#define QSD8X50_GPIO2_SIZE        SZ_4K
 54
 55#define MSM_CLK_CTL_BASE      IOMEM(0xE0005000)
 56#define MSM_CLK_CTL_PHYS      0xA8600000
 57#define MSM_CLK_CTL_SIZE      SZ_4K
 58
 59#define MSM_SIRC_BASE         IOMEM(0xE1006000)
 60#define MSM_SIRC_PHYS         0xAC200000
 61#define MSM_SIRC_SIZE         SZ_4K
 62
 63#define MSM_SCPLL_BASE        IOMEM(0xE1007000)
 64#define MSM_SCPLL_PHYS        0xA8800000
 65#define MSM_SCPLL_SIZE        SZ_4K
 66
 67#ifdef CONFIG_MSM_SOC_REV_A
 68#define MSM_SMI_BASE 0xE0000000
 69#else
 70#define MSM_SMI_BASE 0x00000000
 71#endif
 72
 73#define MSM_SHARED_RAM_BASE   IOMEM(0xE0100000)
 74#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
 75#define MSM_SHARED_RAM_SIZE   SZ_1M
 76
 77#define MSM_UART1_PHYS        0xA9A00000
 78#define MSM_UART1_SIZE        SZ_4K
 79
 80#define MSM_UART2_PHYS        0xA9B00000
 81#define MSM_UART2_SIZE        SZ_4K
 82
 83#define MSM_UART3_PHYS        0xA9C00000
 84#define MSM_UART3_SIZE        SZ_4K
 85
 86#ifdef CONFIG_MSM_DEBUG_UART
 87#define MSM_DEBUG_UART_BASE   0xE1000000
 88#if CONFIG_MSM_DEBUG_UART == 1
 89#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
 90#elif CONFIG_MSM_DEBUG_UART == 2
 91#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
 92#elif CONFIG_MSM_DEBUG_UART == 3
 93#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
 94#endif
 95#define MSM_DEBUG_UART_SIZE   SZ_4K
 96#endif
 97
 98#define MSM_MDC_BASE	      IOMEM(0xE0200000)
 99#define MSM_MDC_PHYS	      0xAA500000
100#define MSM_MDC_SIZE	      SZ_1M
101
102#define MSM_AD5_BASE          IOMEM(0xE0300000)
103#define MSM_AD5_PHYS          0xAC000000
104#define MSM_AD5_SIZE          (SZ_1M*13)
105
106
107#define MSM_I2C_SIZE          SZ_4K
108#define MSM_I2C_PHYS          0xA9900000
109
110#define MSM_HSUSB_PHYS        0xA0800000
111#define MSM_HSUSB_SIZE        SZ_1K
112
113#define MSM_NAND_PHYS           0xA0A00000
114
115
116#define MSM_TSIF_PHYS        (0xa0100000)
117#define MSM_TSIF_SIZE        (0x200)
118
119#define MSM_TSSC_PHYS         0xAA300000
120
121#define MSM_UART1DM_PHYS      0xA0200000
122#define MSM_UART2DM_PHYS      0xA0900000
123
124
125#define MSM_SDC1_PHYS          0xA0300000
126#define MSM_SDC1_SIZE          SZ_4K
127
128#define MSM_SDC2_PHYS          0xA0400000
129#define MSM_SDC2_SIZE          SZ_4K
130
131#define MSM_SDC3_PHYS          0xA0500000
132#define MSM_SDC3_SIZE           SZ_4K
133
134#define MSM_SDC4_PHYS          0xA0600000
135#define MSM_SDC4_SIZE          SZ_4K
136
137#endif