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/include/linux/sc26198.h

https://github.com/airy09/android_kernel_sony_apq8064
C Header | 533 lines | 321 code | 75 blank | 137 comment | 0 complexity | 7377dc6fcc7da071645f5f5b1b3e0adb MD5 | raw file
  1/*****************************************************************************/
  2
  3/*
  4 *	sc26198.h  -- SC26198 UART hardware info.
  5 *
  6 *	Copyright (C) 1995-1998  Stallion Technologies
  7 *
  8 *	This program is free software; you can redistribute it and/or modify
  9 *	it under the terms of the GNU General Public License as published by
 10 *	the Free Software Foundation; either version 2 of the License, or
 11 *	(at your option) any later version.
 12 *
 13 *	This program is distributed in the hope that it will be useful,
 14 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 15 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 16 *	GNU General Public License for more details.
 17 *
 18 *	You should have received a copy of the GNU General Public License
 19 *	along with this program; if not, write to the Free Software
 20 *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21 */
 22
 23/*****************************************************************************/
 24#ifndef	_SC26198_H
 25#define	_SC26198_H
 26/*****************************************************************************/
 27
 28/*
 29 *	Define the number of async ports per sc26198 uart device.
 30 */
 31#define	SC26198_PORTS		8
 32
 33/*
 34 *	Baud rate timing clocks. All derived from a master 14.7456 MHz clock.
 35 */
 36#define	SC26198_MASTERCLOCK	14745600L
 37#define	SC26198_DCLK		(SC26198_MASTERCLOCK)
 38#define	SC26198_CCLK		(SC26198_MASTERCLOCK / 2)
 39#define	SC26198_BCLK		(SC26198_MASTERCLOCK / 4)
 40
 41/*
 42 *	Define internal FIFO sizes for the 26198 ports.
 43 */
 44#define	SC26198_TXFIFOSIZE	16
 45#define	SC26198_RXFIFOSIZE	16
 46
 47/*****************************************************************************/
 48
 49/*
 50 *	Global register definitions. These registers are global to each 26198
 51 *	device, not specific ports on it.
 52 */
 53#define	TSTR		0x0d
 54#define	GCCR		0x0f
 55#define	ICR		0x1b
 56#define	WDTRCR		0x1d
 57#define	IVR		0x1f
 58#define	BRGTRUA		0x84
 59#define	GPOSR		0x87
 60#define	GPOC		0x8b
 61#define	UCIR		0x8c
 62#define	CIR		0x8c
 63#define	BRGTRUB		0x8d
 64#define	GRXFIFO		0x8e
 65#define	GTXFIFO		0x8e
 66#define	GCCR2		0x8f
 67#define	BRGTRLA		0x94
 68#define	GPOR		0x97
 69#define	GPOD		0x9b
 70#define	BRGTCR		0x9c
 71#define	GICR		0x9c
 72#define	BRGTRLB		0x9d
 73#define	GIBCR		0x9d
 74#define	GITR		0x9f
 75
 76/*
 77 *	Per port channel registers. These are the register offsets within
 78 *	the port address space, so need to have the port address (0 to 7)
 79 *	inserted in bit positions 4:6.
 80 */
 81#define	MR0		0x00
 82#define	MR1		0x01
 83#define	IOPCR		0x02
 84#define	BCRBRK		0x03
 85#define	BCRCOS		0x04
 86#define	BCRX		0x06
 87#define	BCRA		0x07
 88#define	XONCR		0x08
 89#define	XOFFCR		0x09
 90#define	ARCR		0x0a
 91#define	RXCSR		0x0c
 92#define	TXCSR		0x0e
 93#define	MR2		0x80
 94#define	SR		0x81
 95#define SCCR		0x81
 96#define	ISR		0x82
 97#define	IMR		0x82
 98#define	TXFIFO		0x83
 99#define	RXFIFO		0x83
100#define	IPR		0x84
101#define	IOPIOR		0x85
102#define	XISR		0x86
103
104/*
105 *	For any given port calculate the address to use to access a specified
106 *	register. This is only used for unusual access, mostly this is done
107 *	through the assembler access routines.
108 */
109#define	SC26198_PORTREG(port,reg)	((((port) & 0x07) << 4) | (reg))
110
111/*****************************************************************************/
112
113/*
114 *	Global configuration control register bit definitions.
115 */
116#define	GCCR_NOACK		0x00
117#define	GCCR_IVRACK		0x02
118#define	GCCR_IVRCHANACK		0x04
119#define	GCCR_IVRTYPCHANACK	0x06
120#define	GCCR_ASYNCCYCLE		0x00
121#define	GCCR_SYNCCYCLE		0x40
122
123/*****************************************************************************/
124
125/*
126 *	Mode register 0 bit definitions.
127 */
128#define	MR0_ADDRNONE		0x00
129#define	MR0_AUTOWAKE		0x01
130#define	MR0_AUTODOZE		0x02
131#define	MR0_AUTOWAKEDOZE	0x03
132#define	MR0_SWFNONE		0x00
133#define	MR0_SWFTX		0x04
134#define	MR0_SWFRX		0x08
135#define	MR0_SWFRXTX		0x0c
136#define	MR0_TXMASK		0x30
137#define	MR0_TXEMPTY		0x00
138#define	MR0_TXHIGH		0x10
139#define	MR0_TXHALF		0x20
140#define	MR0_TXRDY		0x00
141#define	MR0_ADDRNT		0x00
142#define	MR0_ADDRT		0x40
143#define	MR0_SWFNT		0x00
144#define	MR0_SWFT		0x80
145
146/*
147 *	Mode register 1 bit definitions.
148 */
149#define	MR1_CS5			0x00
150#define	MR1_CS6			0x01
151#define	MR1_CS7			0x02
152#define	MR1_CS8			0x03
153#define	MR1_PAREVEN		0x00
154#define	MR1_PARODD		0x04
155#define	MR1_PARENB		0x00
156#define	MR1_PARFORCE		0x08
157#define	MR1_PARNONE		0x10
158#define	MR1_PARSPECIAL		0x18
159#define	MR1_ERRCHAR		0x00
160#define	MR1_ERRBLOCK		0x20
161#define	MR1_ISRUNMASKED		0x00
162#define	MR1_ISRMASKED		0x40
163#define	MR1_AUTORTS		0x80
164
165/*
166 *	Mode register 2 bit definitions.
167 */
168#define	MR2_STOP1		0x00
169#define	MR2_STOP15		0x01
170#define	MR2_STOP2		0x02
171#define	MR2_STOP916		0x03
172#define	MR2_RXFIFORDY		0x00
173#define	MR2_RXFIFOHALF		0x04
174#define	MR2_RXFIFOHIGH		0x08
175#define	MR2_RXFIFOFULL		0x0c
176#define	MR2_AUTOCTS		0x10
177#define	MR2_TXRTS		0x20
178#define	MR2_MODENORM		0x00
179#define	MR2_MODEAUTOECHO	0x40
180#define	MR2_MODELOOP		0x80
181#define	MR2_MODEREMECHO		0xc0
182
183/*****************************************************************************/
184
185/*
186 *	Baud Rate Generator (BRG) selector values.
187 */
188#define	BRG_50			0x00
189#define	BRG_75			0x01
190#define	BRG_150			0x02
191#define	BRG_200			0x03
192#define	BRG_300			0x04
193#define	BRG_450			0x05
194#define	BRG_600			0x06
195#define	BRG_900			0x07
196#define	BRG_1200		0x08
197#define	BRG_1800		0x09
198#define	BRG_2400		0x0a
199#define	BRG_3600		0x0b
200#define	BRG_4800		0x0c
201#define	BRG_7200		0x0d
202#define	BRG_9600		0x0e
203#define	BRG_14400		0x0f
204#define	BRG_19200		0x10
205#define	BRG_28200		0x11
206#define	BRG_38400		0x12
207#define	BRG_57600		0x13
208#define	BRG_115200		0x14
209#define	BRG_230400		0x15
210#define	BRG_GIN0		0x16
211#define	BRG_GIN1		0x17
212#define	BRG_CT0			0x18
213#define	BRG_CT1			0x19
214#define	BRG_RX2TX316		0x1b
215#define	BRG_RX2TX31		0x1c
216
217#define	SC26198_MAXBAUD		921600
218
219/*****************************************************************************/
220
221/*
222 *	Command register command definitions.
223 */
224#define	CR_NULL			0x04
225#define	CR_ADDRNORMAL		0x0c
226#define	CR_RXRESET		0x14
227#define	CR_TXRESET		0x1c
228#define	CR_CLEARRXERR		0x24
229#define	CR_BREAKRESET		0x2c
230#define	CR_TXSTARTBREAK		0x34
231#define	CR_TXSTOPBREAK		0x3c
232#define	CR_RTSON		0x44
233#define	CR_RTSOFF		0x4c
234#define	CR_ADDRINIT		0x5c
235#define	CR_RXERRBLOCK		0x6c
236#define	CR_TXSENDXON		0x84
237#define	CR_TXSENDXOFF		0x8c
238#define	CR_GANGXONSET		0x94
239#define	CR_GANGXOFFSET		0x9c
240#define	CR_GANGXONINIT		0xa4
241#define	CR_GANGXOFFINIT		0xac
242#define	CR_HOSTXON		0xb4
243#define	CR_HOSTXOFF		0xbc
244#define	CR_CANCELXOFF		0xc4
245#define	CR_ADDRRESET		0xdc
246#define	CR_RESETALLPORTS	0xf4
247#define	CR_RESETALL		0xfc
248
249#define	CR_RXENABLE		0x01
250#define	CR_TXENABLE		0x02
251
252/*****************************************************************************/
253
254/*
255 *	Channel status register.
256 */
257#define	SR_RXRDY		0x01
258#define	SR_RXFULL		0x02
259#define	SR_TXRDY		0x04
260#define	SR_TXEMPTY		0x08
261#define	SR_RXOVERRUN		0x10
262#define	SR_RXPARITY		0x20
263#define	SR_RXFRAMING		0x40
264#define	SR_RXBREAK		0x80
265
266#define	SR_RXERRS		(SR_RXPARITY | SR_RXFRAMING | SR_RXOVERRUN)
267
268/*****************************************************************************/
269
270/*
271 *	Interrupt status register and interrupt mask register bit definitions.
272 */
273#define	IR_TXRDY		0x01
274#define	IR_RXRDY		0x02
275#define	IR_RXBREAK		0x04
276#define	IR_XONXOFF		0x10
277#define	IR_ADDRRECOG		0x20
278#define	IR_RXWATCHDOG		0x40
279#define	IR_IOPORT		0x80
280
281/*****************************************************************************/
282
283/*
284 *	Interrupt vector register field definitions.
285 */
286#define	IVR_CHANMASK		0x07
287#define	IVR_TYPEMASK		0x18
288#define	IVR_CONSTMASK		0xc0
289
290#define	IVR_RXDATA		0x10
291#define	IVR_RXBADDATA		0x18
292#define	IVR_TXDATA		0x08
293#define	IVR_OTHER		0x00
294
295/*****************************************************************************/
296
297/*
298 *	BRG timer control register bit definitions.
299 */
300#define	BRGCTCR_DISABCLK0	0x00
301#define	BRGCTCR_ENABCLK0	0x08
302#define	BRGCTCR_DISABCLK1	0x00
303#define	BRGCTCR_ENABCLK1	0x80
304
305#define	BRGCTCR_0SCLK16		0x00
306#define	BRGCTCR_0SCLK32		0x01
307#define	BRGCTCR_0SCLK64		0x02
308#define	BRGCTCR_0SCLK128	0x03
309#define	BRGCTCR_0X1		0x04
310#define	BRGCTCR_0X12		0x05
311#define	BRGCTCR_0IO1A		0x06
312#define	BRGCTCR_0GIN0		0x07
313
314#define	BRGCTCR_1SCLK16		0x00
315#define	BRGCTCR_1SCLK32		0x10
316#define	BRGCTCR_1SCLK64		0x20
317#define	BRGCTCR_1SCLK128	0x30
318#define	BRGCTCR_1X1		0x40
319#define	BRGCTCR_1X12		0x50
320#define	BRGCTCR_1IO1B		0x60
321#define	BRGCTCR_1GIN1		0x70
322
323/*****************************************************************************/
324
325/*
326 *	Watch dog timer enable register.
327 */
328#define	WDTRCR_ENABALL		0xff
329
330/*****************************************************************************/
331
332/*
333 *	XON/XOFF interrupt status register.
334 */
335#define	XISR_TXCHARMASK		0x03
336#define	XISR_TXCHARNORMAL	0x00
337#define	XISR_TXWAIT		0x01
338#define	XISR_TXXOFFPEND		0x02
339#define	XISR_TXXONPEND		0x03
340
341#define	XISR_TXFLOWMASK		0x0c
342#define	XISR_TXNORMAL		0x00
343#define	XISR_TXSTOPPEND		0x04
344#define	XISR_TXSTARTED		0x08
345#define	XISR_TXSTOPPED		0x0c
346
347#define	XISR_RXFLOWMASK		0x30
348#define	XISR_RXFLOWNONE		0x00
349#define	XISR_RXXONSENT		0x10
350#define	XISR_RXXOFFSENT		0x20
351
352#define	XISR_RXXONGOT		0x40
353#define	XISR_RXXOFFGOT		0x80
354
355/*****************************************************************************/
356
357/*
358 *	Current interrupt register.
359 */
360#define	CIR_TYPEMASK		0xc0
361#define	CIR_TYPEOTHER		0x00
362#define	CIR_TYPETX		0x40
363#define	CIR_TYPERXGOOD		0x80
364#define	CIR_TYPERXBAD		0xc0
365
366#define	CIR_RXDATA		0x80
367#define	CIR_RXBADDATA		0x40
368#define	CIR_TXDATA		0x40
369
370#define	CIR_CHANMASK		0x07
371#define	CIR_CNTMASK		0x38
372
373#define	CIR_SUBTYPEMASK		0x38
374#define	CIR_SUBNONE		0x00
375#define	CIR_SUBCOS		0x08
376#define	CIR_SUBADDR		0x10
377#define	CIR_SUBXONXOFF		0x18
378#define	CIR_SUBBREAK		0x28
379
380/*****************************************************************************/
381
382/*
383 *	Global interrupting channel register.
384 */
385#define	GICR_CHANMASK		0x07
386
387/*****************************************************************************/
388
389/*
390 *	Global interrupting byte count register.
391 */
392#define	GICR_COUNTMASK		0x0f
393
394/*****************************************************************************/
395
396/*
397 *	Global interrupting type register.
398 */
399#define	GITR_RXMASK		0xc0
400#define	GITR_RXNONE		0x00
401#define	GITR_RXBADDATA		0x80
402#define	GITR_RXGOODDATA		0xc0
403#define	GITR_TXDATA		0x20
404
405#define	GITR_SUBTYPEMASK	0x07
406#define	GITR_SUBNONE		0x00
407#define	GITR_SUBCOS		0x01
408#define	GITR_SUBADDR		0x02
409#define	GITR_SUBXONXOFF		0x03
410#define	GITR_SUBBREAK		0x05
411
412/*****************************************************************************/
413
414/*
415 *	Input port change register.
416 */
417#define	IPR_CTS			0x01
418#define	IPR_DTR			0x02
419#define	IPR_RTS			0x04
420#define	IPR_DCD			0x08
421#define	IPR_CTSCHANGE		0x10
422#define	IPR_DTRCHANGE		0x20
423#define	IPR_RTSCHANGE		0x40
424#define	IPR_DCDCHANGE		0x80
425
426#define	IPR_CHANGEMASK		0xf0
427
428/*****************************************************************************/
429
430/*
431 *	IO port interrupt and output register.
432 */
433#define	IOPR_CTS		0x01
434#define	IOPR_DTR		0x02
435#define	IOPR_RTS		0x04
436#define	IOPR_DCD		0x08
437#define	IOPR_CTSCOS		0x10
438#define	IOPR_DTRCOS		0x20
439#define	IOPR_RTSCOS		0x40
440#define	IOPR_DCDCOS		0x80
441
442/*****************************************************************************/
443
444/*
445 *	IO port configuration register.
446 */
447#define	IOPCR_SETCTS		0x00
448#define	IOPCR_SETDTR		0x04
449#define	IOPCR_SETRTS		0x10
450#define	IOPCR_SETDCD		0x00
451
452#define	IOPCR_SETSIGS		(IOPCR_SETRTS | IOPCR_SETRTS | IOPCR_SETDTR | IOPCR_SETDCD)
453
454/*****************************************************************************/
455
456/*
457 *	General purpose output select register.
458 */
459#define	GPORS_TXC1XA		0x08
460#define	GPORS_TXC16XA		0x09
461#define	GPORS_RXC16XA		0x0a
462#define	GPORS_TXC16XB		0x0b
463#define	GPORS_GPOR3		0x0c
464#define	GPORS_GPOR2		0x0d
465#define	GPORS_GPOR1		0x0e
466#define	GPORS_GPOR0		0x0f
467
468/*****************************************************************************/
469
470/*
471 *	General purpose output register.
472 */
473#define	GPOR_0			0x01
474#define	GPOR_1			0x02
475#define	GPOR_2			0x04
476#define	GPOR_3			0x08
477
478/*****************************************************************************/
479
480/*
481 *	General purpose output clock register.
482 */
483#define	GPORC_0NONE		0x00
484#define	GPORC_0GIN0		0x01
485#define	GPORC_0GIN1		0x02
486#define	GPORC_0IO3A		0x02
487
488#define	GPORC_1NONE		0x00
489#define	GPORC_1GIN0		0x04
490#define	GPORC_1GIN1		0x08
491#define	GPORC_1IO3C		0x0c
492
493#define	GPORC_2NONE		0x00
494#define	GPORC_2GIN0		0x10
495#define	GPORC_2GIN1		0x20
496#define	GPORC_2IO3E		0x20
497
498#define	GPORC_3NONE		0x00
499#define	GPORC_3GIN0		0x40
500#define	GPORC_3GIN1		0x80
501#define	GPORC_3IO3G		0xc0
502
503/*****************************************************************************/
504
505/*
506 *	General purpose output data register.
507 */
508#define	GPOD_0MASK		0x03
509#define	GPOD_0SET1		0x00
510#define	GPOD_0SET0		0x01
511#define	GPOD_0SETR0		0x02
512#define	GPOD_0SETIO3B		0x03
513
514#define	GPOD_1MASK		0x0c
515#define	GPOD_1SET1		0x00
516#define	GPOD_1SET0		0x04
517#define	GPOD_1SETR0		0x08
518#define	GPOD_1SETIO3D		0x0c
519
520#define	GPOD_2MASK		0x30
521#define	GPOD_2SET1		0x00
522#define	GPOD_2SET0		0x10
523#define	GPOD_2SETR0		0x20
524#define	GPOD_2SETIO3F		0x30
525
526#define	GPOD_3MASK		0xc0
527#define	GPOD_3SET1		0x00
528#define	GPOD_3SET0		0x40
529#define	GPOD_3SETR0		0x80
530#define	GPOD_3SETIO3H		0xc0
531
532/*****************************************************************************/
533#endif