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/arch/powerpc/boot/dcr.h

https://github.com/aicjofs/android_kernel_lge_v500_20d
C Header | 203 lines | 169 code | 23 blank | 11 comment | 0 complexity | 13be0e01dcda4c2490c62b7070f5e354 MD5 | raw file
  1#ifndef _PPC_BOOT_DCR_H_
  2#define _PPC_BOOT_DCR_H_
  3
  4#define mfdcr(rn) \
  5	({	\
  6		unsigned long rval; \
  7		asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
  8		rval; \
  9	})
 10#define mtdcr(rn, val) \
 11	asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
 12#define mfdcrx(rn) \
 13	({	\
 14		unsigned long rval; \
 15		asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
 16		rval; \
 17	})
 18
 19/* 440GP/440GX SDRAM controller DCRs */
 20#define DCRN_SDRAM0_CFGADDR				0x010
 21#define DCRN_SDRAM0_CFGDATA				0x011
 22
 23#define SDRAM0_READ(offset) ({\
 24	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
 25	mfdcr(DCRN_SDRAM0_CFGDATA); })
 26#define SDRAM0_WRITE(offset, data) ({\
 27	mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
 28	mtdcr(DCRN_SDRAM0_CFGDATA, data); })
 29
 30#define 	SDRAM0_B0CR				0x40
 31#define 	SDRAM0_B1CR				0x44
 32#define 	SDRAM0_B2CR				0x48
 33#define 	SDRAM0_B3CR				0x4c
 34
 35static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
 36					    SDRAM0_B2CR, SDRAM0_B3CR };
 37
 38#define			SDRAM_CONFIG_BANK_ENABLE        0x00000001
 39#define			SDRAM_CONFIG_SIZE_MASK          0x000e0000
 40#define			SDRAM_CONFIG_BANK_SIZE(reg)	\
 41	(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
 42
 43/* 440GP External Bus Controller (EBC) */
 44#define DCRN_EBC0_CFGADDR				0x012
 45#define DCRN_EBC0_CFGDATA				0x013
 46#define   EBC_NUM_BANKS					  8
 47#define   EBC_B0CR					  0x00
 48#define   EBC_B1CR					  0x01
 49#define   EBC_B2CR					  0x02
 50#define   EBC_B3CR					  0x03
 51#define   EBC_B4CR					  0x04
 52#define   EBC_B5CR					  0x05
 53#define   EBC_B6CR					  0x06
 54#define   EBC_B7CR					  0x07
 55#define   EBC_BXCR(n)					  (n)
 56#define	    EBC_BXCR_BAS				    0xfff00000
 57#define	    EBC_BXCR_BS				  	    0x000e0000
 58#define	    EBC_BXCR_BANK_SIZE(reg) \
 59	(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
 60#define	    EBC_BXCR_BU				  	    0x00018000
 61#define	      EBC_BXCR_BU_OFF			  	      0x00000000
 62#define	      EBC_BXCR_BU_RO			  	      0x00008000
 63#define	      EBC_BXCR_BU_WO			  	      0x00010000
 64#define	      EBC_BXCR_BU_RW			  	      0x00018000
 65#define	    EBC_BXCR_BW				  	    0x00006000
 66#define   EBC_B0AP					  0x10
 67#define   EBC_B1AP					  0x11
 68#define   EBC_B2AP					  0x12
 69#define   EBC_B3AP					  0x13
 70#define   EBC_B4AP					  0x14
 71#define   EBC_B5AP					  0x15
 72#define   EBC_B6AP					  0x16
 73#define   EBC_B7AP					  0x17
 74#define   EBC_BXAP(n)					  (0x10+(n))
 75#define   EBC_BEAR					  0x20
 76#define   EBC_BESR					  0x21
 77#define   EBC_CFG					  0x23
 78#define   EBC_CID					  0x24
 79
 80/* 440GP Clock, PM, chip control */
 81#define DCRN_CPC0_SR					0x0b0
 82#define DCRN_CPC0_ER					0x0b1
 83#define DCRN_CPC0_FR					0x0b2
 84#define DCRN_CPC0_SYS0					0x0e0
 85#define	  CPC0_SYS0_TUNE				  0xffc00000
 86#define	  CPC0_SYS0_FBDV_MASK				  0x003c0000
 87#define	  CPC0_SYS0_FWDVA_MASK				  0x00038000
 88#define	  CPC0_SYS0_FWDVB_MASK				  0x00007000
 89#define	  CPC0_SYS0_OPDV_MASK				  0x00000c00
 90#define	  CPC0_SYS0_EPDV_MASK				  0x00000300
 91/* Helper macros to compute the actual clock divider values from the
 92 * encodings in the CPC0 register */
 93#define	  CPC0_SYS0_FBDV(reg) \
 94		((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
 95#define	  CPC0_SYS0_FWDVA(reg) \
 96		(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
 97#define	  CPC0_SYS0_FWDVB(reg) \
 98		(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
 99#define	  CPC0_SYS0_OPDV(reg) \
100		((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
101#define	  CPC0_SYS0_EPDV(reg) \
102		((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
103#define	  CPC0_SYS0_EXTSL				  0x00000080
104#define	  CPC0_SYS0_RW_MASK				  0x00000060
105#define	  CPC0_SYS0_RL					  0x00000010
106#define	  CPC0_SYS0_ZMIISL_MASK				  0x0000000c
107#define	  CPC0_SYS0_BYPASS				  0x00000002
108#define	  CPC0_SYS0_NTO1				  0x00000001
109#define DCRN_CPC0_SYS1					0x0e1
110#define DCRN_CPC0_CUST0					0x0e2
111#define DCRN_CPC0_CUST1					0x0e3
112#define DCRN_CPC0_STRP0					0x0e4
113#define DCRN_CPC0_STRP1					0x0e5
114#define DCRN_CPC0_STRP2					0x0e6
115#define DCRN_CPC0_STRP3					0x0e7
116#define DCRN_CPC0_GPIO					0x0e8
117#define DCRN_CPC0_PLB					0x0e9
118#define DCRN_CPC0_CR1					0x0ea
119#define DCRN_CPC0_CR0					0x0eb
120#define	  CPC0_CR0_SWE					  0x80000000
121#define	  CPC0_CR0_CETE					  0x40000000
122#define	  CPC0_CR0_U1FCS				  0x20000000
123#define	  CPC0_CR0_U0DTE				  0x10000000
124#define	  CPC0_CR0_U0DRE				  0x08000000
125#define	  CPC0_CR0_U0DC					  0x04000000
126#define	  CPC0_CR0_U1DTE				  0x02000000
127#define	  CPC0_CR0_U1DRE				  0x01000000
128#define	  CPC0_CR0_U1DC					  0x00800000
129#define	  CPC0_CR0_U0EC					  0x00400000
130#define	  CPC0_CR0_U1EC					  0x00200000
131#define	  CPC0_CR0_UDIV_MASK				  0x001f0000
132#define	  CPC0_CR0_UDIV(reg) \
133		((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
134#define DCRN_CPC0_MIRQ0					0x0ec
135#define DCRN_CPC0_MIRQ1					0x0ed
136#define DCRN_CPC0_JTAGID				0x0ef
137
138#define DCRN_MAL0_CFG					0x180
139#define MAL_RESET 0x80000000
140
141/* 440EP Clock/Power-on Reset regs */
142#define DCRN_CPR0_ADDR	0xc
143#define DCRN_CPR0_DATA	0xd
144#define CPR0_PLLD0	0x60
145#define CPR0_OPBD0	0xc0
146#define CPR0_PERD0	0xe0
147#define CPR0_PRIMBD0	0xa0
148#define CPR0_SCPID	0x120
149#define CPR0_PLLC0	0x40
150
151/* 405GP Clocking/Power Management/Chip Control regs */
152#define DCRN_CPC0_PLLMR 0xb0
153#define DCRN_405_CPC0_CR0 0xb1
154#define DCRN_405_CPC0_CR1 0xb2
155#define DCRN_405_CPC0_PSR 0xb4
156
157/* 405EP Clocking/Power Management/Chip Control regs */
158#define DCRN_CPC0_PLLMR0  0xf0
159#define DCRN_CPC0_PLLMR1  0xf4
160#define DCRN_CPC0_UCR     0xf5
161
162/* 440GX/405EX Clock Control reg */
163#define DCRN_CPR0_CLKUPD				0x020
164#define DCRN_CPR0_PLLC					0x040
165#define DCRN_CPR0_PLLD					0x060
166#define DCRN_CPR0_PRIMAD				0x080
167#define DCRN_CPR0_PRIMBD				0x0a0
168#define DCRN_CPR0_OPBD					0x0c0
169#define DCRN_CPR0_PERD					0x0e0
170#define DCRN_CPR0_MALD					0x100
171
172#define DCRN_SDR0_CONFIG_ADDR 	0xe
173#define DCRN_SDR0_CONFIG_DATA	0xf
174
175/* SDR read/write helper macros */
176#define SDR0_READ(offset) ({\
177	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
178	mfdcr(DCRN_SDR0_CONFIG_DATA); })
179#define SDR0_WRITE(offset, data) ({\
180	mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
181	mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
182
183#define DCRN_SDR0_UART0		0x0120
184#define DCRN_SDR0_UART1		0x0121
185#define DCRN_SDR0_UART2		0x0122
186#define DCRN_SDR0_UART3		0x0123
187
188
189/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
190
191#define DCRN_CPR0_CFGADDR				0xc
192#define DCRN_CPR0_CFGDATA				0xd
193
194#define CPR0_READ(offset) ({\
195	mtdcr(DCRN_CPR0_CFGADDR, offset); \
196	mfdcr(DCRN_CPR0_CFGDATA); })
197#define CPR0_WRITE(offset, data) ({\
198	mtdcr(DCRN_CPR0_CFGADDR, offset); \
199	mtdcr(DCRN_CPR0_CFGDATA, data); })
200
201
202
203#endif	/* _PPC_BOOT_DCR_H_ */