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/arch/arm/mach-imx/ehci-imx5.c

https://github.com/AICP/kernel_google_msm
C | 156 lines | 110 code | 20 blank | 26 comment | 16 complexity | 6a0746328abffb93309452f384c28d8a MD5 | raw file
  1/*
  2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License as published by the
  7 * Free Software Foundation; either version 2 of the License, or (at your
  8 * option) any later version.
  9 *
 10 * This program is distributed in the hope that it will be useful, but
 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 12 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 13 * for more details.
 14 */
 15
 16#include <linux/platform_device.h>
 17#include <linux/io.h>
 18
 19#include <mach/hardware.h>
 20#include <mach/mxc_ehci.h>
 21
 22#define MXC_OTG_OFFSET			0
 23#define MXC_H1_OFFSET			0x200
 24#define MXC_H2_OFFSET			0x400
 25
 26/* USB_CTRL */
 27#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)	/* OTG wakeup intr enable */
 28#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)	/* OTG power mask */
 29#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)	/* Host1 ULPI interrupt enable */
 30#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)	/* HOST1 wakeup intr enable */
 31#define MXC_H1_UCTRL_H1PM_BIT		(1 <<  8)		/* HOST1 power mask */
 32
 33/* USB_PHY_CTRL_FUNC */
 34#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)	/* OTG Disable Overcurrent Event */
 35#define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */
 36
 37/* USBH2CTRL */
 38#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
 39#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
 40#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
 41
 42#define MXC_USBCMD_OFFSET		0x140
 43
 44/* USBCMD */
 45#define MXC_UCMD_ITC_NO_THRESHOLD_MASK	(~(0xff << 16))	/* Interrupt Threshold Control */
 46
 47int mx51_initialize_usb_hw(int port, unsigned int flags)
 48{
 49	unsigned int v;
 50	void __iomem *usb_base;
 51	void __iomem *usbotg_base;
 52	void __iomem *usbother_base;
 53	int ret = 0;
 54
 55	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 56	if (!usb_base) {
 57		printk(KERN_ERR "%s(): ioremap failed\n", __func__);
 58		return -ENOMEM;
 59	}
 60
 61	switch (port) {
 62	case 0:	/* OTG port */
 63		usbotg_base = usb_base + MXC_OTG_OFFSET;
 64		break;
 65	case 1:	/* Host 1 port */
 66		usbotg_base = usb_base + MXC_H1_OFFSET;
 67		break;
 68	case 2: /* Host 2 port */
 69		usbotg_base = usb_base + MXC_H2_OFFSET;
 70		break;
 71	default:
 72		printk(KERN_ERR"%s no such port %d\n", __func__, port);
 73		ret = -ENOENT;
 74		goto error;
 75	}
 76	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 77
 78	switch (port) {
 79	case 0:	/*OTG port */
 80		if (flags & MXC_EHCI_INTERNAL_PHY) {
 81			v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 82
 83			if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
 84				/* OC/USBPWR is not used */
 85				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
 86			} else {
 87				/* OC/USBPWR is used */
 88				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
 89			}
 90			__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 91
 92			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 93			if (flags & MXC_EHCI_WAKEUP_ENABLED)
 94				v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
 95			else
 96				v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
 97			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
 98				v |= MXC_OTG_UCTRL_OPM_BIT;
 99			else
100				v &= ~MXC_OTG_UCTRL_OPM_BIT;
101			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
102		}
103		break;
104	case 1:	/* Host 1 */
105		/*Host ULPI */
106		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
107		if (flags & MXC_EHCI_WAKEUP_ENABLED) {
108			/* HOST1 wakeup/ULPI intr enable */
109			v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
110		} else {
111			/* HOST1 wakeup/ULPI intr disable */
112			v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
113		}
114
115		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
116			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
117		else
118			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
119		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
120
121		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
122		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
123			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
124		else
125			v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
126		__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
127
128		v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
129		if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
130			/* Interrupt Threshold Control:Immediate (no threshold) */
131			v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
132		__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
133		break;
134	case 2: /* Host 2 ULPI */
135		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
136		if (flags & MXC_EHCI_WAKEUP_ENABLED) {
137			/* HOST1 wakeup/ULPI intr enable */
138			v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
139		} else {
140			/* HOST1 wakeup/ULPI intr disable */
141			v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
142		}
143
144		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
145			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
146		else
147			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
148		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
149		break;
150	}
151
152error:
153	iounmap(usb_base);
154	return ret;
155}
156