PageRenderTime 23ms CodeModel.GetById 17ms app.highlight 3ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/powerpc/boot/uartlite.c

https://github.com/aicjofs/android_kernel_lge_v500_20d
C | 79 lines | 56 code | 13 blank | 10 comment | 5 complexity | df94a02133eeae2030dff8224ad66437 MD5 | raw file
 1/*
 2 * Xilinx UARTLITE bootloader driver
 3 *
 4 * Copyright (C) 2007 Secret Lab Technologies Ltd.
 5 *
 6 * This file is licensed under the terms of the GNU General Public License
 7 * version 2. This program is licensed "as is" without any warranty of any
 8 * kind, whether express or implied.
 9 */
10
11#include <stdarg.h>
12#include <stddef.h>
13#include "types.h"
14#include "string.h"
15#include "stdio.h"
16#include "io.h"
17#include "ops.h"
18
19#define ULITE_RX		0x00
20#define ULITE_TX		0x04
21#define ULITE_STATUS		0x08
22#define ULITE_CONTROL		0x0c
23
24#define ULITE_STATUS_RXVALID	0x01
25#define ULITE_STATUS_TXFULL	0x08
26
27#define ULITE_CONTROL_RST_RX	0x02
28
29static void * reg_base;
30
31static int uartlite_open(void)
32{
33	/* Clear the RX FIFO */
34	out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
35	return 0;
36}
37
38static void uartlite_putc(unsigned char c)
39{
40	u32 reg = ULITE_STATUS_TXFULL;
41	while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
42		reg = in_be32(reg_base + ULITE_STATUS);
43	out_be32(reg_base + ULITE_TX, c);
44}
45
46static unsigned char uartlite_getc(void)
47{
48	u32 reg = 0;
49	while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
50		reg = in_be32(reg_base + ULITE_STATUS);
51	return in_be32(reg_base + ULITE_RX);
52}
53
54static u8 uartlite_tstc(void)
55{
56	u32 reg = in_be32(reg_base + ULITE_STATUS);
57	return reg & ULITE_STATUS_RXVALID;
58}
59
60int uartlite_console_init(void *devp, struct serial_console_data *scdp)
61{
62	int n;
63	unsigned long reg_phys;
64
65	n = getprop(devp, "virtual-reg", &reg_base, sizeof(reg_base));
66	if (n != sizeof(reg_base)) {
67		if (!dt_xlate_reg(devp, 0, &reg_phys, NULL))
68			return -1;
69
70		reg_base = (void *)reg_phys;
71	}
72
73	scdp->open = uartlite_open;
74	scdp->putc = uartlite_putc;
75	scdp->getc = uartlite_getc;
76	scdp->tstc = uartlite_tstc;
77	scdp->close = NULL;
78	return 0;
79}