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/arch/powerpc/boot/dts/ebony.dts

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
Device Tree | 337 lines | 264 code | 39 blank | 34 comment | 0 complexity | 6f2b057e7742dc219faf4b4bd035d930 MD5 | raw file
  1/*
  2 * Device Tree Source for IBM Ebony
  3 *
  4 * Copyright (c) 2006, 2007 IBM Corp.
  5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
  6 *
  7 * FIXME: Draft only!
  8 *
  9 * This file is licensed under the terms of the GNU General Public
 10 * License version 2.  This program is licensed "as is" without
 11 * any warranty of any kind, whether express or implied.
 12 */
 13
 14/dts-v1/;
 15
 16/ {
 17	#address-cells = <2>;
 18	#size-cells = <1>;
 19	model = "ibm,ebony";
 20	compatible = "ibm,ebony";
 21	dcr-parent = <&{/cpus/cpu@0}>;
 22
 23	aliases {
 24		ethernet0 = &EMAC0;
 25		ethernet1 = &EMAC1;
 26		serial0 = &UART0;
 27		serial1 = &UART1;
 28	};
 29
 30	cpus {
 31		#address-cells = <1>;
 32		#size-cells = <0>;
 33
 34		cpu@0 {
 35			device_type = "cpu";
 36			model = "PowerPC,440GP";
 37			reg = <0x00000000>;
 38			clock-frequency = <0>; // Filled in by zImage
 39			timebase-frequency = <0>; // Filled in by zImage
 40			i-cache-line-size = <32>;
 41			d-cache-line-size = <32>;
 42			i-cache-size = <32768>; /* 32 kB */
 43			d-cache-size = <32768>; /* 32 kB */
 44			dcr-controller;
 45			dcr-access-method = "native";
 46		};
 47	};
 48
 49	memory {
 50		device_type = "memory";
 51		reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
 52	};
 53
 54	UIC0: interrupt-controller0 {
 55		compatible = "ibm,uic-440gp", "ibm,uic";
 56		interrupt-controller;
 57		cell-index = <0>;
 58		dcr-reg = <0x0c0 0x009>;
 59		#address-cells = <0>;
 60		#size-cells = <0>;
 61		#interrupt-cells = <2>;
 62
 63	};
 64
 65	UIC1: interrupt-controller1 {
 66		compatible = "ibm,uic-440gp", "ibm,uic";
 67		interrupt-controller;
 68		cell-index = <1>;
 69		dcr-reg = <0x0d0 0x009>;
 70		#address-cells = <0>;
 71		#size-cells = <0>;
 72		#interrupt-cells = <2>;
 73		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
 74		interrupt-parent = <&UIC0>;
 75	};
 76
 77	CPC0: cpc {
 78		compatible = "ibm,cpc-440gp";
 79		dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
 80		// FIXME: anything else?
 81	};
 82
 83	plb {
 84		compatible = "ibm,plb-440gp", "ibm,plb4";
 85		#address-cells = <2>;
 86		#size-cells = <1>;
 87		ranges;
 88		clock-frequency = <0>; // Filled in by zImage
 89
 90		SDRAM0: memory-controller {
 91			compatible = "ibm,sdram-440gp";
 92			dcr-reg = <0x010 0x002>;
 93			// FIXME: anything else?
 94		};
 95
 96		SRAM0: sram {
 97			compatible = "ibm,sram-440gp";
 98			dcr-reg = <0x020 0x008 0x00a 0x001>;
 99		};
100
101		DMA0: dma {
102			// FIXME: ???
103			compatible = "ibm,dma-440gp";
104			dcr-reg = <0x100 0x027>;
105		};
106
107		MAL0: mcmal {
108			compatible = "ibm,mcmal-440gp", "ibm,mcmal";
109			dcr-reg = <0x180 0x062>;
110			num-tx-chans = <4>;
111			num-rx-chans = <4>;
112			interrupt-parent = <&MAL0>;
113			interrupts = <0x0 0x1 0x2 0x3 0x4>;
114			#interrupt-cells = <1>;
115			#address-cells = <0>;
116			#size-cells = <0>;
117			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
118					 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
119					 /*SERR*/  0x2 &UIC1 0x0 0x4
120					 /*TXDE*/  0x3 &UIC1 0x1 0x4
121					 /*RXDE*/  0x4 &UIC1 0x2 0x4>;
122			interrupt-map-mask = <0xffffffff>;
123		};
124
125		POB0: opb {
126			compatible = "ibm,opb-440gp", "ibm,opb";
127			#address-cells = <1>;
128			#size-cells = <1>;
129			/* Wish there was a nicer way of specifying a full 32-bit
130			   range */
131			ranges = <0x00000000 0x00000001 0x00000000 0x80000000
132				  0x80000000 0x00000001 0x80000000 0x80000000>;
133			dcr-reg = <0x090 0x00b>;
134			interrupt-parent = <&UIC1>;
135			interrupts = <0x7 0x4>;
136			clock-frequency = <0>; // Filled in by zImage
137
138			EBC0: ebc {
139				compatible = "ibm,ebc-440gp", "ibm,ebc";
140				dcr-reg = <0x012 0x002>;
141				#address-cells = <2>;
142				#size-cells = <1>;
143				clock-frequency = <0>; // Filled in by zImage
144				// ranges property is supplied by zImage
145				// based on firmware's configuration of the
146				// EBC bridge
147				interrupts = <0x5 0x4>;
148				interrupt-parent = <&UIC1>;
149
150				small-flash@0,80000 {
151					compatible = "jedec-flash";
152					bank-width = <1>;
153					reg = <0x00000000 0x00080000 0x00080000>;
154					#address-cells = <1>;
155					#size-cells = <1>;
156					partition@0 {
157						label = "OpenBIOS";
158						reg = <0x00000000 0x00080000>;
159						read-only;
160					};
161				};
162
163				nvram@1,0 {
164					/* NVRAM & RTC */
165					compatible = "ds1743-nvram";
166					#bytes = <0x2000>;
167					reg = <0x00000001 0x00000000 0x00002000>;
168				};
169
170				large-flash@2,0 {
171					compatible = "jedec-flash";
172					bank-width = <1>;
173					reg = <0x00000002 0x00000000 0x00400000>;
174					#address-cells = <1>;
175					#size-cells = <1>;
176					partition@0 {
177						label = "fs";
178						reg = <0x00000000 0x00380000>;
179					};
180					partition@380000 {
181						label = "firmware";
182						reg = <0x00380000 0x00080000>;
183					};
184				};
185
186				ir@3,0 {
187					reg = <0x00000003 0x00000000 0x00000010>;
188				};
189
190				fpga@7,0 {
191					compatible = "Ebony-FPGA";
192					reg = <0x00000007 0x00000000 0x00000010>;
193					virtual-reg = <0xe8300000>;
194				};
195			};
196
197			UART0: serial@40000200 {
198				device_type = "serial";
199				compatible = "ns16550";
200				reg = <0x40000200 0x00000008>;
201				virtual-reg = <0xe0000200>;
202				clock-frequency = <11059200>;
203				current-speed = <9600>;
204				interrupt-parent = <&UIC0>;
205				interrupts = <0x0 0x4>;
206			};
207
208			UART1: serial@40000300 {
209				device_type = "serial";
210				compatible = "ns16550";
211				reg = <0x40000300 0x00000008>;
212				virtual-reg = <0xe0000300>;
213				clock-frequency = <11059200>;
214				current-speed = <9600>;
215				interrupt-parent = <&UIC0>;
216				interrupts = <0x1 0x4>;
217			};
218
219			IIC0: i2c@40000400 {
220				/* FIXME */
221				compatible = "ibm,iic-440gp", "ibm,iic";
222				reg = <0x40000400 0x00000014>;
223				interrupt-parent = <&UIC0>;
224				interrupts = <0x2 0x4>;
225			};
226			IIC1: i2c@40000500 {
227				/* FIXME */
228				compatible = "ibm,iic-440gp", "ibm,iic";
229				reg = <0x40000500 0x00000014>;
230				interrupt-parent = <&UIC0>;
231				interrupts = <0x3 0x4>;
232			};
233
234			GPIO0: gpio@40000700 {
235				/* FIXME */
236				compatible = "ibm,gpio-440gp";
237				reg = <0x40000700 0x00000020>;
238			};
239
240			ZMII0: emac-zmii@40000780 {
241				compatible = "ibm,zmii-440gp", "ibm,zmii";
242				reg = <0x40000780 0x0000000c>;
243			};
244
245			EMAC0: ethernet@40000800 {
246				device_type = "network";
247				compatible = "ibm,emac-440gp", "ibm,emac";
248				interrupt-parent = <&UIC1>;
249				interrupts = <0x1c 0x4 0x1d 0x4>;
250				reg = <0x40000800 0x00000070>;
251				local-mac-address = [000000000000]; // Filled in by zImage
252				mal-device = <&MAL0>;
253				mal-tx-channel = <0 1>;
254				mal-rx-channel = <0>;
255				cell-index = <0>;
256				max-frame-size = <1500>;
257				rx-fifo-size = <4096>;
258				tx-fifo-size = <2048>;
259				phy-mode = "rmii";
260				phy-map = <0x00000001>;
261				zmii-device = <&ZMII0>;
262				zmii-channel = <0>;
263			};
264			EMAC1: ethernet@40000900 {
265				device_type = "network";
266				compatible = "ibm,emac-440gp", "ibm,emac";
267				interrupt-parent = <&UIC1>;
268				interrupts = <0x1e 0x4 0x1f 0x4>;
269				reg = <0x40000900 0x00000070>;
270				local-mac-address = [000000000000]; // Filled in by zImage
271				mal-device = <&MAL0>;
272				mal-tx-channel = <2 3>;
273				mal-rx-channel = <1>;
274				cell-index = <1>;
275				max-frame-size = <1500>;
276				rx-fifo-size = <4096>;
277				tx-fifo-size = <2048>;
278				phy-mode = "rmii";
279				phy-map = <0x00000001>;
280				zmii-device = <&ZMII0>;
281				zmii-channel = <1>;
282			};
283
284
285			GPT0: gpt@40000a00 {
286				/* FIXME */
287				reg = <0x40000a00 0x000000d4>;
288				interrupt-parent = <&UIC0>;
289				interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
290			};
291
292		};
293
294		PCIX0: pci@20ec00000 {
295			device_type = "pci";
296			#interrupt-cells = <1>;
297			#size-cells = <2>;
298			#address-cells = <3>;
299			compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
300			primary;
301			reg = <0x00000002 0x0ec00000 0x00000008	/* Config space access */
302			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
303			       0x00000002 0x0ed00000 0x00000004     /* Special cycles */
304			       0x00000002 0x0ec80000 0x000000f0	/* Internal registers */
305			       0x00000002 0x0ec80100 0x000000fc>;	/* Internal messaging registers */
306
307			/* Outbound ranges, one memory and one IO,
308			 * later cannot be changed
309			 */
310			ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
311				  0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
312
313			/* Inbound 2GB range starting at 0 */
314			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
315
316			/* Ebony has all 4 IRQ pins tied together per slot */
317			interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
318			interrupt-map = <
319				/* IDSEL 1 */
320				0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
321
322				/* IDSEL 2 */
323				0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
324
325				/* IDSEL 3 */
326				0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
327
328				/* IDSEL 4 */
329				0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
330			>;
331		};
332	};
333
334	chosen {
335		linux,stdout-path = "/plb/opb/serial@40000200";
336	};
337};