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/arch/powerpc/boot/dts/asp834x-redboot.dts

https://github.com/aicjofs/android_kernel_lge_v500_20d
Device Tree | 312 lines | 259 code | 31 blank | 22 comment | 0 complexity | c1d1df350a1aa3a4283acec7522cac4e MD5 | raw file
  1/*
  2 * Analogue & Micro ASP8347 Device Tree Source
  3 *
  4 * Copyright 2008 Codehermit
  5 *
  6 * This program is free software; you can redistribute  it and/or modify it
  7 * under  the terms of  the GNU General  Public License as published by the
  8 * Free Software Foundation;  either version 2 of the  License, or (at your
  9 * option) any later version.
 10 */
 11
 12/dts-v1/;
 13
 14/ {
 15	model = "Analogue & Micro ASP8347E";
 16	compatible = "analogue-and-micro,asp8347e";
 17	#address-cells = <1>;
 18	#size-cells = <1>;
 19
 20	aliases {
 21		ethernet0 = &enet0;
 22		ethernet1 = &enet1;
 23		serial0 = &serial0;
 24		serial1 = &serial1;
 25	};
 26
 27	cpus {
 28		#address-cells = <1>;
 29		#size-cells = <0>;
 30
 31		PowerPC,8347@0 {
 32			device_type = "cpu";
 33			reg = <0x0>;
 34			d-cache-line-size = <32>;
 35			i-cache-line-size = <32>;
 36			d-cache-size = <32768>;
 37			i-cache-size = <32768>;
 38			timebase-frequency = <0>;	// from bootloader
 39			bus-frequency = <0>;		// from bootloader
 40			clock-frequency = <0>;		// from bootloader
 41		};
 42	};
 43
 44	memory {
 45		device_type = "memory";
 46		reg = <0x00000000 0x8000000>;	// 128MB at 0
 47	};
 48
 49	localbus@ff005000 {
 50		#address-cells = <2>;
 51		#size-cells = <1>;
 52		compatible = "fsl,mpc8347e-localbus",
 53			     "fsl,pq2pro-localbus",
 54			     "simple-bus";
 55		reg = <0xff005000 0x1000>;
 56		interrupts = <77 0x8>;
 57		interrupt-parent = <&ipic>;
 58
 59		ranges = <
 60			0 0 0xf0000000 0x02000000
 61		>;
 62
 63		flash@0,0 {
 64			compatible = "cfi-flash";
 65			reg = <0 0 0x02000000>;
 66			bank-width = <2>;
 67			device-width = <2>;
 68		};
 69	};
 70
 71	soc8349@ff000000 {
 72		#address-cells = <1>;
 73		#size-cells = <1>;
 74		device_type = "soc";
 75		ranges = <0x0 0xff000000 0x00100000>;
 76		reg = <0xff000000 0x00000200>;
 77		bus-frequency = <0>;
 78
 79		wdt@200 {
 80			device_type = "watchdog";
 81			compatible = "mpc83xx_wdt";
 82			reg = <0x200 0x100>;
 83		};
 84
 85		i2c@3000 {
 86			#address-cells = <1>;
 87			#size-cells = <0>;
 88			cell-index = <0>;
 89			compatible = "fsl-i2c";
 90			reg = <0x3000 0x100>;
 91			interrupts = <14 0x8>;
 92			interrupt-parent = <&ipic>;
 93			dfsrr;
 94
 95			rtc@68 {
 96				compatible = "dallas,ds1374";
 97				reg = <0x68>;
 98			};
 99		};
100
101		i2c@3100 {
102			#address-cells = <1>;
103			#size-cells = <0>;
104			cell-index = <1>;
105			compatible = "fsl-i2c";
106			reg = <0x3100 0x100>;
107			interrupts = <15 0x8>;
108			interrupt-parent = <&ipic>;
109			dfsrr;
110		};
111
112		spi@7000 {
113			cell-index = <0>;
114			compatible = "fsl,spi";
115			reg = <0x7000 0x1000>;
116			interrupts = <16 0x8>;
117			interrupt-parent = <&ipic>;
118			mode = "cpu";
119		};
120
121		dma@82a8 {
122			#address-cells = <1>;
123			#size-cells = <1>;
124			compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
125			reg = <0x82a8 4>;
126			ranges = <0 0x8100 0x1a8>;
127			interrupt-parent = <&ipic>;
128			interrupts = <71 8>;
129			cell-index = <0>;
130			dma-channel@0 {
131				compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
132				reg = <0 0x80>;
133				cell-index = <0>;
134				interrupt-parent = <&ipic>;
135				interrupts = <71 8>;
136			};
137			dma-channel@80 {
138				compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
139				reg = <0x80 0x80>;
140				cell-index = <1>;
141				interrupt-parent = <&ipic>;
142				interrupts = <71 8>;
143			};
144			dma-channel@100 {
145				compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
146				reg = <0x100 0x80>;
147				cell-index = <2>;
148				interrupt-parent = <&ipic>;
149				interrupts = <71 8>;
150			};
151			dma-channel@180 {
152				compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
153				reg = <0x180 0x28>;
154				cell-index = <3>;
155				interrupt-parent = <&ipic>;
156				interrupts = <71 8>;
157			};
158		};
159
160		/* phy type (ULPI or SERIAL) are only types supported for MPH */
161		/* port = 0 or 1 */
162		usb@22000 {
163			compatible = "fsl-usb2-mph";
164			reg = <0x22000 0x1000>;
165			#address-cells = <1>;
166			#size-cells = <0>;
167			interrupt-parent = <&ipic>;
168			interrupts = <39 0x8>;
169			phy_type = "ulpi";
170			port0;
171		};
172		/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
173		usb@23000 {
174			compatible = "fsl-usb2-dr";
175			reg = <0x23000 0x1000>;
176			#address-cells = <1>;
177			#size-cells = <0>;
178			interrupt-parent = <&ipic>;
179			interrupts = <38 0x8>;
180			dr_mode = "otg";
181			phy_type = "ulpi";
182		};
183
184		enet0: ethernet@24000 {
185			#address-cells = <1>;
186			#size-cells = <1>;
187			cell-index = <0>;
188			device_type = "network";
189			model = "TSEC";
190			compatible = "gianfar";
191			reg = <0x24000 0x1000>;
192			ranges = <0x0 0x24000 0x1000>;
193			local-mac-address = [ 00 08 e5 11 32 33 ];
194			interrupts = <32 0x8 33 0x8 34 0x8>;
195			interrupt-parent = <&ipic>;
196			tbi-handle = <&tbi0>;
197			phy-handle = <&phy0>;
198			linux,network-index = <0>;
199
200			mdio@520 {
201				#address-cells = <1>;
202				#size-cells = <0>;
203				compatible = "fsl,gianfar-mdio";
204				reg = <0x520 0x20>;
205
206				phy0: ethernet-phy@0 {
207					interrupt-parent = <&ipic>;
208					interrupts = <17 0x8>;
209					reg = <0x1>;
210					device_type = "ethernet-phy";
211				};
212
213				phy1: ethernet-phy@1 {
214					interrupt-parent = <&ipic>;
215					interrupts = <18 0x8>;
216					reg = <0x2>;
217					device_type = "ethernet-phy";
218				};
219
220				tbi0: tbi-phy@11 {
221					reg = <0x11>;
222					device_type = "tbi-phy";
223				};
224			};
225		};
226
227		enet1: ethernet@25000 {
228			#address-cells = <1>;
229			#size-cells = <1>;
230			cell-index = <1>;
231			device_type = "network";
232			model = "TSEC";
233			compatible = "gianfar";
234			reg = <0x25000 0x1000>;
235			ranges = <0x0 0x25000 0x1000>;
236			local-mac-address = [ 00 08 e5 11 32 34 ];
237			interrupts = <35 0x8 36 0x8 37 0x8>;
238			interrupt-parent = <&ipic>;
239			tbi-handle = <&tbi1>;
240			phy-handle = <&phy1>;
241			linux,network-index = <1>;
242
243			mdio@520 {
244				#address-cells = <1>;
245				#size-cells = <0>;
246				compatible = "fsl,gianfar-tbi";
247				reg = <0x520 0x20>;
248
249				tbi1: tbi-phy@11 {
250					reg = <0x11>;
251					device_type = "tbi-phy";
252				};
253			};
254		};
255
256		serial0: serial@4500 {
257			cell-index = <0>;
258			device_type = "serial";
259			compatible = "fsl,ns16550", "ns16550";
260			reg = <0x4500 0x100>;
261			clock-frequency = <400000000>;
262			interrupts = <9 0x8>;
263			interrupt-parent = <&ipic>;
264		};
265
266		serial1: serial@4600 {
267			cell-index = <1>;
268			device_type = "serial";
269			compatible = "fsl,ns16550", "ns16550";
270			reg = <0x4600 0x100>;
271			clock-frequency = <400000000>;
272			interrupts = <10 0x8>;
273			interrupt-parent = <&ipic>;
274		};
275
276		/* May need to remove if on a part without crypto engine */
277		crypto@30000 {
278			device_type = "crypto";
279			model = "SEC2";
280			compatible = "talitos";
281			reg = <0x30000 0x10000>;
282			interrupts = <11 0x8>;
283			interrupt-parent = <&ipic>;
284			num-channels = <4>;
285			channel-fifo-len = <24>;
286			exec-units-mask = <0x0000007e>;
287			/* desc mask is for rev2.0,
288			 * we need runtime fixup for >2.0 */
289			descriptor-types-mask = <0x01010ebf>;
290		};
291
292		/* IPIC
293		 * interrupts cell = <intr #, sense>
294		 * sense values match linux IORESOURCE_IRQ_* defines:
295		 * sense == 8: Level, low assertion
296		 * sense == 2: Edge, high-to-low change
297		 */
298		ipic: pic@700 {
299			interrupt-controller;
300			#address-cells = <0>;
301			#interrupt-cells = <2>;
302			reg = <0x700 0x100>;
303			device_type = "ipic";
304		};
305	};
306
307	chosen {
308		bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
309		linux,stdout-path = &serial0;
310	};
311
312};