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/arch/powerpc/boot/dts/digsy_mtc.dts

https://github.com/aicjofs/android_kernel_lge_v500_20d
Device Tree | 169 lines | 130 code | 26 blank | 13 comment | 0 complexity | de68e66969a0ac6578bef201fcbcdcce MD5 | raw file
  1/*
  2 * Digsy MTC board Device Tree Source
  3 *
  4 * Copyright (C) 2009 Semihalf
  5 *
  6 * Based on the CM5200 by M. Balakowicz
  7 *
  8 * This program is free software; you can redistribute  it and/or modify it
  9 * under  the terms of  the GNU General  Public License as published by the
 10 * Free Software Foundation;  either version 2 of the  License, or (at your
 11 * option) any later version.
 12 */
 13
 14/include/ "mpc5200b.dtsi"
 15
 16/ {
 17	model = "intercontrol,digsy-mtc";
 18	compatible = "intercontrol,digsy-mtc";
 19
 20	memory {
 21		reg = <0x00000000 0x02000000>;	// 32MB
 22	};
 23
 24	soc5200@f0000000 {
 25		timer@600 {	// General Purpose Timer
 26			#gpio-cells = <2>;
 27			fsl,has-wdt;
 28			gpio-controller;
 29		};
 30
 31		timer@610 {
 32			#gpio-cells = <2>;
 33			gpio-controller;
 34		};
 35
 36		rtc@800 {
 37			status = "disabled";
 38		};
 39
 40		spi@f00 {
 41			msp430@0 {
 42				compatible = "spidev";
 43				spi-max-frequency = <32000>;
 44				reg = <0>;
 45			};
 46		};
 47
 48		psc@2000 {		// PSC1
 49			status = "disabled";
 50		};
 51
 52		psc@2200 {		// PSC2
 53			status = "disabled";
 54		};
 55
 56		psc@2400 {		// PSC3
 57			status = "disabled";
 58		};
 59
 60		psc@2600 {		// PSC4
 61			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
 62		};
 63
 64		psc@2800 {		// PSC5
 65			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
 66		};
 67
 68		psc@2c00 {		// PSC6
 69			status = "disabled";
 70		};
 71
 72		ethernet@3000 {
 73			phy-handle = <&phy0>;
 74		};
 75
 76		mdio@3000 {
 77			phy0: ethernet-phy@0 {
 78				reg = <0>;
 79			};
 80		};
 81
 82		i2c@3d00 {
 83			eeprom@50 {
 84				compatible = "at,24c08";
 85				reg = <0x50>;
 86			};
 87
 88			rtc@56 {
 89				compatible = "mc,rv3029c2";
 90				reg = <0x56>;
 91			};
 92
 93			rtc@68 {
 94				compatible = "dallas,ds1339";
 95				reg = <0x68>;
 96			};
 97		};
 98
 99		i2c@3d40 {
100			status = "disabled";
101		};
102	};
103
104	pci@f0000d00 {
105		interrupt-map-mask = <0xf800 0 0 7>;
106		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
107				 0xc000 0 0 2 &mpc5200_pic 0 0 3
108				 0xc000 0 0 3 &mpc5200_pic 0 0 3
109				 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
110		clock-frequency = <0>; // From boot loader
111		interrupts = <2 8 0 2 9 0 2 10 0>;
112		bus-range = <0 0>;
113		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
114			  0x02000000 0 0x90000000 0x90000000 0 0x10000000
115			  0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
116	};
117
118	localbus {
119		ranges = <0 0 0xff000000 0x1000000
120			  4 0 0x60000000 0x0001000>;
121
122		// 16-bit flash device at LocalPlus Bus CS0
123		flash@0,0 {
124			compatible = "cfi-flash";
125			reg = <0 0 0x1000000>;
126			bank-width = <2>;
127			device-width = <2>;
128			#size-cells = <1>;
129			#address-cells = <1>;
130
131			partition@0 {
132				label = "kernel";
133				reg = <0x0 0x00200000>;
134			};
135			partition@200000 {
136				label = "root";
137				reg = <0x00200000 0x00300000>;
138			};
139			partition@500000 {
140				label = "user";
141				reg = <0x00500000 0x00a00000>;
142			};
143			partition@f00000 {
144				label = "u-boot";
145				reg = <0x00f00000 0x100000>;
146			};
147		};
148
149		can@4,0 {
150			compatible = "nxp,sja1000";
151			reg = <4 0x000 0x80>;
152			nxp,external-clock-frequency = <24000000>;
153			interrupts = <1 2 3>; // Level-low
154		};
155
156		can@4,100 {
157			compatible = "nxp,sja1000";
158			reg = <4 0x100 0x80>;
159			nxp,external-clock-frequency = <24000000>;
160			interrupts = <1 2 3>;  // Level-low
161		};
162
163		serial@4,200 {
164			compatible = "nxp,sc28l92";
165			reg = <4 0x200 0x10>;
166			interrupts = <1 3 3>;
167		};
168	};
169};