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/arch/arm/mach-integrator/include/mach/platform.h

https://github.com/AICP/kernel_google_msm
C Header | 402 lines | 220 code | 47 blank | 135 comment | 0 complexity | bbdd5add0d444dd9dc4288d5bd0d7547 MD5 | raw file
  1/*
  2 * This program is free software; you can redistribute it and/or modify
  3 * it under the terms of the GNU General Public License as published by
  4 * the Free Software Foundation; either version 2 of the License, or
  5 * (at your option) any later version.
  6 *
  7 * This program is distributed in the hope that it will be useful,
  8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 10 * GNU General Public License for more details.
 11 *
 12 * You should have received a copy of the GNU General Public License
 13 * along with this program; if not, write to the Free Software
 14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 15 */
 16/**************************************************************************
 17 * * Copyright © ARM Limited 1998.  All rights reserved.
 18 * ***********************************************************************/
 19/* ************************************************************************
 20 *
 21 *   Integrator address map
 22 *
 23 * ***********************************************************************/
 24
 25#ifndef __address_h
 26#define __address_h                     1
 27
 28/* ========================================================================
 29 *  Integrator definitions
 30 * ========================================================================
 31 * ------------------------------------------------------------------------
 32 *  Memory definitions
 33 * ------------------------------------------------------------------------
 34 *  Integrator memory map
 35 *
 36 */
 37#define INTEGRATOR_BOOT_ROM_LO          0x00000000
 38#define INTEGRATOR_BOOT_ROM_HI          0x20000000
 39#define INTEGRATOR_BOOT_ROM_BASE        INTEGRATOR_BOOT_ROM_HI	 /*  Normal position */
 40#define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K
 41
 42/*
 43 *  New Core Modules have different amounts of SSRAM, the amount of SSRAM
 44 *  fitted can be found in HDR_STAT.
 45 *
 46 *  The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
 47 *  the minimum amount of SSRAM fitted on any core module.
 48 *
 49 *  New Core Modules also alias the SSRAM.
 50 *
 51 */
 52#define INTEGRATOR_SSRAM_BASE           0x00000000
 53#define INTEGRATOR_SSRAM_ALIAS_BASE     0x10800000
 54#define INTEGRATOR_SSRAM_SIZE           SZ_256K
 55
 56#define INTEGRATOR_FLASH_BASE           0x24000000
 57#define INTEGRATOR_FLASH_SIZE           SZ_32M
 58
 59#define INTEGRATOR_MBRD_SSRAM_BASE      0x28000000
 60#define INTEGRATOR_MBRD_SSRAM_SIZE      SZ_512K
 61
 62/*
 63 *  SDRAM is a SIMM therefore the size is not known.
 64 *
 65 */
 66#define INTEGRATOR_SDRAM_BASE           0x00040000
 67
 68#define INTEGRATOR_SDRAM_ALIAS_BASE     0x80000000
 69#define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
 70#define INTEGRATOR_HDR1_SDRAM_BASE      0x90000000
 71#define INTEGRATOR_HDR2_SDRAM_BASE      0xA0000000
 72#define INTEGRATOR_HDR3_SDRAM_BASE      0xB0000000
 73
 74/*
 75 *  Logic expansion modules
 76 *
 77 */
 78#define INTEGRATOR_LOGIC_MODULES_BASE   0xC0000000
 79#define INTEGRATOR_LOGIC_MODULE0_BASE   0xC0000000
 80#define INTEGRATOR_LOGIC_MODULE1_BASE   0xD0000000
 81#define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
 82#define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000
 83
 84/* ------------------------------------------------------------------------
 85 *  Integrator header card registers
 86 * ------------------------------------------------------------------------
 87 *
 88 */
 89#define INTEGRATOR_HDR_ID_OFFSET        0x00
 90#define INTEGRATOR_HDR_PROC_OFFSET      0x04
 91#define INTEGRATOR_HDR_OSC_OFFSET       0x08
 92#define INTEGRATOR_HDR_CTRL_OFFSET      0x0C
 93#define INTEGRATOR_HDR_STAT_OFFSET      0x10
 94#define INTEGRATOR_HDR_LOCK_OFFSET      0x14
 95#define INTEGRATOR_HDR_SDRAM_OFFSET     0x20
 96#define INTEGRATOR_HDR_INIT_OFFSET      0x24	 /*  CM9x6 */
 97#define INTEGRATOR_HDR_IC_OFFSET        0x40
 98#define INTEGRATOR_HDR_SPDBASE_OFFSET   0x100
 99#define INTEGRATOR_HDR_SPDTOP_OFFSET    0x200
100
101#define INTEGRATOR_HDR_BASE             0x10000000
102#define INTEGRATOR_HDR_ID               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
103#define INTEGRATOR_HDR_PROC             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
104#define INTEGRATOR_HDR_OSC              (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
105#define INTEGRATOR_HDR_CTRL             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
106#define INTEGRATOR_HDR_STAT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
107#define INTEGRATOR_HDR_LOCK             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
108#define INTEGRATOR_HDR_SDRAM            (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
109#define INTEGRATOR_HDR_INIT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
110#define INTEGRATOR_HDR_IC               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
111#define INTEGRATOR_HDR_SPDBASE          (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
112#define INTEGRATOR_HDR_SPDTOP           (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
113
114#define INTEGRATOR_HDR_CTRL_LED         0x01
115#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
116#define INTEGRATOR_HDR_CTRL_REMAP       0x04
117#define INTEGRATOR_HDR_CTRL_RESET       0x08
118#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
119#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN  0x20
120#define INTEGRATOR_HDR_CTRL_FASTBUS     0x40
121#define INTEGRATOR_HDR_CTRL_SYNC        0x80
122
123#define INTEGRATOR_HDR_OSC_CORE_10MHz   0x102
124#define INTEGRATOR_HDR_OSC_CORE_15MHz   0x107
125#define INTEGRATOR_HDR_OSC_CORE_20MHz   0x10C
126#define INTEGRATOR_HDR_OSC_CORE_25MHz   0x111
127#define INTEGRATOR_HDR_OSC_CORE_30MHz   0x116
128#define INTEGRATOR_HDR_OSC_CORE_35MHz   0x11B
129#define INTEGRATOR_HDR_OSC_CORE_40MHz   0x120
130#define INTEGRATOR_HDR_OSC_CORE_45MHz   0x125
131#define INTEGRATOR_HDR_OSC_CORE_50MHz   0x12A
132#define INTEGRATOR_HDR_OSC_CORE_55MHz   0x12F
133#define INTEGRATOR_HDR_OSC_CORE_60MHz   0x134
134#define INTEGRATOR_HDR_OSC_CORE_65MHz   0x139
135#define INTEGRATOR_HDR_OSC_CORE_70MHz   0x13E
136#define INTEGRATOR_HDR_OSC_CORE_75MHz   0x143
137#define INTEGRATOR_HDR_OSC_CORE_80MHz   0x148
138#define INTEGRATOR_HDR_OSC_CORE_85MHz   0x14D
139#define INTEGRATOR_HDR_OSC_CORE_90MHz   0x152
140#define INTEGRATOR_HDR_OSC_CORE_95MHz   0x157
141#define INTEGRATOR_HDR_OSC_CORE_100MHz  0x15C
142#define INTEGRATOR_HDR_OSC_CORE_105MHz  0x161
143#define INTEGRATOR_HDR_OSC_CORE_110MHz  0x166
144#define INTEGRATOR_HDR_OSC_CORE_115MHz  0x16B
145#define INTEGRATOR_HDR_OSC_CORE_120MHz  0x170
146#define INTEGRATOR_HDR_OSC_CORE_125MHz  0x175
147#define INTEGRATOR_HDR_OSC_CORE_130MHz  0x17A
148#define INTEGRATOR_HDR_OSC_CORE_135MHz  0x17F
149#define INTEGRATOR_HDR_OSC_CORE_140MHz  0x184
150#define INTEGRATOR_HDR_OSC_CORE_145MHz  0x189
151#define INTEGRATOR_HDR_OSC_CORE_150MHz  0x18E
152#define INTEGRATOR_HDR_OSC_CORE_155MHz  0x193
153#define INTEGRATOR_HDR_OSC_CORE_160MHz  0x198
154#define INTEGRATOR_HDR_OSC_CORE_MASK    0x7FF
155
156#define INTEGRATOR_HDR_OSC_MEM_10MHz    0x10C000
157#define INTEGRATOR_HDR_OSC_MEM_15MHz    0x116000
158#define INTEGRATOR_HDR_OSC_MEM_20MHz    0x120000
159#define INTEGRATOR_HDR_OSC_MEM_25MHz    0x12A000
160#define INTEGRATOR_HDR_OSC_MEM_30MHz    0x134000
161#define INTEGRATOR_HDR_OSC_MEM_33MHz    0x13A000
162#define INTEGRATOR_HDR_OSC_MEM_40MHz    0x148000
163#define INTEGRATOR_HDR_OSC_MEM_50MHz    0x15C000
164#define INTEGRATOR_HDR_OSC_MEM_60MHz    0x170000
165#define INTEGRATOR_HDR_OSC_MEM_66MHz    0x17C000
166#define INTEGRATOR_HDR_OSC_MEM_MASK     0x7FF000
167
168#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0  0x0
169#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0  0x0800000
170#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6  0x1000000
171#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00  0x1800000
172#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK  0x1800000
173
174#define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)
175
176
177/* ------------------------------------------------------------------------
178 *  Integrator system registers
179 * ------------------------------------------------------------------------
180 *
181 */
182
183/*
184 *  System Controller
185 *
186 */
187#define INTEGRATOR_SC_ID_OFFSET         0x00
188#define INTEGRATOR_SC_OSC_OFFSET        0x04
189#define INTEGRATOR_SC_CTRLS_OFFSET      0x08
190#define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
191#define INTEGRATOR_SC_DEC_OFFSET        0x10
192#define INTEGRATOR_SC_ARB_OFFSET        0x14
193#define INTEGRATOR_SC_PCIENABLE_OFFSET  0x18
194#define INTEGRATOR_SC_LOCK_OFFSET       0x1C
195
196#define INTEGRATOR_SC_BASE              0x11000000
197#define INTEGRATOR_SC_ID                (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
198#define INTEGRATOR_SC_OSC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
199#define INTEGRATOR_SC_CTRLS             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
200#define INTEGRATOR_SC_CTRLC             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
201#define INTEGRATOR_SC_DEC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
202#define INTEGRATOR_SC_ARB               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
203#define INTEGRATOR_SC_PCIENABLE         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
204#define INTEGRATOR_SC_LOCK              (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
205
206#define INTEGRATOR_SC_OSC_SYS_10MHz     0x20
207#define INTEGRATOR_SC_OSC_SYS_15MHz     0x34
208#define INTEGRATOR_SC_OSC_SYS_20MHz     0x48
209#define INTEGRATOR_SC_OSC_SYS_25MHz     0x5C
210#define INTEGRATOR_SC_OSC_SYS_33MHz     0x7C
211#define INTEGRATOR_SC_OSC_SYS_MASK      0xFF
212
213#define INTEGRATOR_SC_OSC_PCI_25MHz     0x100
214#define INTEGRATOR_SC_OSC_PCI_33MHz     0x0
215#define INTEGRATOR_SC_OSC_PCI_MASK      0x100
216
217#define INTEGRATOR_SC_CTRL_SOFTRST      (1 << 0)
218#define INTEGRATOR_SC_CTRL_nFLVPPEN     (1 << 1)
219#define INTEGRATOR_SC_CTRL_nFLWP        (1 << 2)
220#define INTEGRATOR_SC_CTRL_URTS0        (1 << 4)
221#define INTEGRATOR_SC_CTRL_UDTR0        (1 << 5)
222#define INTEGRATOR_SC_CTRL_URTS1        (1 << 6)
223#define INTEGRATOR_SC_CTRL_UDTR1        (1 << 7)
224
225/*
226 *  External Bus Interface
227 *
228 */
229#define INTEGRATOR_EBI_BASE             0x12000000
230
231#define INTEGRATOR_EBI_CSR0_OFFSET      0x00
232#define INTEGRATOR_EBI_CSR1_OFFSET      0x04
233#define INTEGRATOR_EBI_CSR2_OFFSET      0x08
234#define INTEGRATOR_EBI_CSR3_OFFSET      0x0C
235#define INTEGRATOR_EBI_LOCK_OFFSET      0x20
236
237#define INTEGRATOR_EBI_CSR0             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
238#define INTEGRATOR_EBI_CSR1             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
239#define INTEGRATOR_EBI_CSR2             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
240#define INTEGRATOR_EBI_CSR3             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
241#define INTEGRATOR_EBI_LOCK             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
242
243#define INTEGRATOR_EBI_8_BIT            0x00
244#define INTEGRATOR_EBI_16_BIT           0x01
245#define INTEGRATOR_EBI_32_BIT           0x02
246#define INTEGRATOR_EBI_WRITE_ENABLE     0x04
247#define INTEGRATOR_EBI_SYNC             0x08
248#define INTEGRATOR_EBI_WS_2             0x00
249#define INTEGRATOR_EBI_WS_3             0x10
250#define INTEGRATOR_EBI_WS_4             0x20
251#define INTEGRATOR_EBI_WS_5             0x30
252#define INTEGRATOR_EBI_WS_6             0x40
253#define INTEGRATOR_EBI_WS_7             0x50
254#define INTEGRATOR_EBI_WS_8             0x60
255#define INTEGRATOR_EBI_WS_9             0x70
256#define INTEGRATOR_EBI_WS_10            0x80
257#define INTEGRATOR_EBI_WS_11            0x90
258#define INTEGRATOR_EBI_WS_12            0xA0
259#define INTEGRATOR_EBI_WS_13            0xB0
260#define INTEGRATOR_EBI_WS_14            0xC0
261#define INTEGRATOR_EBI_WS_15            0xD0
262#define INTEGRATOR_EBI_WS_16            0xE0
263#define INTEGRATOR_EBI_WS_17            0xF0
264
265
266#define INTEGRATOR_CT_BASE              0x13000000	 /*  Counter/Timers */
267#define INTEGRATOR_IC_BASE              0x14000000	 /*  Interrupt Controller */
268#define INTEGRATOR_RTC_BASE             0x15000000	 /*  Real Time Clock */
269#define INTEGRATOR_UART0_BASE           0x16000000	 /*  UART 0 */
270#define INTEGRATOR_UART1_BASE           0x17000000	 /*  UART 1 */
271#define INTEGRATOR_KBD_BASE             0x18000000	 /*  Keyboard */
272#define INTEGRATOR_MOUSE_BASE           0x19000000	 /*  Mouse */
273
274/*
275 *  LED's & Switches
276 *
277 */
278#define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
279#define INTEGRATOR_DBG_LEDS_OFFSET      0x04
280#define INTEGRATOR_DBG_SWITCH_OFFSET    0x08
281
282#define INTEGRATOR_DBG_BASE             0x1A000000
283#define INTEGRATOR_DBG_ALPHA            (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
284#define INTEGRATOR_DBG_LEDS             (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
285#define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
286
287#define INTEGRATOR_AP_GPIO_BASE		0x1B000000	/* GPIO */
288
289#define INTEGRATOR_CP_MMC_BASE		0x1C000000	/* MMC */
290#define INTEGRATOR_CP_AACI_BASE		0x1D000000	/* AACI */
291#define INTEGRATOR_CP_ETH_BASE		0xC8000000	/* Ethernet */
292#define INTEGRATOR_CP_GPIO_BASE		0xC9000000	/* GPIO */
293#define INTEGRATOR_CP_SIC_BASE		0xCA000000	/* SIC */
294#define INTEGRATOR_CP_CTL_BASE		0xCB000000	/* CP system control */
295
296/* ------------------------------------------------------------------------
297 *  KMI keyboard/mouse definitions
298 * ------------------------------------------------------------------------
299 */
300/* PS2 Keyboard interface */
301#define KMI0_BASE                       INTEGRATOR_KBD_BASE
302
303/* PS2 Mouse interface */
304#define KMI1_BASE                       INTEGRATOR_MOUSE_BASE
305
306/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
307
308/* ------------------------------------------------------------------------
309 *  Where in the memory map does PCI live?
310 * ------------------------------------------------------------------------
311 *  This represents a fairly liberal usage of address space.  Even though
312 *  the V3 only has two windows (therefore we need to map stuff on the fly),
313 *  we maintain the same addresses, even if they're not mapped.
314 *
315 */
316#define PHYS_PCI_MEM_BASE               0x40000000   /* 512M to xxx */
317/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
318 */
319#define PHYS_PCI_IO_BASE                0x60000000   /* 16M to xxx */
320/*  unused (128-16)M from B1000000-B7FFFFFF
321 */
322#define PHYS_PCI_CONFIG_BASE            0x61000000   /* 16M to xxx */
323/*  unused ((128-16)M - 64K) from XXX
324 */
325#define PHYS_PCI_V3_BASE                0x62000000
326
327/* ------------------------------------------------------------------------
328 *  Integrator Interrupt Controllers
329 * ------------------------------------------------------------------------
330 *
331 *  Offsets from interrupt controller base
332 *
333 *  System Controller interrupt controller base is
334 *
335 * 	INTEGRATOR_IC_BASE + (header_number << 6)
336 *
337 *  Core Module interrupt controller base is
338 *
339 * 	INTEGRATOR_HDR_IC
340 *
341 */
342#define IRQ_STATUS                      0
343#define IRQ_RAW_STATUS                  0x04
344#define IRQ_ENABLE                      0x08
345#define IRQ_ENABLE_SET                  0x08
346#define IRQ_ENABLE_CLEAR                0x0C
347
348#define INT_SOFT_SET                    0x10
349#define INT_SOFT_CLEAR                  0x14
350
351#define FIQ_STATUS                      0x20
352#define FIQ_RAW_STATUS                  0x24
353#define FIQ_ENABLE                      0x28
354#define FIQ_ENABLE_SET                  0x28
355#define FIQ_ENABLE_CLEAR                0x2C
356
357
358/* ------------------------------------------------------------------------
359 *  Interrupts
360 * ------------------------------------------------------------------------
361 *
362 *
363 *  Each Core Module has two interrupts controllers, one on the core module
364 *  itself and one in the system controller on the motherboard.  The
365 *  READ_INT macro in target.s reads both interrupt controllers and returns
366 *  a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
367 *  and bits 24 to 31 are from the core module.
368 *
369 *  The following definitions relate to the bitmask returned by READ_INT.
370 *
371 */
372
373/* ------------------------------------------------------------------------
374 *  LED's
375 * ------------------------------------------------------------------------
376 *
377 */
378#define GREEN_LED                       0x01
379#define YELLOW_LED                      0x02
380#define RED_LED                         0x04
381#define GREEN_LED_2                     0x08
382#define ALL_LEDS                        0x0F
383
384#define LED_BANK                        INTEGRATOR_DBG_LEDS
385
386/*
387 *  Timer definitions
388 *
389 *  Only use timer 1 & 2
390 *  (both run at 24MHz and will need the clock divider set to 16).
391 *
392 *  Timer 0 runs at bus frequency
393 */
394
395#define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
396#define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
397#define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)
398
399#define INTEGRATOR_CSR_BASE             0x10000000
400#define INTEGRATOR_CSR_SIZE             0x10000000
401
402#endif