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/arch/powerpc/boot/dts/mpc8308rdb.dts

https://github.com/aicjofs/android_kernel_lge_v500_20d
Device Tree | 311 lines | 260 code | 30 blank | 21 comment | 0 complexity | 23507071b21aaa5c06fbc6607440a0d9 MD5 | raw file
  1/*
  2 * MPC8308RDB Device Tree Source
  3 *
  4 * Copyright 2009 Freescale Semiconductor Inc.
  5 * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  6 *
  7 * This program is free software; you can redistribute  it and/or modify it
  8 * under  the terms of  the GNU General  Public License as published by the
  9 * Free Software Foundation;  either version 2 of the  License, or (at your
 10 * option) any later version.
 11 */
 12
 13/dts-v1/;
 14
 15/ {
 16	compatible = "fsl,mpc8308rdb";
 17	#address-cells = <1>;
 18	#size-cells = <1>;
 19
 20	aliases {
 21		ethernet0 = &enet0;
 22		ethernet1 = &enet1;
 23		serial0 = &serial0;
 24		serial1 = &serial1;
 25		pci0 = &pci0;
 26	};
 27
 28	cpus {
 29		#address-cells = <1>;
 30		#size-cells = <0>;
 31
 32		PowerPC,8308@0 {
 33			device_type = "cpu";
 34			reg = <0x0>;
 35			d-cache-line-size = <32>;
 36			i-cache-line-size = <32>;
 37			d-cache-size = <16384>;
 38			i-cache-size = <16384>;
 39			timebase-frequency = <0>;	// from bootloader
 40			bus-frequency = <0>;		// from bootloader
 41			clock-frequency = <0>;		// from bootloader
 42		};
 43	};
 44
 45	memory {
 46		device_type = "memory";
 47		reg = <0x00000000 0x08000000>;	// 128MB at 0
 48	};
 49
 50	localbus@e0005000 {
 51		#address-cells = <2>;
 52		#size-cells = <1>;
 53		compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
 54		reg = <0xe0005000 0x1000>;
 55		interrupts = <77 0x8>;
 56		interrupt-parent = <&ipic>;
 57
 58		// CS0 and CS1 are swapped when
 59		// booting from nand, but the
 60		// addresses are the same.
 61		ranges = <0x0 0x0 0xfe000000 0x00800000
 62		          0x1 0x0 0xe0600000 0x00002000
 63		          0x2 0x0 0xf0000000 0x00020000
 64		          0x3 0x0 0xfa000000 0x00008000>;
 65
 66		flash@0,0 {
 67			#address-cells = <1>;
 68			#size-cells = <1>;
 69			compatible = "cfi-flash";
 70			reg = <0x0 0x0 0x800000>;
 71			bank-width = <2>;
 72			device-width = <1>;
 73
 74			u-boot@0 {
 75				reg = <0x0 0x60000>;
 76				read-only;
 77			};
 78			env@60000 {
 79				reg = <0x60000 0x10000>;
 80			};
 81			env1@70000 {
 82				reg = <0x70000 0x10000>;
 83			};
 84			kernel@80000 {
 85				reg = <0x80000 0x200000>;
 86			};
 87			dtb@280000 {
 88				reg = <0x280000 0x10000>;
 89			};
 90			ramdisk@290000 {
 91				reg = <0x290000 0x570000>;
 92			};
 93		};
 94
 95		nand@1,0 {
 96			#address-cells = <1>;
 97			#size-cells = <1>;
 98			compatible = "fsl,mpc8315-fcm-nand",
 99			             "fsl,elbc-fcm-nand";
100			reg = <0x1 0x0 0x2000>;
101
102			jffs2@0 {
103				reg = <0x0 0x2000000>;
104			};
105		};
106	};
107
108	immr@e0000000 {
109		#address-cells = <1>;
110		#size-cells = <1>;
111		device_type = "soc";
112		compatible = "fsl,mpc8308-immr", "simple-bus";
113		ranges = <0 0xe0000000 0x00100000>;
114		reg = <0xe0000000 0x00000200>;
115		bus-frequency = <0>;
116
117		i2c@3000 {
118			#address-cells = <1>;
119			#size-cells = <0>;
120			cell-index = <0>;
121			compatible = "fsl-i2c";
122			reg = <0x3000 0x100>;
123			interrupts = <14 0x8>;
124			interrupt-parent = <&ipic>;
125			dfsrr;
126			rtc@68 {
127				compatible = "dallas,ds1339";
128				reg = <0x68>;
129			};
130		};
131
132		usb@23000 {
133			compatible = "fsl-usb2-dr";
134			reg = <0x23000 0x1000>;
135			#address-cells = <1>;
136			#size-cells = <0>;
137			interrupt-parent = <&ipic>;
138			interrupts = <38 0x8>;
139			dr_mode = "peripheral";
140			phy_type = "ulpi";
141		};
142
143		enet0: ethernet@24000 {
144			#address-cells = <1>;
145			#size-cells = <1>;
146			ranges = <0x0 0x24000 0x1000>;
147
148			cell-index = <0>;
149			device_type = "network";
150			model = "eTSEC";
151			compatible = "gianfar";
152			reg = <0x24000 0x1000>;
153			local-mac-address = [ 00 00 00 00 00 00 ];
154			interrupts = <32 0x8 33 0x8 34 0x8>;
155			interrupt-parent = <&ipic>;
156			tbi-handle = < &tbi0 >;
157			phy-handle = < &phy2 >;
158			fsl,magic-packet;
159
160			mdio@520 {
161				#address-cells = <1>;
162				#size-cells = <0>;
163				compatible = "fsl,gianfar-mdio";
164				reg = <0x520 0x20>;
165				phy2: ethernet-phy@2 {
166					interrupt-parent = <&ipic>;
167					interrupts = <17 0x8>;
168					reg = <0x2>;
169					device_type = "ethernet-phy";
170				};
171				tbi0: tbi-phy@11 {
172					reg = <0x11>;
173					device_type = "tbi-phy";
174				};
175			};
176		};
177
178		enet1: ethernet@25000 {
179			#address-cells = <1>;
180			#size-cells = <1>;
181			cell-index = <1>;
182			device_type = "network";
183			model = "eTSEC";
184			compatible = "gianfar";
185			reg = <0x25000 0x1000>;
186			ranges = <0x0 0x25000 0x1000>;
187			local-mac-address = [ 00 00 00 00 00 00 ];
188			interrupts = <35 0x8 36 0x8 37 0x8>;
189			interrupt-parent = <&ipic>;
190			tbi-handle = < &tbi1 >;
191			/* Vitesse 7385 isn't on the MDIO bus */
192			fixed-link = <1 1 1000 0 0>;
193			fsl,magic-packet;
194
195			mdio@520 {
196				#address-cells = <1>;
197				#size-cells = <0>;
198				compatible = "fsl,gianfar-tbi";
199				reg = <0x520 0x20>;
200
201				tbi1: tbi-phy@11 {
202					reg = <0x11>;
203					device_type = "tbi-phy";
204				};
205			};
206		};
207
208		serial0: serial@4500 {
209			cell-index = <0>;
210			device_type = "serial";
211			compatible = "fsl,ns16550", "ns16550";
212			reg = <0x4500 0x100>;
213			clock-frequency = <133333333>;
214			interrupts = <9 0x8>;
215			interrupt-parent = <&ipic>;
216		};
217
218		serial1: serial@4600 {
219			cell-index = <1>;
220			device_type = "serial";
221			compatible = "fsl,ns16550", "ns16550";
222			reg = <0x4600 0x100>;
223			clock-frequency = <133333333>;
224			interrupts = <10 0x8>;
225			interrupt-parent = <&ipic>;
226		};
227
228		gpio@c00 {
229			#gpio-cells = <2>;
230			device_type = "gpio";
231			compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
232			reg = <0xc00 0x18>;
233			interrupts = <74 0x8>;
234			interrupt-parent = <&ipic>;
235			gpio-controller;
236		};
237
238		/* IPIC
239		 * interrupts cell = <intr #, sense>
240		 * sense values match linux IORESOURCE_IRQ_* defines:
241		 * sense == 8: Level, low assertion
242		 * sense == 2: Edge, high-to-low change
243		 */
244		ipic: interrupt-controller@700 {
245			compatible = "fsl,ipic";
246			interrupt-controller;
247			#address-cells = <0>;
248			#interrupt-cells = <2>;
249			reg = <0x700 0x100>;
250			device_type = "ipic";
251		};
252
253		ipic-msi@7c0 {
254			compatible = "fsl,ipic-msi";
255			reg = <0x7c0 0x40>;
256			msi-available-ranges = <0x0 0x100>;
257			interrupts = < 0x43 0x8
258					0x4  0x8
259					0x51 0x8
260					0x52 0x8
261					0x56 0x8
262					0x57 0x8
263					0x58 0x8
264					0x59 0x8 >;
265			interrupt-parent = < &ipic >;
266		};
267
268		dma@2c000 {
269			compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
270			reg = <0x2c000 0x1800>;
271			interrupts = <3 0x8
272					94 0x8>;
273			interrupt-parent = < &ipic >;
274		};
275
276	};
277
278	pci0: pcie@e0009000 {
279		#address-cells = <3>;
280		#size-cells = <2>;
281		#interrupt-cells = <1>;
282		device_type = "pci";
283		compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
284		reg = <0xe0009000 0x00001000
285			0xb0000000 0x01000000>;
286		ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
287		          0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
288		bus-range = <0 0>;
289		interrupt-map-mask = <0xf800 0 0 7>;
290		interrupt-map = <0 0 0 1 &ipic 1 8
291				 0 0 0 2 &ipic 1 8
292				 0 0 0 3 &ipic 1 8
293				 0 0 0 4 &ipic 1 8>;
294		interrupts = <0x1 0x8>;
295		interrupt-parent = <&ipic>;
296		clock-frequency = <0>;
297
298		pcie@0 {
299			#address-cells = <3>;
300			#size-cells = <2>;
301			device_type = "pci";
302			reg = <0 0 0 0 0>;
303			ranges = <0x02000000 0 0xa0000000
304				  0x02000000 0 0xa0000000
305				  0 0x10000000
306				  0x01000000 0 0x00000000
307				  0x01000000 0 0x00000000
308				  0 0x00800000>;
309		};
310	};
311};