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/arch/arm/mach-iop32x/include/mach/irqs.h

https://github.com/AICP/kernel_google_msm
C Header | 50 lines | 32 code | 5 blank | 13 comment | 0 complexity | 51f594e98d0a3c2b9c851a0c785074d6 MD5 | raw file
 1/*
 2 * arch/arm/mach-iop32x/include/mach/irqs.h
 3 *
 4 * Author:	Rory Bolt <rorybolt@pacbell.net>
 5 * Copyright:	(C) 2002 Rory Bolt
 6 *
 7 * This program is free software; you can redistribute it and/or modify
 8 * it under the terms of the GNU General Public License version 2 as
 9 * published by the Free Software Foundation.
10 */
11
12#ifndef __IRQS_H
13#define __IRQS_H
14
15/*
16 * IOP80321 chipset interrupts
17 */
18#define IRQ_IOP32X_DMA0_EOT	0
19#define IRQ_IOP32X_DMA0_EOC	1
20#define IRQ_IOP32X_DMA1_EOT	2
21#define IRQ_IOP32X_DMA1_EOC	3
22#define IRQ_IOP32X_AA_EOT	6
23#define IRQ_IOP32X_AA_EOC	7
24#define IRQ_IOP32X_CORE_PMON	8
25#define IRQ_IOP32X_TIMER0	9
26#define IRQ_IOP32X_TIMER1	10
27#define IRQ_IOP32X_I2C_0	11
28#define IRQ_IOP32X_I2C_1	12
29#define IRQ_IOP32X_MESSAGING	13
30#define IRQ_IOP32X_ATU_BIST	14
31#define IRQ_IOP32X_PERFMON	15
32#define IRQ_IOP32X_CORE_PMU	16
33#define IRQ_IOP32X_BIU_ERR	17
34#define IRQ_IOP32X_ATU_ERR	18
35#define IRQ_IOP32X_MCU_ERR	19
36#define IRQ_IOP32X_DMA0_ERR	20
37#define IRQ_IOP32X_DMA1_ERR	21
38#define IRQ_IOP32X_AA_ERR	23
39#define IRQ_IOP32X_MSG_ERR	24
40#define IRQ_IOP32X_SSP		25
41#define IRQ_IOP32X_XINT0	27
42#define IRQ_IOP32X_XINT1	28
43#define IRQ_IOP32X_XINT2	29
44#define IRQ_IOP32X_XINT3	30
45#define IRQ_IOP32X_HPI		31
46
47#define NR_IRQS			32
48
49
50#endif