/arch/arm/mach-omap2/clock3xxx_data.c
C | 3578 lines | 2994 code | 380 blank | 204 comment | 21 complexity | 4d7954d79a97ece3ac12b7aa9bb80f42 MD5 | raw file
Large files files are truncated, but you can click here to view the full file
1/* 2 * OMAP3 clock data 3 * 4 * Copyright (C) 2007-2010 Texas Instruments, Inc. 5 * Copyright (C) 2007-2011 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * With many device clock fixes by Kevin Hilman and Jouni Högander 9 * DPLL bypass clock support added by Roman Tereshonkov 10 * 11 */ 12 13/* 14 * Virtual clocks are introduced as convenient tools. 15 * They are sources for other clocks and not supposed 16 * to be requested from drivers directly. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/clk.h> 21#include <linux/list.h> 22 23#include <plat/clkdev_omap.h> 24 25#include "clock.h" 26#include "clock3xxx.h" 27#include "clock34xx.h" 28#include "clock36xx.h" 29#include "clock3517.h" 30 31#include "cm2xxx_3xxx.h" 32#include "cm-regbits-34xx.h" 33#include "prm2xxx_3xxx.h" 34#include "prm-regbits-34xx.h" 35#include "control.h" 36 37/* 38 * clocks 39 */ 40 41#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR 42 43/* Maximum DPLL multiplier, divider values for OMAP3 */ 44#define OMAP3_MAX_DPLL_MULT 2047 45#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 46#define OMAP3_MAX_DPLL_DIV 128 47 48/* 49 * DPLL1 supplies clock to the MPU. 50 * DPLL2 supplies clock to the IVA2. 51 * DPLL3 supplies CORE domain clocks. 52 * DPLL4 supplies peripheral clocks. 53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM). 54 */ 55 56/* Forward declarations for DPLL bypass clocks */ 57static struct clk dpll1_fck; 58static struct clk dpll2_fck; 59 60/* PRM CLOCKS */ 61 62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ 63static struct clk omap_32k_fck = { 64 .name = "omap_32k_fck", 65 .ops = &clkops_null, 66 .rate = 32768, 67}; 68 69static struct clk secure_32k_fck = { 70 .name = "secure_32k_fck", 71 .ops = &clkops_null, 72 .rate = 32768, 73}; 74 75/* Virtual source clocks for osc_sys_ck */ 76static struct clk virt_12m_ck = { 77 .name = "virt_12m_ck", 78 .ops = &clkops_null, 79 .rate = 12000000, 80}; 81 82static struct clk virt_13m_ck = { 83 .name = "virt_13m_ck", 84 .ops = &clkops_null, 85 .rate = 13000000, 86}; 87 88static struct clk virt_16_8m_ck = { 89 .name = "virt_16_8m_ck", 90 .ops = &clkops_null, 91 .rate = 16800000, 92}; 93 94static struct clk virt_19_2m_ck = { 95 .name = "virt_19_2m_ck", 96 .ops = &clkops_null, 97 .rate = 19200000, 98}; 99 100static struct clk virt_26m_ck = { 101 .name = "virt_26m_ck", 102 .ops = &clkops_null, 103 .rate = 26000000, 104}; 105 106static struct clk virt_38_4m_ck = { 107 .name = "virt_38_4m_ck", 108 .ops = &clkops_null, 109 .rate = 38400000, 110}; 111 112static const struct clksel_rate osc_sys_12m_rates[] = { 113 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 114 { .div = 0 } 115}; 116 117static const struct clksel_rate osc_sys_13m_rates[] = { 118 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 119 { .div = 0 } 120}; 121 122static const struct clksel_rate osc_sys_16_8m_rates[] = { 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, 124 { .div = 0 } 125}; 126 127static const struct clksel_rate osc_sys_19_2m_rates[] = { 128 { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, 129 { .div = 0 } 130}; 131 132static const struct clksel_rate osc_sys_26m_rates[] = { 133 { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, 134 { .div = 0 } 135}; 136 137static const struct clksel_rate osc_sys_38_4m_rates[] = { 138 { .div = 1, .val = 4, .flags = RATE_IN_3XXX }, 139 { .div = 0 } 140}; 141 142static const struct clksel osc_sys_clksel[] = { 143 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, 144 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, 145 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, 146 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, 147 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, 148 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, 149 { .parent = NULL }, 150}; 151 152/* Oscillator clock */ 153/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ 154static struct clk osc_sys_ck = { 155 .name = "osc_sys_ck", 156 .ops = &clkops_null, 157 .init = &omap2_init_clksel_parent, 158 .clksel_reg = OMAP3430_PRM_CLKSEL, 159 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, 160 .clksel = osc_sys_clksel, 161 /* REVISIT: deal with autoextclkmode? */ 162 .recalc = &omap2_clksel_recalc, 163}; 164 165static const struct clksel_rate div2_rates[] = { 166 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 167 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 168 { .div = 0 } 169}; 170 171static const struct clksel sys_clksel[] = { 172 { .parent = &osc_sys_ck, .rates = div2_rates }, 173 { .parent = NULL } 174}; 175 176/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ 177/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ 178static struct clk sys_ck = { 179 .name = "sys_ck", 180 .ops = &clkops_null, 181 .parent = &osc_sys_ck, 182 .init = &omap2_init_clksel_parent, 183 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, 184 .clksel_mask = OMAP_SYSCLKDIV_MASK, 185 .clksel = sys_clksel, 186 .recalc = &omap2_clksel_recalc, 187}; 188 189static struct clk sys_altclk = { 190 .name = "sys_altclk", 191 .ops = &clkops_null, 192}; 193 194/* Optional external clock input for some McBSPs */ 195static struct clk mcbsp_clks = { 196 .name = "mcbsp_clks", 197 .ops = &clkops_null, 198}; 199 200/* PRM EXTERNAL CLOCK OUTPUT */ 201 202static struct clk sys_clkout1 = { 203 .name = "sys_clkout1", 204 .ops = &clkops_omap2_dflt, 205 .parent = &osc_sys_ck, 206 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, 207 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, 208 .recalc = &followparent_recalc, 209}; 210 211/* DPLLS */ 212 213/* CM CLOCKS */ 214 215static const struct clksel_rate div16_dpll_rates[] = { 216 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 217 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 218 { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, 219 { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, 220 { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, 221 { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, 222 { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, 223 { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, 224 { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, 225 { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, 226 { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, 227 { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, 228 { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, 229 { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, 230 { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, 231 { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, 232 { .div = 0 } 233}; 234 235static const struct clksel_rate dpll4_rates[] = { 236 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 237 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 238 { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, 239 { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, 240 { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, 241 { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, 242 { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, 243 { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, 244 { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, 245 { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, 246 { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, 247 { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, 248 { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, 249 { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, 250 { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, 251 { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, 252 { .div = 17, .val = 17, .flags = RATE_IN_36XX }, 253 { .div = 18, .val = 18, .flags = RATE_IN_36XX }, 254 { .div = 19, .val = 19, .flags = RATE_IN_36XX }, 255 { .div = 20, .val = 20, .flags = RATE_IN_36XX }, 256 { .div = 21, .val = 21, .flags = RATE_IN_36XX }, 257 { .div = 22, .val = 22, .flags = RATE_IN_36XX }, 258 { .div = 23, .val = 23, .flags = RATE_IN_36XX }, 259 { .div = 24, .val = 24, .flags = RATE_IN_36XX }, 260 { .div = 25, .val = 25, .flags = RATE_IN_36XX }, 261 { .div = 26, .val = 26, .flags = RATE_IN_36XX }, 262 { .div = 27, .val = 27, .flags = RATE_IN_36XX }, 263 { .div = 28, .val = 28, .flags = RATE_IN_36XX }, 264 { .div = 29, .val = 29, .flags = RATE_IN_36XX }, 265 { .div = 30, .val = 30, .flags = RATE_IN_36XX }, 266 { .div = 31, .val = 31, .flags = RATE_IN_36XX }, 267 { .div = 32, .val = 32, .flags = RATE_IN_36XX }, 268 { .div = 0 } 269}; 270 271/* DPLL1 */ 272/* MPU clock source */ 273/* Type: DPLL */ 274static struct dpll_data dpll1_dd = { 275 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 276 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, 277 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, 278 .clk_bypass = &dpll1_fck, 279 .clk_ref = &sys_ck, 280 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, 281 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), 282 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, 283 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 284 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, 285 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, 286 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, 287 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), 288 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, 289 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 290 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, 291 .max_multiplier = OMAP3_MAX_DPLL_MULT, 292 .min_divider = 1, 293 .max_divider = OMAP3_MAX_DPLL_DIV, 294}; 295 296static struct clk dpll1_ck = { 297 .name = "dpll1_ck", 298 .ops = &clkops_omap3_noncore_dpll_ops, 299 .parent = &sys_ck, 300 .dpll_data = &dpll1_dd, 301 .round_rate = &omap2_dpll_round_rate, 302 .set_rate = &omap3_noncore_dpll_set_rate, 303 .clkdm_name = "dpll1_clkdm", 304 .recalc = &omap3_dpll_recalc, 305}; 306 307/* 308 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 309 * DPLL isn't bypassed. 310 */ 311static struct clk dpll1_x2_ck = { 312 .name = "dpll1_x2_ck", 313 .ops = &clkops_null, 314 .parent = &dpll1_ck, 315 .clkdm_name = "dpll1_clkdm", 316 .recalc = &omap3_clkoutx2_recalc, 317}; 318 319/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ 320static const struct clksel div16_dpll1_x2m2_clksel[] = { 321 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, 322 { .parent = NULL } 323}; 324 325/* 326 * Does not exist in the TRM - needed to separate the M2 divider from 327 * bypass selection in mpu_ck 328 */ 329static struct clk dpll1_x2m2_ck = { 330 .name = "dpll1_x2m2_ck", 331 .ops = &clkops_null, 332 .parent = &dpll1_x2_ck, 333 .init = &omap2_init_clksel_parent, 334 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), 335 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, 336 .clksel = div16_dpll1_x2m2_clksel, 337 .clkdm_name = "dpll1_clkdm", 338 .recalc = &omap2_clksel_recalc, 339}; 340 341/* DPLL2 */ 342/* IVA2 clock source */ 343/* Type: DPLL */ 344 345static struct dpll_data dpll2_dd = { 346 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 347 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, 348 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, 349 .clk_bypass = &dpll2_fck, 350 .clk_ref = &sys_ck, 351 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, 352 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), 353 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, 354 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | 355 (1 << DPLL_LOW_POWER_BYPASS), 356 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, 357 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, 358 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, 359 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), 360 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, 361 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), 362 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, 363 .max_multiplier = OMAP3_MAX_DPLL_MULT, 364 .min_divider = 1, 365 .max_divider = OMAP3_MAX_DPLL_DIV, 366}; 367 368static struct clk dpll2_ck = { 369 .name = "dpll2_ck", 370 .ops = &clkops_omap3_noncore_dpll_ops, 371 .parent = &sys_ck, 372 .dpll_data = &dpll2_dd, 373 .round_rate = &omap2_dpll_round_rate, 374 .set_rate = &omap3_noncore_dpll_set_rate, 375 .clkdm_name = "dpll2_clkdm", 376 .recalc = &omap3_dpll_recalc, 377}; 378 379static const struct clksel div16_dpll2_m2x2_clksel[] = { 380 { .parent = &dpll2_ck, .rates = div16_dpll_rates }, 381 { .parent = NULL } 382}; 383 384/* 385 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT 386 * or CLKOUTX2. CLKOUT seems most plausible. 387 */ 388static struct clk dpll2_m2_ck = { 389 .name = "dpll2_m2_ck", 390 .ops = &clkops_null, 391 .parent = &dpll2_ck, 392 .init = &omap2_init_clksel_parent, 393 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 394 OMAP3430_CM_CLKSEL2_PLL), 395 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, 396 .clksel = div16_dpll2_m2x2_clksel, 397 .clkdm_name = "dpll2_clkdm", 398 .recalc = &omap2_clksel_recalc, 399}; 400 401/* 402 * DPLL3 403 * Source clock for all interfaces and for some device fclks 404 * REVISIT: Also supports fast relock bypass - not included below 405 */ 406static struct dpll_data dpll3_dd = { 407 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 408 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, 409 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, 410 .clk_bypass = &sys_ck, 411 .clk_ref = &sys_ck, 412 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, 413 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 414 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, 415 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, 416 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, 417 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, 418 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 419 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, 420 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 421 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, 422 .max_multiplier = OMAP3_MAX_DPLL_MULT, 423 .min_divider = 1, 424 .max_divider = OMAP3_MAX_DPLL_DIV, 425}; 426 427static struct clk dpll3_ck = { 428 .name = "dpll3_ck", 429 .ops = &clkops_omap3_core_dpll_ops, 430 .parent = &sys_ck, 431 .dpll_data = &dpll3_dd, 432 .round_rate = &omap2_dpll_round_rate, 433 .clkdm_name = "dpll3_clkdm", 434 .recalc = &omap3_dpll_recalc, 435}; 436 437/* 438 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 439 * DPLL isn't bypassed 440 */ 441static struct clk dpll3_x2_ck = { 442 .name = "dpll3_x2_ck", 443 .ops = &clkops_null, 444 .parent = &dpll3_ck, 445 .clkdm_name = "dpll3_clkdm", 446 .recalc = &omap3_clkoutx2_recalc, 447}; 448 449static const struct clksel_rate div31_dpll3_rates[] = { 450 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 451 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 452 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX }, 453 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX }, 454 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, 455 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX }, 456 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX }, 457 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX }, 458 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX }, 459 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX }, 460 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX }, 461 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX }, 462 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX }, 463 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX }, 464 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX }, 465 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX }, 466 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX }, 467 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX }, 468 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX }, 469 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX }, 470 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX }, 471 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX }, 472 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX }, 473 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX }, 474 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX }, 475 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX }, 476 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX }, 477 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX }, 478 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX }, 479 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX }, 480 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX }, 481 { .div = 0 }, 482}; 483 484static const struct clksel div31_dpll3m2_clksel[] = { 485 { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, 486 { .parent = NULL } 487}; 488 489/* DPLL3 output M2 - primary control point for CORE speed */ 490static struct clk dpll3_m2_ck = { 491 .name = "dpll3_m2_ck", 492 .ops = &clkops_null, 493 .parent = &dpll3_ck, 494 .init = &omap2_init_clksel_parent, 495 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 496 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, 497 .clksel = div31_dpll3m2_clksel, 498 .clkdm_name = "dpll3_clkdm", 499 .round_rate = &omap2_clksel_round_rate, 500 .set_rate = &omap3_core_dpll_m2_set_rate, 501 .recalc = &omap2_clksel_recalc, 502}; 503 504static struct clk core_ck = { 505 .name = "core_ck", 506 .ops = &clkops_null, 507 .parent = &dpll3_m2_ck, 508 .recalc = &followparent_recalc, 509}; 510 511static struct clk dpll3_m2x2_ck = { 512 .name = "dpll3_m2x2_ck", 513 .ops = &clkops_null, 514 .parent = &dpll3_m2_ck, 515 .clkdm_name = "dpll3_clkdm", 516 .recalc = &omap3_clkoutx2_recalc, 517}; 518 519/* The PWRDN bit is apparently only available on 3430ES2 and above */ 520static const struct clksel div16_dpll3_clksel[] = { 521 { .parent = &dpll3_ck, .rates = div16_dpll_rates }, 522 { .parent = NULL } 523}; 524 525/* This virtual clock is the source for dpll3_m3x2_ck */ 526static struct clk dpll3_m3_ck = { 527 .name = "dpll3_m3_ck", 528 .ops = &clkops_null, 529 .parent = &dpll3_ck, 530 .init = &omap2_init_clksel_parent, 531 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 532 .clksel_mask = OMAP3430_DIV_DPLL3_MASK, 533 .clksel = div16_dpll3_clksel, 534 .clkdm_name = "dpll3_clkdm", 535 .recalc = &omap2_clksel_recalc, 536}; 537 538/* The PWRDN bit is apparently only available on 3430ES2 and above */ 539static struct clk dpll3_m3x2_ck = { 540 .name = "dpll3_m3x2_ck", 541 .ops = &clkops_omap2_dflt_wait, 542 .parent = &dpll3_m3_ck, 543 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 544 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, 545 .flags = INVERT_ENABLE, 546 .clkdm_name = "dpll3_clkdm", 547 .recalc = &omap3_clkoutx2_recalc, 548}; 549 550static struct clk emu_core_alwon_ck = { 551 .name = "emu_core_alwon_ck", 552 .ops = &clkops_null, 553 .parent = &dpll3_m3x2_ck, 554 .clkdm_name = "dpll3_clkdm", 555 .recalc = &followparent_recalc, 556}; 557 558/* DPLL4 */ 559/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ 560/* Type: DPLL */ 561static struct dpll_data dpll4_dd; 562 563static struct dpll_data dpll4_dd_34xx __initdata = { 564 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 565 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, 566 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, 567 .clk_bypass = &sys_ck, 568 .clk_ref = &sys_ck, 569 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, 570 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 571 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, 572 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 573 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, 574 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, 575 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, 576 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 577 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, 578 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 579 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, 580 .max_multiplier = OMAP3_MAX_DPLL_MULT, 581 .min_divider = 1, 582 .max_divider = OMAP3_MAX_DPLL_DIV, 583}; 584 585static struct dpll_data dpll4_dd_3630 __initdata = { 586 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 587 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, 588 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, 589 .clk_bypass = &sys_ck, 590 .clk_ref = &sys_ck, 591 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 592 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, 593 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 594 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, 595 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, 596 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, 597 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 598 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, 599 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 600 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, 601 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK, 602 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK, 603 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, 604 .min_divider = 1, 605 .max_divider = OMAP3_MAX_DPLL_DIV, 606 .flags = DPLL_J_TYPE 607}; 608 609static struct clk dpll4_ck = { 610 .name = "dpll4_ck", 611 .ops = &clkops_omap3_noncore_dpll_ops, 612 .parent = &sys_ck, 613 .dpll_data = &dpll4_dd, 614 .round_rate = &omap2_dpll_round_rate, 615 .set_rate = &omap3_dpll4_set_rate, 616 .clkdm_name = "dpll4_clkdm", 617 .recalc = &omap3_dpll_recalc, 618}; 619 620/* 621 * This virtual clock provides the CLKOUTX2 output from the DPLL if the 622 * DPLL isn't bypassed -- 623 * XXX does this serve any downstream clocks? 624 */ 625static struct clk dpll4_x2_ck = { 626 .name = "dpll4_x2_ck", 627 .ops = &clkops_null, 628 .parent = &dpll4_ck, 629 .clkdm_name = "dpll4_clkdm", 630 .recalc = &omap3_clkoutx2_recalc, 631}; 632 633static const struct clksel dpll4_clksel[] = { 634 { .parent = &dpll4_ck, .rates = dpll4_rates }, 635 { .parent = NULL } 636}; 637 638/* This virtual clock is the source for dpll4_m2x2_ck */ 639static struct clk dpll4_m2_ck = { 640 .name = "dpll4_m2_ck", 641 .ops = &clkops_null, 642 .parent = &dpll4_ck, 643 .init = &omap2_init_clksel_parent, 644 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 645 .clksel_mask = OMAP3630_DIV_96M_MASK, 646 .clksel = dpll4_clksel, 647 .clkdm_name = "dpll4_clkdm", 648 .recalc = &omap2_clksel_recalc, 649}; 650 651/* The PWRDN bit is apparently only available on 3430ES2 and above */ 652static struct clk dpll4_m2x2_ck = { 653 .name = "dpll4_m2x2_ck", 654 .ops = &clkops_omap2_dflt_wait, 655 .parent = &dpll4_m2_ck, 656 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 657 .enable_bit = OMAP3430_PWRDN_96M_SHIFT, 658 .flags = INVERT_ENABLE, 659 .clkdm_name = "dpll4_clkdm", 660 .recalc = &omap3_clkoutx2_recalc, 661}; 662 663/* 664 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as 665 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: 666 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and 667 * CM_96K_(F)CLK. 668 */ 669 670/* Adding 192MHz Clock node needed by SGX */ 671static struct clk omap_192m_alwon_fck = { 672 .name = "omap_192m_alwon_fck", 673 .ops = &clkops_null, 674 .parent = &dpll4_m2x2_ck, 675 .recalc = &followparent_recalc, 676}; 677 678static const struct clksel_rate omap_96m_alwon_fck_rates[] = { 679 { .div = 1, .val = 1, .flags = RATE_IN_36XX }, 680 { .div = 2, .val = 2, .flags = RATE_IN_36XX }, 681 { .div = 0 } 682}; 683 684static const struct clksel omap_96m_alwon_fck_clksel[] = { 685 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, 686 { .parent = NULL } 687}; 688 689static const struct clksel_rate omap_96m_dpll_rates[] = { 690 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 691 { .div = 0 } 692}; 693 694static const struct clksel_rate omap_96m_sys_rates[] = { 695 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 696 { .div = 0 } 697}; 698 699static struct clk omap_96m_alwon_fck = { 700 .name = "omap_96m_alwon_fck", 701 .ops = &clkops_null, 702 .parent = &dpll4_m2x2_ck, 703 .recalc = &followparent_recalc, 704}; 705 706static struct clk omap_96m_alwon_fck_3630 = { 707 .name = "omap_96m_alwon_fck", 708 .parent = &omap_192m_alwon_fck, 709 .init = &omap2_init_clksel_parent, 710 .ops = &clkops_null, 711 .recalc = &omap2_clksel_recalc, 712 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 713 .clksel_mask = OMAP3630_CLKSEL_96M_MASK, 714 .clksel = omap_96m_alwon_fck_clksel 715}; 716 717static struct clk cm_96m_fck = { 718 .name = "cm_96m_fck", 719 .ops = &clkops_null, 720 .parent = &omap_96m_alwon_fck, 721 .recalc = &followparent_recalc, 722}; 723 724static const struct clksel omap_96m_fck_clksel[] = { 725 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, 726 { .parent = &sys_ck, .rates = omap_96m_sys_rates }, 727 { .parent = NULL } 728}; 729 730static struct clk omap_96m_fck = { 731 .name = "omap_96m_fck", 732 .ops = &clkops_null, 733 .parent = &sys_ck, 734 .init = &omap2_init_clksel_parent, 735 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 736 .clksel_mask = OMAP3430_SOURCE_96M_MASK, 737 .clksel = omap_96m_fck_clksel, 738 .recalc = &omap2_clksel_recalc, 739}; 740 741/* This virtual clock is the source for dpll4_m3x2_ck */ 742static struct clk dpll4_m3_ck = { 743 .name = "dpll4_m3_ck", 744 .ops = &clkops_null, 745 .parent = &dpll4_ck, 746 .init = &omap2_init_clksel_parent, 747 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 748 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 749 .clksel = dpll4_clksel, 750 .clkdm_name = "dpll4_clkdm", 751 .recalc = &omap2_clksel_recalc, 752}; 753 754/* The PWRDN bit is apparently only available on 3430ES2 and above */ 755static struct clk dpll4_m3x2_ck = { 756 .name = "dpll4_m3x2_ck", 757 .ops = &clkops_omap2_dflt_wait, 758 .parent = &dpll4_m3_ck, 759 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 760 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 761 .flags = INVERT_ENABLE, 762 .clkdm_name = "dpll4_clkdm", 763 .recalc = &omap3_clkoutx2_recalc, 764}; 765 766static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 767 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 768 { .div = 0 } 769}; 770 771static const struct clksel_rate omap_54m_alt_rates[] = { 772 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 773 { .div = 0 } 774}; 775 776static const struct clksel omap_54m_clksel[] = { 777 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, 778 { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, 779 { .parent = NULL } 780}; 781 782static struct clk omap_54m_fck = { 783 .name = "omap_54m_fck", 784 .ops = &clkops_null, 785 .init = &omap2_init_clksel_parent, 786 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 787 .clksel_mask = OMAP3430_SOURCE_54M_MASK, 788 .clksel = omap_54m_clksel, 789 .recalc = &omap2_clksel_recalc, 790}; 791 792static const struct clksel_rate omap_48m_cm96m_rates[] = { 793 { .div = 2, .val = 0, .flags = RATE_IN_3XXX }, 794 { .div = 0 } 795}; 796 797static const struct clksel_rate omap_48m_alt_rates[] = { 798 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 799 { .div = 0 } 800}; 801 802static const struct clksel omap_48m_clksel[] = { 803 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, 804 { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, 805 { .parent = NULL } 806}; 807 808static struct clk omap_48m_fck = { 809 .name = "omap_48m_fck", 810 .ops = &clkops_null, 811 .init = &omap2_init_clksel_parent, 812 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 813 .clksel_mask = OMAP3430_SOURCE_48M_MASK, 814 .clksel = omap_48m_clksel, 815 .recalc = &omap2_clksel_recalc, 816}; 817 818static struct clk omap_12m_fck = { 819 .name = "omap_12m_fck", 820 .ops = &clkops_null, 821 .parent = &omap_48m_fck, 822 .fixed_div = 4, 823 .recalc = &omap_fixed_divisor_recalc, 824}; 825 826/* This virtual clock is the source for dpll4_m4x2_ck */ 827static struct clk dpll4_m4_ck = { 828 .name = "dpll4_m4_ck", 829 .ops = &clkops_null, 830 .parent = &dpll4_ck, 831 .init = &omap2_init_clksel_parent, 832 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 833 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 834 .clksel = dpll4_clksel, 835 .clkdm_name = "dpll4_clkdm", 836 .recalc = &omap2_clksel_recalc, 837 .set_rate = &omap2_clksel_set_rate, 838 .round_rate = &omap2_clksel_round_rate, 839}; 840 841/* The PWRDN bit is apparently only available on 3430ES2 and above */ 842static struct clk dpll4_m4x2_ck = { 843 .name = "dpll4_m4x2_ck", 844 .ops = &clkops_omap2_dflt_wait, 845 .parent = &dpll4_m4_ck, 846 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 847 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT, 848 .flags = INVERT_ENABLE, 849 .clkdm_name = "dpll4_clkdm", 850 .recalc = &omap3_clkoutx2_recalc, 851}; 852 853/* This virtual clock is the source for dpll4_m5x2_ck */ 854static struct clk dpll4_m5_ck = { 855 .name = "dpll4_m5_ck", 856 .ops = &clkops_null, 857 .parent = &dpll4_ck, 858 .init = &omap2_init_clksel_parent, 859 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 860 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 861 .clksel = dpll4_clksel, 862 .clkdm_name = "dpll4_clkdm", 863 .set_rate = &omap2_clksel_set_rate, 864 .round_rate = &omap2_clksel_round_rate, 865 .recalc = &omap2_clksel_recalc, 866}; 867 868/* The PWRDN bit is apparently only available on 3430ES2 and above */ 869static struct clk dpll4_m5x2_ck = { 870 .name = "dpll4_m5x2_ck", 871 .ops = &clkops_omap2_dflt_wait, 872 .parent = &dpll4_m5_ck, 873 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 874 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 875 .flags = INVERT_ENABLE, 876 .clkdm_name = "dpll4_clkdm", 877 .recalc = &omap3_clkoutx2_recalc, 878}; 879 880/* This virtual clock is the source for dpll4_m6x2_ck */ 881static struct clk dpll4_m6_ck = { 882 .name = "dpll4_m6_ck", 883 .ops = &clkops_null, 884 .parent = &dpll4_ck, 885 .init = &omap2_init_clksel_parent, 886 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 887 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 888 .clksel = dpll4_clksel, 889 .clkdm_name = "dpll4_clkdm", 890 .recalc = &omap2_clksel_recalc, 891}; 892 893/* The PWRDN bit is apparently only available on 3430ES2 and above */ 894static struct clk dpll4_m6x2_ck = { 895 .name = "dpll4_m6x2_ck", 896 .ops = &clkops_omap2_dflt_wait, 897 .parent = &dpll4_m6_ck, 898 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 899 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 900 .flags = INVERT_ENABLE, 901 .clkdm_name = "dpll4_clkdm", 902 .recalc = &omap3_clkoutx2_recalc, 903}; 904 905static struct clk emu_per_alwon_ck = { 906 .name = "emu_per_alwon_ck", 907 .ops = &clkops_null, 908 .parent = &dpll4_m6x2_ck, 909 .clkdm_name = "dpll4_clkdm", 910 .recalc = &followparent_recalc, 911}; 912 913/* DPLL5 */ 914/* Supplies 120MHz clock, USIM source clock */ 915/* Type: DPLL */ 916/* 3430ES2 only */ 917static struct dpll_data dpll5_dd = { 918 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), 919 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, 920 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, 921 .clk_bypass = &sys_ck, 922 .clk_ref = &sys_ck, 923 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, 924 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), 925 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, 926 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 927 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, 928 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, 929 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, 930 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), 931 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, 932 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 933 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, 934 .max_multiplier = OMAP3_MAX_DPLL_MULT, 935 .min_divider = 1, 936 .max_divider = OMAP3_MAX_DPLL_DIV, 937}; 938 939static struct clk dpll5_ck = { 940 .name = "dpll5_ck", 941 .ops = &clkops_omap3_noncore_dpll_ops, 942 .parent = &sys_ck, 943 .dpll_data = &dpll5_dd, 944 .round_rate = &omap2_dpll_round_rate, 945 .set_rate = &omap3_noncore_dpll_set_rate, 946 .clkdm_name = "dpll5_clkdm", 947 .recalc = &omap3_dpll_recalc, 948}; 949 950static const struct clksel div16_dpll5_clksel[] = { 951 { .parent = &dpll5_ck, .rates = div16_dpll_rates }, 952 { .parent = NULL } 953}; 954 955static struct clk dpll5_m2_ck = { 956 .name = "dpll5_m2_ck", 957 .ops = &clkops_null, 958 .parent = &dpll5_ck, 959 .init = &omap2_init_clksel_parent, 960 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 961 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 962 .clksel = div16_dpll5_clksel, 963 .clkdm_name = "dpll5_clkdm", 964 .recalc = &omap2_clksel_recalc, 965}; 966 967/* CM EXTERNAL CLOCK OUTPUTS */ 968 969static const struct clksel_rate clkout2_src_core_rates[] = { 970 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 971 { .div = 0 } 972}; 973 974static const struct clksel_rate clkout2_src_sys_rates[] = { 975 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 976 { .div = 0 } 977}; 978 979static const struct clksel_rate clkout2_src_96m_rates[] = { 980 { .div = 1, .val = 2, .flags = RATE_IN_3XXX }, 981 { .div = 0 } 982}; 983 984static const struct clksel_rate clkout2_src_54m_rates[] = { 985 { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, 986 { .div = 0 } 987}; 988 989static const struct clksel clkout2_src_clksel[] = { 990 { .parent = &core_ck, .rates = clkout2_src_core_rates }, 991 { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, 992 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, 993 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, 994 { .parent = NULL } 995}; 996 997static struct clk clkout2_src_ck = { 998 .name = "clkout2_src_ck", 999 .ops = &clkops_omap2_dflt, 1000 .init = &omap2_init_clksel_parent, 1001 .enable_reg = OMAP3430_CM_CLKOUT_CTRL, 1002 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, 1003 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 1004 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, 1005 .clksel = clkout2_src_clksel, 1006 .clkdm_name = "core_clkdm", 1007 .recalc = &omap2_clksel_recalc, 1008}; 1009 1010static const struct clksel_rate sys_clkout2_rates[] = { 1011 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 1012 { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, 1013 { .div = 4, .val = 2, .flags = RATE_IN_3XXX }, 1014 { .div = 8, .val = 3, .flags = RATE_IN_3XXX }, 1015 { .div = 16, .val = 4, .flags = RATE_IN_3XXX }, 1016 { .div = 0 }, 1017}; 1018 1019static const struct clksel sys_clkout2_clksel[] = { 1020 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, 1021 { .parent = NULL }, 1022}; 1023 1024static struct clk sys_clkout2 = { 1025 .name = "sys_clkout2", 1026 .ops = &clkops_null, 1027 .init = &omap2_init_clksel_parent, 1028 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 1029 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 1030 .clksel = sys_clkout2_clksel, 1031 .recalc = &omap2_clksel_recalc, 1032 .round_rate = &omap2_clksel_round_rate, 1033 .set_rate = &omap2_clksel_set_rate 1034}; 1035 1036/* CM OUTPUT CLOCKS */ 1037 1038static struct clk corex2_fck = { 1039 .name = "corex2_fck", 1040 .ops = &clkops_null, 1041 .parent = &dpll3_m2x2_ck, 1042 .recalc = &followparent_recalc, 1043}; 1044 1045/* DPLL power domain clock controls */ 1046 1047static const struct clksel_rate div4_rates[] = { 1048 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 1049 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 1050 { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, 1051 { .div = 0 } 1052}; 1053 1054static const struct clksel div4_core_clksel[] = { 1055 { .parent = &core_ck, .rates = div4_rates }, 1056 { .parent = NULL } 1057}; 1058 1059/* 1060 * REVISIT: Are these in DPLL power domain or CM power domain? docs 1061 * may be inconsistent here? 1062 */ 1063static struct clk dpll1_fck = { 1064 .name = "dpll1_fck", 1065 .ops = &clkops_null, 1066 .parent = &core_ck, 1067 .init = &omap2_init_clksel_parent, 1068 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 1069 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, 1070 .clksel = div4_core_clksel, 1071 .recalc = &omap2_clksel_recalc, 1072}; 1073 1074static struct clk mpu_ck = { 1075 .name = "mpu_ck", 1076 .ops = &clkops_null, 1077 .parent = &dpll1_x2m2_ck, 1078 .clkdm_name = "mpu_clkdm", 1079 .recalc = &followparent_recalc, 1080}; 1081 1082/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1083static const struct clksel_rate arm_fck_rates[] = { 1084 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 1085 { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, 1086 { .div = 0 }, 1087}; 1088 1089static const struct clksel arm_fck_clksel[] = { 1090 { .parent = &mpu_ck, .rates = arm_fck_rates }, 1091 { .parent = NULL } 1092}; 1093 1094static struct clk arm_fck = { 1095 .name = "arm_fck", 1096 .ops = &clkops_null, 1097 .parent = &mpu_ck, 1098 .init = &omap2_init_clksel_parent, 1099 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1100 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1101 .clksel = arm_fck_clksel, 1102 .clkdm_name = "mpu_clkdm", 1103 .recalc = &omap2_clksel_recalc, 1104}; 1105 1106/* XXX What about neon_clkdm ? */ 1107 1108/* 1109 * REVISIT: This clock is never specifically defined in the 3430 TRM, 1110 * although it is referenced - so this is a guess 1111 */ 1112static struct clk emu_mpu_alwon_ck = { 1113 .name = "emu_mpu_alwon_ck", 1114 .ops = &clkops_null, 1115 .parent = &mpu_ck, 1116 .recalc = &followparent_recalc, 1117}; 1118 1119static struct clk dpll2_fck = { 1120 .name = "dpll2_fck", 1121 .ops = &clkops_null, 1122 .parent = &core_ck, 1123 .init = &omap2_init_clksel_parent, 1124 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 1125 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, 1126 .clksel = div4_core_clksel, 1127 .recalc = &omap2_clksel_recalc, 1128}; 1129 1130static struct clk iva2_ck = { 1131 .name = "iva2_ck", 1132 .ops = &clkops_omap2_dflt_wait, 1133 .parent = &dpll2_m2_ck, 1134 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1135 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1136 .clkdm_name = "iva2_clkdm", 1137 .recalc = &followparent_recalc, 1138}; 1139 1140/* Common interface clocks */ 1141 1142static const struct clksel div2_core_clksel[] = { 1143 { .parent = &core_ck, .rates = div2_rates }, 1144 { .parent = NULL } 1145}; 1146 1147static struct clk l3_ick = { 1148 .name = "l3_ick", 1149 .ops = &clkops_null, 1150 .parent = &core_ck, 1151 .init = &omap2_init_clksel_parent, 1152 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1153 .clksel_mask = OMAP3430_CLKSEL_L3_MASK, 1154 .clksel = div2_core_clksel, 1155 .clkdm_name = "core_l3_clkdm", 1156 .recalc = &omap2_clksel_recalc, 1157}; 1158 1159static const struct clksel div2_l3_clksel[] = { 1160 { .parent = &l3_ick, .rates = div2_rates }, 1161 { .parent = NULL } 1162}; 1163 1164static struct clk l4_ick = { 1165 .name = "l4_ick", 1166 .ops = &clkops_null, 1167 .parent = &l3_ick, 1168 .init = &omap2_init_clksel_parent, 1169 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1170 .clksel_mask = OMAP3430_CLKSEL_L4_MASK, 1171 .clksel = div2_l3_clksel, 1172 .clkdm_name = "core_l4_clkdm", 1173 .recalc = &omap2_clksel_recalc, 1174 1175}; 1176 1177static const struct clksel div2_l4_clksel[] = { 1178 { .parent = &l4_ick, .rates = div2_rates }, 1179 { .parent = NULL } 1180}; 1181 1182static struct clk rm_ick = { 1183 .name = "rm_ick", 1184 .ops = &clkops_null, 1185 .parent = &l4_ick, 1186 .init = &omap2_init_clksel_parent, 1187 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 1188 .clksel_mask = OMAP3430_CLKSEL_RM_MASK, 1189 .clksel = div2_l4_clksel, 1190 .recalc = &omap2_clksel_recalc, 1191}; 1192 1193/* GFX power domain */ 1194 1195/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ 1196 1197static const struct clksel gfx_l3_clksel[] = { 1198 { .parent = &l3_ick, .rates = gfx_l3_rates }, 1199 { .parent = NULL } 1200}; 1201 1202/* 1203 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck 1204 * This interface clock does not have a CM_AUTOIDLE bit 1205 */ 1206static struct clk gfx_l3_ck = { 1207 .name = "gfx_l3_ck", 1208 .ops = &clkops_omap2_dflt_wait, 1209 .parent = &l3_ick, 1210 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1211 .enable_bit = OMAP_EN_GFX_SHIFT, 1212 .recalc = &followparent_recalc, 1213}; 1214 1215static struct clk gfx_l3_fck = { 1216 .name = "gfx_l3_fck", 1217 .ops = &clkops_null, 1218 .parent = &gfx_l3_ck, 1219 .init = &omap2_init_clksel_parent, 1220 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1221 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1222 .clksel = gfx_l3_clksel, 1223 .clkdm_name = "gfx_3430es1_clkdm", 1224 .recalc = &omap2_clksel_recalc, 1225}; 1226 1227static struct clk gfx_l3_ick = { 1228 .name = "gfx_l3_ick", 1229 .ops = &clkops_null, 1230 .parent = &gfx_l3_ck, 1231 .clkdm_name = "gfx_3430es1_clkdm", 1232 .recalc = &followparent_recalc, 1233}; 1234 1235static struct clk gfx_cg1_ck = { 1236 .name = "gfx_cg1_ck", 1237 .ops = &clkops_omap2_dflt_wait, 1238 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1240 .enable_bit = OMAP3430ES1_EN_2D_SHIFT, 1241 .clkdm_name = "gfx_3430es1_clkdm", 1242 .recalc = &followparent_recalc, 1243}; 1244 1245static struct clk gfx_cg2_ck = { 1246 .name = "gfx_cg2_ck", 1247 .ops = &clkops_omap2_dflt_wait, 1248 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1249 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1250 .enable_bit = OMAP3430ES1_EN_3D_SHIFT, 1251 .clkdm_name = "gfx_3430es1_clkdm", 1252 .recalc = &followparent_recalc, 1253}; 1254 1255/* SGX power domain - 3430ES2 only */ 1256 1257static const struct clksel_rate sgx_core_rates[] = { 1258 { .div = 2, .val = 5, .flags = RATE_IN_36XX }, 1259 { .div = 3, .val = 0, .flags = RATE_IN_3XXX }, 1260 { .div = 4, .val = 1, .flags = RATE_IN_3XXX }, 1261 { .div = 6, .val = 2, .flags = RATE_IN_3XXX }, 1262 { .div = 0 }, 1263}; 1264 1265static const struct clksel_rate sgx_192m_rates[] = { 1266 { .div = 1, .val = 4, .flags = RATE_IN_36XX }, 1267 { .div = 0 }, 1268}; 1269 1270static const struct clksel_rate sgx_corex2_rates[] = { 1271 { .div = 3, .val = 6, .flags = RATE_IN_36XX }, 1272 { .div = 5, .val = 7, .flags = RATE_IN_36XX }, 1273 { .div = 0 }, 1274}; 1275 1276static const struct clksel_rate sgx_96m_rates[] = { 1277 { .div = 1, .val = 3, .flags = RATE_IN_3XXX }, 1278 { .div = 0 }, 1279}; 1280 1281static const struct clksel sgx_clksel[] = { 1282 { .parent = &core_ck, .rates = sgx_core_rates }, 1283 { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, 1284 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, 1285 { .parent = &corex2_fck, .rates = sgx_corex2_rates }, 1286 { .parent = NULL } 1287}; 1288 1289static struct clk sgx_fck = { 1290 .name = "sgx_fck", 1291 .ops = &clkops_omap2_dflt_wait, 1292 .init = &omap2_init_clksel_parent, 1293 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), 1294 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, 1295 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), 1296 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, 1297 .clksel = sgx_clksel, 1298 .clkdm_name = "sgx_clkdm", 1299 .recalc = &omap2_clksel_recalc, 1300 .set_rate = &omap2_clksel_set_rate, 1301 .round_rate = &omap2_clksel_round_rate 1302}; 1303 1304/* This interface clock does not have a CM_AUTOIDLE bit */ 1305static struct clk sgx_ick = { 1306 .name = "sgx_ick", 1307 .ops = &clkops_omap2_dflt_wait, 1308 .parent = &l3_ick, 1309 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1310 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, 1311 .clkdm_name = "sgx_clkdm", 1312 .recalc = &followparent_recalc, 1313}; 1314 1315/* CORE power domain */ 1316 1317static struct clk d2d_26m_fck = { 1318 .name = "d2d_26m_fck", 1319 .ops = &clkops_omap2_dflt_wait, 1320 .parent = &sys_ck, 1321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1322 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, 1323 .clkdm_name = "d2d_clkdm", 1324 .recalc = &followparent_recalc, 1325}; 1326 1327static struct clk modem_fck = { 1328 .name = "modem_fck", 1329 .ops = &clkops_omap2_mdmclk_dflt_wait, 1330 .parent = &sys_ck, 1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT, 1333 .clkdm_name = "d2d_clkdm", 1334 .recalc = &followparent_recalc, 1335}; 1336 1337static struct clk sad2d_ick = { 1338 .name = "sad2d_ick", 1339 .ops = &clkops_omap2_iclk_dflt_wait, 1340 .parent = &l3_ick, 1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT, 1343 .clkdm_name = "d2d_clkdm", 1344 .recalc = &followparent_recalc, 1345}; 1346 1347static struct clk mad2d_ick = { 1348 .name = "mad2d_ick", 1349 .ops = &clkops_omap2_iclk_dflt_wait, 1350 .parent = &l3_ick, 1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT, 1353 .clkdm_name = "d2d_clkdm", 1354 .recalc = &followparent_recalc, 1355}; 1356 1357static const struct clksel omap343x_gpt_clksel[] = { 1358 { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, 1359 { .parent = &sys_ck, .rates = gpt_sys_rates }, 1360 { .parent = NULL} 1361}; 1362 1363static struct clk gpt10_fck = { 1364 .name = "gpt10_fck", 1365 .ops = &clkops_omap2_dflt_wait, 1366 .parent = &sys_ck, 1367 .init = &omap2_init_clksel_parent, 1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1369 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1370 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1371 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, 1372 .clksel = omap343x_gpt_clksel, 1373 .clkdm_name = "core_l4_clkdm", 1374 .recalc = &omap2_clksel_recalc, 1375}; 1376 1377static struct clk gpt11_fck = { 1378 .name = "gpt11_fck", 1379 .ops = &clkops_omap2_dflt_wait, 1380 .parent = &sys_ck, 1381 .init = &omap2_init_clksel_parent, 1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1383 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1384 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1385 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, 1386 .clksel = omap343x_gpt_clksel, 1387 .clkdm_name = "core_l4_clkdm", 1388 .recalc = &omap2_clksel_recalc, 1389}; 1390 1391static struct clk cpefuse_fck = { 1392 .name = "cpefuse_fck", 1393 .ops = &clkops_omap2_dflt, 1394 .parent = &sys_ck, 1395 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1396 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, 1397 .recalc = &followparent_recalc, 1398}; 1399 1400static struct clk ts_fck = { 1401 .name = "ts_fck", 1402 .ops = &clkops_omap2_dflt, 1403 .parent = &omap_32k_fck, 1404 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1405 .enable_bit = OMAP3430ES2_EN_TS_SHIFT, 1406 .recalc = &followparent_recalc, 1407}; 1408 1409static struct clk usbtll_fck = { 1410 .name = "usbtll_fck", 1411 .ops = &clkops_omap2_dflt_wait, 1412 .parent = &dpll5_m2_ck, 1413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1414 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1415 .recalc = &followparent_recalc, 1416}; 1417 1418/* CORE 96M FCLK-derived clocks */ 1419 1420static struct clk core_96m_fck = { 1421 .name = "core_96m_fck", 1422 .ops = &clkops_null, 1423 .parent = &omap_96m_fck, 1424 .clkdm_name = "core_l4_clkdm", 1425 .recalc = &followparent_recalc, 1426}; 1427 1428static struct clk mmchs3_fck = { 1429 .name = "mmchs3_fck", 1430 .ops = &clkops_omap2_dflt_wait, 1431 .parent = &core_96m_fck, 1432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1433 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1434 .clkdm_name = "core_l4_clkdm", 1435 .recalc = &followparent_recalc, 1436}; 1437 1438static struct clk mmchs2_fck = { 1439 .name = "mmchs2_fck", 1440 .ops = &clkops_omap2_dflt_wait, 1441 .parent = &core_96m_fck, 1442 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1443 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1444 .clkdm_name = "core_l4_clkdm", 1445 .recalc = &followparent_recalc, 1446}; 1447 1448static struct clk mspro_fck = { 1449 .name = "mspro_fck", 1450 .ops = &clkops_omap2_dflt_wait, 1451 .parent = &core_96m_fck, 1452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1453 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1454 .clkdm_name = "core_l4_clkdm", 1455 .recalc = &followparent_recalc, 1456}; 1457 1458static struct clk mmchs1_fck = { 1459 .name = "mmchs1_fck", 1460 .ops = &clkops_omap2_dflt_wait, 1461 .parent = &core_96m_fck, 1462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1463 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1464 .clkdm_name = "core_l4_clkdm", 1465 .recalc = &followparent_recalc, 1466}; 1467 1468static struct clk i2c3_fck = { 1469 .name = "i2c3_fck", 1470 .ops = &clkops_omap2_dflt_wait, 1471 .parent = &core_96m_fck, 1472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1473 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1474 .clkdm_name = "core_l4_clkdm", 1475 .recalc = &followparent_recalc, 1476}; 1477 1478static struct clk i2c2_fck = { 1479 .name = "i2c2_fck", 1480 .ops = &clkops_omap2_dflt_wait, 1481 .parent = &core_96m_fck, 1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1483 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1484 .clkdm_name = "core_l4_clkdm", 1485 .recalc = &followparent_recalc, 1486}; 1487 1488static struct clk i2c1_fck = { 1489 .name = "i2c1_fck", 1490 .ops = &clkops_omap2_dflt_wait, 1491 .parent = &core_96m_fck, 1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1493 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1494 .clkdm_name = "core_l4_clkdm", 1495 .recalc = &followparent_recalc, 1496}; 1497 1498/* 1499 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; 1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. 1501 */ 1502static const struct clksel_rate common_mcbsp_96m_rates[] = { 1503 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 1504 { .div = 0 } 1505}; 1506 1507static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { 1508 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 1509 { .div = 0 } 1510}; 1511 1512static const struct clksel mcbsp_15_clksel[] = { 1513 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, 1514 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 1515 { .parent = NULL } 1516}; 1517 1518static struct clk mcbsp5_fck = { 1519 .name = "mcbsp5_fck", 1520 .ops = &clkops_omap2_dflt_wait, 1521 .init = &omap2_init_clksel_parent, 1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1523 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1524 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 1525 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, 1526 .clksel = mcbsp_15_clksel, 1527 .clkdm_name = "core_l4_clkdm", 1528 .recalc = &omap2_clksel_recalc, 1529}; 1530 1531static struct clk mcbsp1_fck = { 1532 .name = "mcbsp1_fck", 1533 .ops = &clkops_omap2_dflt_wait, 1534 .init = &omap2_init_clksel_parent, 1535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1536 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1537 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 1538 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, 1539 .clksel = mcbsp_15_clksel, 1540 .clkdm_name = "core_l4_clkdm", 1541 .recalc = &omap2_clksel_recalc, 1542}; 1543 1544/* CORE_48M_FCK-derived clocks */ 1545 1546static struct clk core_48m_fck = { 1547 .name = "core_48m_fck", 1548 .ops = &clkops_null, 1549 .parent = &omap_48m_fck, 1550 .clkdm_name = "core_l4_clkdm", 1551 .recalc = &followparent_recalc, 1552}; 1553 1554static struct clk mcspi4_fck = { 1555 .name = "mcspi4_fck", 1556 .ops = &clkops_omap2_dflt_wait, 1557 .parent = &core_48m_fck, 1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1559 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1560 .recalc = &followparent_recalc, 1561 .clkdm_name = "core_l4_clkdm", 1562}; 1563 1564static struct clk mcspi3_fck = { 1565 .name = "mcspi3_fck", 1566 .ops = &clkops_omap2_dflt_wait, 1567 .parent = &core_48m_fck, 1568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1569 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1570 .recalc = &followparent_recalc, 1571 .clkdm_name = "core_l4_clkdm", 1572}; 1573 1574static struct clk mcspi2_fck = { 1575 .name = "mcspi2_fck", 1576 .ops = &clkops_omap2_dflt_wait, 1577 .parent = &core_48m_fck, 1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1579 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1580 .recalc = &followparent_recalc, 1581 .clkdm_name = "core_l4_clkdm", 1582}; 1583 1584static struct clk mcspi1_fck = { 1585 .name = "mcspi1_fck", 1586 .ops = &clkops_omap2_dflt_wait, 1587 .parent = &core_48m_fck, 1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1589 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1590 .recalc = &followparent_recalc, 1591 .clkdm_name = "core_l4_clkdm", 1592}; 1593 1594static struct clk uart2_fck = { 1595 .name = "uart2_fck", 1596 .ops = &clkops_omap2_dflt_wait, 1597 .parent = &core_48m_fck, 1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1599 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1600 .clkdm_name = "core_l4_clkdm", 1601 .recalc = &followparent_recalc, 1602}; 1603 1604static struct clk uart1_fck = { 1605 .name = "uart1_fck", 1606 .ops = &clkops_omap2_dflt_wait, 1607 .parent = &core_48m_fck, 1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1609 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1610 .clkdm_name = "core_l4_clkdm", 1611 .recalc = &followparent_recalc, 1612}; 1613 1614static struct clk fshostusb_fck = { 1615 .name = "fshostusb_fck", 1616 .ops = &clkops_omap2_dflt_wait, 1617 .parent = &core_48m_fck, 1618 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1619 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, 1620 .recalc = &followparent_recalc, 1621}; 1622 1623/* CORE_12M_FCK based clocks */ 1624 1625static struct clk core_12m_fck = { 1626 .name = "core_12m_fck", 1627 .ops = &clkops_null, 1628 .parent = &omap_12m_fck, 1629 .clkdm_name = "core_l4_clkdm", 1630 .recalc = &followparent_recalc, 1631}; 1632 1633static struct clk hdq_fck = { 1634 .name = "hdq_fck", 1635 .ops = &clkops_omap2_dflt_wait, 1636 .parent = &core_12m_fck, 1637 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1638 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1639 .recalc = &followparent_recalc, 1640}; 1641 1642/* DPLL3-derived clock */ 1643 1644static const struct clksel_rate ssi_ssr_corex2_rates[] = { 1645 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 1646 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 1647 { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, 1648 { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, 1649 { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, 1650 { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, 1651 { .div = 0 } 1652}; 1653 1654static const struct clksel ssi_ssr_clksel[] = { 1655 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, 1656 { .parent = NULL } 1657}; 1658 1659static struct clk ssi_ssr_fck_3430es1 = { 1660 .name = "ssi_ssr_fck", 1661 .ops = &clkops_omap2_dflt, 1662 .init = &omap2_init_clksel_parent, 1663 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1664 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1665 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1666 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, 1667 .clksel = ssi_ssr_clksel, 1668 .clkdm_name = "core_l4_clkdm", 1669 .recalc = &omap2_clksel_recalc, 1670}; 1671 1672static struct clk ssi_ssr_fck_3430es2 = { 1673 .name = "ssi_ssr_fck", 1674 .ops …
Large files files are truncated, but you can click here to view the full file