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/arch/arm/mach-omap2/clockdomains44xx_data.c

https://github.com/AICP/kernel_asus_grouper
C | 691 lines | 628 code | 41 blank | 22 comment | 0 complexity | ed14f7c5d429a5b778ed277b0ddb0acb MD5 | raw file
  1/*
  2 * OMAP4 Clock domains framework
  3 *
  4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
  5 * Copyright (C) 2009-2011 Nokia Corporation
  6 *
  7 * Abhijit Pagare (abhijitpagare@ti.com)
  8 * Benoit Cousson (b-cousson@ti.com)
  9 * Paul Walmsley (paul@pwsan.com)
 10 *
 11 * This file is automatically generated from the OMAP hardware databases.
 12 * We respectfully ask that any modifications to this file be coordinated
 13 * with the public linux-omap@vger.kernel.org mailing list and the
 14 * authors above to ensure that the autogeneration scripts are kept
 15 * up-to-date with the file contents.
 16 *
 17 * This program is free software; you can redistribute it and/or modify
 18 * it under the terms of the GNU General Public License version 2 as
 19 * published by the Free Software Foundation.
 20 */
 21
 22#include <linux/kernel.h>
 23#include <linux/io.h>
 24
 25#include "clockdomain.h"
 26#include "cm1_44xx.h"
 27#include "cm2_44xx.h"
 28
 29#include "cm-regbits-44xx.h"
 30#include "prm44xx.h"
 31#include "prcm44xx.h"
 32#include "prcm_mpu44xx.h"
 33
 34/* Static Dependencies for OMAP4 Clock Domains */
 35
 36static struct clkdm_dep d2d_wkup_sleep_deps[] = {
 37	{
 38		.clkdm_name	 = "abe_clkdm",
 39		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 40	},
 41	{
 42		.clkdm_name	 = "ivahd_clkdm",
 43		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 44	},
 45	{
 46		.clkdm_name	 = "l3_1_clkdm",
 47		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 48	},
 49	{
 50		.clkdm_name	 = "l3_2_clkdm",
 51		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 52	},
 53	{
 54		.clkdm_name	 = "l3_emif_clkdm",
 55		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 56	},
 57	{
 58		.clkdm_name	 = "l3_init_clkdm",
 59		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 60	},
 61	{
 62		.clkdm_name	 = "l4_cfg_clkdm",
 63		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 64	},
 65	{
 66		.clkdm_name	 = "l4_per_clkdm",
 67		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 68	},
 69	{ NULL },
 70};
 71
 72static struct clkdm_dep ducati_wkup_sleep_deps[] = {
 73	{
 74		.clkdm_name	 = "abe_clkdm",
 75		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 76	},
 77	{
 78		.clkdm_name	 = "ivahd_clkdm",
 79		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 80	},
 81	{
 82		.clkdm_name	 = "l3_1_clkdm",
 83		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 84	},
 85	{
 86		.clkdm_name	 = "l3_2_clkdm",
 87		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 88	},
 89	{
 90		.clkdm_name	 = "l3_dss_clkdm",
 91		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 92	},
 93	{
 94		.clkdm_name	 = "l3_emif_clkdm",
 95		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
 96	},
 97	{
 98		.clkdm_name	 = "l3_gfx_clkdm",
 99		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
100	},
101	{
102		.clkdm_name	 = "l3_init_clkdm",
103		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
104	},
105	{
106		.clkdm_name	 = "l4_cfg_clkdm",
107		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
108	},
109	{
110		.clkdm_name	 = "l4_per_clkdm",
111		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
112	},
113	{
114		.clkdm_name	 = "l4_secure_clkdm",
115		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
116	},
117	{
118		.clkdm_name	 = "l4_wkup_clkdm",
119		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
120	},
121	{
122		.clkdm_name	 = "tesla_clkdm",
123		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
124	},
125	{ NULL },
126};
127
128static struct clkdm_dep iss_wkup_sleep_deps[] = {
129	{
130		.clkdm_name	 = "ivahd_clkdm",
131		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
132	},
133	{
134		.clkdm_name	 = "l3_1_clkdm",
135		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
136	},
137	{
138		.clkdm_name	 = "l3_emif_clkdm",
139		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
140	},
141	{ NULL },
142};
143
144static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
145	{
146		.clkdm_name	 = "l3_1_clkdm",
147		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
148	},
149	{
150		.clkdm_name	 = "l3_emif_clkdm",
151		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
152	},
153	{ NULL },
154};
155
156static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
157	{
158		.clkdm_name	 = "abe_clkdm",
159		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
160	},
161	{
162		.clkdm_name	 = "ducati_clkdm",
163		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
164	},
165	{
166		.clkdm_name	 = "ivahd_clkdm",
167		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
168	},
169	{
170		.clkdm_name	 = "l3_1_clkdm",
171		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
172	},
173	{
174		.clkdm_name	 = "l3_dss_clkdm",
175		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
176	},
177	{
178		.clkdm_name	 = "l3_emif_clkdm",
179		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
180	},
181	{
182		.clkdm_name	 = "l3_init_clkdm",
183		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
184	},
185	{
186		.clkdm_name	 = "l4_cfg_clkdm",
187		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
188	},
189	{
190		.clkdm_name	 = "l4_per_clkdm",
191		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
192	},
193	{
194		.clkdm_name	 = "l4_secure_clkdm",
195		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
196	},
197	{
198		.clkdm_name	 = "l4_wkup_clkdm",
199		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
200	},
201	{ NULL },
202};
203
204static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
205	{
206		.clkdm_name	 = "ivahd_clkdm",
207		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
208	},
209	{
210		.clkdm_name	 = "l3_2_clkdm",
211		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
212	},
213	{
214		.clkdm_name	 = "l3_emif_clkdm",
215		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
216	},
217	{ NULL },
218};
219
220static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
221	{
222		.clkdm_name	 = "ivahd_clkdm",
223		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
224	},
225	{
226		.clkdm_name	 = "l3_1_clkdm",
227		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
228	},
229	{
230		.clkdm_name	 = "l3_emif_clkdm",
231		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
232	},
233	{ NULL },
234};
235
236static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
237	{
238		.clkdm_name	 = "abe_clkdm",
239		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
240	},
241	{
242		.clkdm_name	 = "ivahd_clkdm",
243		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
244	},
245	{
246		.clkdm_name	 = "l3_emif_clkdm",
247		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
248	},
249	{
250		.clkdm_name	 = "l4_cfg_clkdm",
251		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
252	},
253	{
254		.clkdm_name	 = "l4_per_clkdm",
255		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
256	},
257	{
258		.clkdm_name	 = "l4_secure_clkdm",
259		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
260	},
261	{
262		.clkdm_name	 = "l4_wkup_clkdm",
263		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
264	},
265	{ NULL },
266};
267
268static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
269	{
270		.clkdm_name	 = "l3_1_clkdm",
271		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
272	},
273	{
274		.clkdm_name	 = "l3_emif_clkdm",
275		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
276	},
277	{
278		.clkdm_name	 = "l4_per_clkdm",
279		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
280	},
281	{ NULL },
282};
283
284static struct clkdm_dep mpu_wkup_sleep_deps[] = {
285	{
286		.clkdm_name	 = "abe_clkdm",
287		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
288	},
289	{
290		.clkdm_name	 = "ducati_clkdm",
291		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
292	},
293	{
294		.clkdm_name	 = "ivahd_clkdm",
295		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
296	},
297	{
298		.clkdm_name	 = "l3_1_clkdm",
299		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
300	},
301	{
302		.clkdm_name	 = "l3_2_clkdm",
303		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
304	},
305	{
306		.clkdm_name	 = "l3_dss_clkdm",
307		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
308	},
309	{
310		.clkdm_name	 = "l3_emif_clkdm",
311		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
312	},
313	{
314		.clkdm_name	 = "l3_gfx_clkdm",
315		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
316	},
317	{
318		.clkdm_name	 = "l3_init_clkdm",
319		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
320	},
321	{
322		.clkdm_name	 = "l4_cfg_clkdm",
323		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
324	},
325	{
326		.clkdm_name	 = "l4_per_clkdm",
327		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
328	},
329	{
330		.clkdm_name	 = "l4_secure_clkdm",
331		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
332	},
333	{
334		.clkdm_name	 = "l4_wkup_clkdm",
335		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
336	},
337	{
338		.clkdm_name	 = "tesla_clkdm",
339		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
340	},
341	{ NULL },
342};
343
344static struct clkdm_dep tesla_wkup_sleep_deps[] = {
345	{
346		.clkdm_name	 = "abe_clkdm",
347		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
348	},
349	{
350		.clkdm_name	 = "ivahd_clkdm",
351		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
352	},
353	{
354		.clkdm_name	 = "l3_1_clkdm",
355		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
356	},
357	{
358		.clkdm_name	 = "l3_2_clkdm",
359		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
360	},
361	{
362		.clkdm_name	 = "l3_emif_clkdm",
363		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
364	},
365	{
366		.clkdm_name	 = "l3_init_clkdm",
367		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
368	},
369	{
370		.clkdm_name	 = "l4_cfg_clkdm",
371		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
372	},
373	{
374		.clkdm_name	 = "l4_per_clkdm",
375		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
376	},
377	{
378		.clkdm_name	 = "l4_wkup_clkdm",
379		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
380	},
381	{ NULL },
382};
383
384static struct clockdomain l4_cefuse_44xx_clkdm = {
385	.name		  = "l4_cefuse_clkdm",
386	.pwrdm		  = { .name = "cefuse_pwrdm" },
387	.prcm_partition	  = OMAP4430_CM2_PARTITION,
388	.cm_inst	  = OMAP4430_CM2_CEFUSE_INST,
389	.clkdm_offs	  = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
390	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
391	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
392};
393
394static struct clockdomain l4_cfg_44xx_clkdm = {
395	.name		  = "l4_cfg_clkdm",
396	.pwrdm		  = { .name = "core_pwrdm" },
397	.prcm_partition	  = OMAP4430_CM2_PARTITION,
398	.cm_inst	  = OMAP4430_CM2_CORE_INST,
399	.clkdm_offs	  = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
400	.dep_bit	  = OMAP4430_L4CFG_STATDEP_SHIFT,
401	.flags		  = CLKDM_CAN_HWSUP,
402	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
403};
404
405static struct clockdomain tesla_44xx_clkdm = {
406	.name		  = "tesla_clkdm",
407	.pwrdm		  = { .name = "tesla_pwrdm" },
408	.prcm_partition	  = OMAP4430_CM1_PARTITION,
409	.cm_inst	  = OMAP4430_CM1_TESLA_INST,
410	.clkdm_offs	  = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
411	.dep_bit	  = OMAP4430_TESLA_STATDEP_SHIFT,
412	.wkdep_srcs	  = tesla_wkup_sleep_deps,
413	.sleepdep_srcs	  = tesla_wkup_sleep_deps,
414	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
415	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
416};
417
418static struct clockdomain l3_gfx_44xx_clkdm = {
419	.name		  = "l3_gfx_clkdm",
420	.pwrdm		  = { .name = "gfx_pwrdm" },
421	.prcm_partition	  = OMAP4430_CM2_PARTITION,
422	.cm_inst	  = OMAP4430_CM2_GFX_INST,
423	.clkdm_offs	  = OMAP4430_CM2_GFX_GFX_CDOFFS,
424	.dep_bit	  = OMAP4430_GFX_STATDEP_SHIFT,
425	.wkdep_srcs	  = l3_gfx_wkup_sleep_deps,
426	.sleepdep_srcs	  = l3_gfx_wkup_sleep_deps,
427	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
428	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
429};
430
431static struct clockdomain ivahd_44xx_clkdm = {
432	.name		  = "ivahd_clkdm",
433	.pwrdm		  = { .name = "ivahd_pwrdm" },
434	.prcm_partition	  = OMAP4430_CM2_PARTITION,
435	.cm_inst	  = OMAP4430_CM2_IVAHD_INST,
436	.clkdm_offs	  = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
437	.dep_bit	  = OMAP4430_IVAHD_STATDEP_SHIFT,
438	.wkdep_srcs	  = ivahd_wkup_sleep_deps,
439	.sleepdep_srcs	  = ivahd_wkup_sleep_deps,
440	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
441	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
442};
443
444static struct clockdomain l4_secure_44xx_clkdm = {
445	.name		  = "l4_secure_clkdm",
446	.pwrdm		  = { .name = "l4per_pwrdm" },
447	.prcm_partition	  = OMAP4430_CM2_PARTITION,
448	.cm_inst	  = OMAP4430_CM2_L4PER_INST,
449	.clkdm_offs	  = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
450	.dep_bit	  = OMAP4430_L4SEC_STATDEP_SHIFT,
451	.wkdep_srcs	  = l4_secure_wkup_sleep_deps,
452	.sleepdep_srcs	  = l4_secure_wkup_sleep_deps,
453	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
454	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
455};
456
457static struct clockdomain l4_per_44xx_clkdm = {
458	.name		  = "l4_per_clkdm",
459	.pwrdm		  = { .name = "l4per_pwrdm" },
460	.prcm_partition	  = OMAP4430_CM2_PARTITION,
461	.cm_inst	  = OMAP4430_CM2_L4PER_INST,
462	.clkdm_offs	  = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
463	.dep_bit	  = OMAP4430_L4PER_STATDEP_SHIFT,
464	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
465	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
466};
467
468static struct clockdomain abe_44xx_clkdm = {
469	.name		  = "abe_clkdm",
470	.pwrdm		  = { .name = "abe_pwrdm" },
471	.prcm_partition	  = OMAP4430_CM1_PARTITION,
472	.cm_inst	  = OMAP4430_CM1_ABE_INST,
473	.clkdm_offs	  = OMAP4430_CM1_ABE_ABE_CDOFFS,
474	.dep_bit	  = OMAP4430_ABE_STATDEP_SHIFT,
475	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
476	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
477};
478
479static struct clockdomain l3_instr_44xx_clkdm = {
480	.name		  = "l3_instr_clkdm",
481	.pwrdm		  = { .name = "core_pwrdm" },
482	.prcm_partition	  = OMAP4430_CM2_PARTITION,
483	.cm_inst	  = OMAP4430_CM2_CORE_INST,
484	.clkdm_offs	  = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
485	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
486};
487
488static struct clockdomain l3_init_44xx_clkdm = {
489	.name		  = "l3_init_clkdm",
490	.pwrdm		  = { .name = "l3init_pwrdm" },
491	.prcm_partition	  = OMAP4430_CM2_PARTITION,
492	.cm_inst	  = OMAP4430_CM2_L3INIT_INST,
493	.clkdm_offs	  = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
494	.dep_bit	  = OMAP4430_L3INIT_STATDEP_SHIFT,
495	.wkdep_srcs	  = l3_init_wkup_sleep_deps,
496	.sleepdep_srcs	  = l3_init_wkup_sleep_deps,
497	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
498	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
499};
500
501static struct clockdomain d2d_44xx_clkdm = {
502	.name		  = "d2d_clkdm",
503	.pwrdm		  = { .name = "core_pwrdm" },
504	.prcm_partition	  = OMAP4430_CM2_PARTITION,
505	.cm_inst	  = OMAP4430_CM2_CORE_INST,
506	.clkdm_offs	  = OMAP4430_CM2_CORE_D2D_CDOFFS,
507	.wkdep_srcs	  = d2d_wkup_sleep_deps,
508	.sleepdep_srcs	  = d2d_wkup_sleep_deps,
509	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
510	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
511};
512
513static struct clockdomain mpu0_44xx_clkdm = {
514	.name		  = "mpu0_clkdm",
515	.pwrdm		  = { .name = "cpu0_pwrdm" },
516	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
517	.cm_inst	  = OMAP4430_PRCM_MPU_CPU0_INST,
518	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
519	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
520	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
521};
522
523static struct clockdomain mpu1_44xx_clkdm = {
524	.name		  = "mpu1_clkdm",
525	.pwrdm		  = { .name = "cpu1_pwrdm" },
526	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
527	.cm_inst	  = OMAP4430_PRCM_MPU_CPU1_INST,
528	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
529	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
530	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
531};
532
533static struct clockdomain l3_emif_44xx_clkdm = {
534	.name		  = "l3_emif_clkdm",
535	.pwrdm		  = { .name = "core_pwrdm" },
536	.prcm_partition	  = OMAP4430_CM2_PARTITION,
537	.cm_inst	  = OMAP4430_CM2_CORE_INST,
538	.clkdm_offs	  = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
539	.dep_bit	  = OMAP4430_MEMIF_STATDEP_SHIFT,
540	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
541	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
542};
543
544static struct clockdomain l4_ao_44xx_clkdm = {
545	.name		  = "l4_ao_clkdm",
546	.pwrdm		  = { .name = "always_on_core_pwrdm" },
547	.prcm_partition	  = OMAP4430_CM2_PARTITION,
548	.cm_inst	  = OMAP4430_CM2_ALWAYS_ON_INST,
549	.clkdm_offs	  = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
550	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
551	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
552};
553
554static struct clockdomain ducati_44xx_clkdm = {
555	.name		  = "ducati_clkdm",
556	.pwrdm		  = { .name = "core_pwrdm" },
557	.prcm_partition	  = OMAP4430_CM2_PARTITION,
558	.cm_inst	  = OMAP4430_CM2_CORE_INST,
559	.clkdm_offs	  = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
560	.dep_bit	  = OMAP4430_DUCATI_STATDEP_SHIFT,
561	.wkdep_srcs	  = ducati_wkup_sleep_deps,
562	.sleepdep_srcs	  = ducati_wkup_sleep_deps,
563	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
564	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
565};
566
567static struct clockdomain mpu_44xx_clkdm = {
568	.name		  = "mpuss_clkdm",
569	.pwrdm		  = { .name = "mpu_pwrdm" },
570	.prcm_partition	  = OMAP4430_CM1_PARTITION,
571	.cm_inst	  = OMAP4430_CM1_MPU_INST,
572	.clkdm_offs	  = OMAP4430_CM1_MPU_MPU_CDOFFS,
573	.wkdep_srcs	  = mpu_wkup_sleep_deps,
574	.sleepdep_srcs	  = mpu_wkup_sleep_deps,
575	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
576	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
577};
578
579static struct clockdomain l3_2_44xx_clkdm = {
580	.name		  = "l3_2_clkdm",
581	.pwrdm		  = { .name = "core_pwrdm" },
582	.prcm_partition	  = OMAP4430_CM2_PARTITION,
583	.cm_inst	  = OMAP4430_CM2_CORE_INST,
584	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_2_CDOFFS,
585	.dep_bit	  = OMAP4430_L3_2_STATDEP_SHIFT,
586	.flags		  = CLKDM_CAN_HWSUP,
587	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
588};
589
590static struct clockdomain l3_1_44xx_clkdm = {
591	.name		  = "l3_1_clkdm",
592	.pwrdm		  = { .name = "core_pwrdm" },
593	.prcm_partition	  = OMAP4430_CM2_PARTITION,
594	.cm_inst	  = OMAP4430_CM2_CORE_INST,
595	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_1_CDOFFS,
596	.dep_bit	  = OMAP4430_L3_1_STATDEP_SHIFT,
597	.flags		  = CLKDM_CAN_HWSUP,
598	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
599};
600
601static struct clockdomain iss_44xx_clkdm = {
602	.name		  = "iss_clkdm",
603	.pwrdm		  = { .name = "cam_pwrdm" },
604	.prcm_partition	  = OMAP4430_CM2_PARTITION,
605	.cm_inst	  = OMAP4430_CM2_CAM_INST,
606	.clkdm_offs	  = OMAP4430_CM2_CAM_CAM_CDOFFS,
607	.wkdep_srcs	  = iss_wkup_sleep_deps,
608	.sleepdep_srcs	  = iss_wkup_sleep_deps,
609	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
610	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
611};
612
613static struct clockdomain l3_dss_44xx_clkdm = {
614	.name		  = "l3_dss_clkdm",
615	.pwrdm		  = { .name = "dss_pwrdm" },
616	.prcm_partition	  = OMAP4430_CM2_PARTITION,
617	.cm_inst	  = OMAP4430_CM2_DSS_INST,
618	.clkdm_offs	  = OMAP4430_CM2_DSS_DSS_CDOFFS,
619	.dep_bit	  = OMAP4430_DSS_STATDEP_SHIFT,
620	.wkdep_srcs	  = l3_dss_wkup_sleep_deps,
621	.sleepdep_srcs	  = l3_dss_wkup_sleep_deps,
622	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
623	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
624};
625
626static struct clockdomain l4_wkup_44xx_clkdm = {
627	.name		  = "l4_wkup_clkdm",
628	.pwrdm		  = { .name = "wkup_pwrdm" },
629	.prcm_partition	  = OMAP4430_PRM_PARTITION,
630	.cm_inst	  = OMAP4430_PRM_WKUP_CM_INST,
631	.clkdm_offs	  = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
632	.dep_bit	  = OMAP4430_L4WKUP_STATDEP_SHIFT,
633	.flags		  = CLKDM_CAN_HWSUP,
634	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
635};
636
637static struct clockdomain emu_sys_44xx_clkdm = {
638	.name		  = "emu_sys_clkdm",
639	.pwrdm		  = { .name = "emu_pwrdm" },
640	.prcm_partition	  = OMAP4430_PRM_PARTITION,
641	.cm_inst	  = OMAP4430_PRM_EMU_CM_INST,
642	.clkdm_offs	  = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
643	.flags		  = CLKDM_CAN_HWSUP,
644	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
645};
646
647static struct clockdomain l3_dma_44xx_clkdm = {
648	.name		  = "l3_dma_clkdm",
649	.pwrdm		  = { .name = "core_pwrdm" },
650	.prcm_partition	  = OMAP4430_CM2_PARTITION,
651	.cm_inst	  = OMAP4430_CM2_CORE_INST,
652	.clkdm_offs	  = OMAP4430_CM2_CORE_SDMA_CDOFFS,
653	.wkdep_srcs	  = l3_dma_wkup_sleep_deps,
654	.sleepdep_srcs	  = l3_dma_wkup_sleep_deps,
655	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
656	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
657};
658
659/* As clockdomains are added or removed above, this list must also be changed */
660static struct clockdomain *clockdomains_omap44xx[] __initdata = {
661	&l4_cefuse_44xx_clkdm,
662	&l4_cfg_44xx_clkdm,
663	&tesla_44xx_clkdm,
664	&l3_gfx_44xx_clkdm,
665	&ivahd_44xx_clkdm,
666	&l4_secure_44xx_clkdm,
667	&l4_per_44xx_clkdm,
668	&abe_44xx_clkdm,
669	&l3_instr_44xx_clkdm,
670	&l3_init_44xx_clkdm,
671	&d2d_44xx_clkdm,
672	&mpu0_44xx_clkdm,
673	&mpu1_44xx_clkdm,
674	&l3_emif_44xx_clkdm,
675	&l4_ao_44xx_clkdm,
676	&ducati_44xx_clkdm,
677	&mpu_44xx_clkdm,
678	&l3_2_44xx_clkdm,
679	&l3_1_44xx_clkdm,
680	&iss_44xx_clkdm,
681	&l3_dss_44xx_clkdm,
682	&l4_wkup_44xx_clkdm,
683	&emu_sys_44xx_clkdm,
684	&l3_dma_44xx_clkdm,
685	NULL
686};
687
688void __init omap44xx_clockdomains_init(void)
689{
690	clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
691}