/arch/arm/mach-omap2/clockdomains44xx_data.c

https://github.com/AICP/kernel_asus_grouper · C · 691 lines · 628 code · 41 blank · 22 comment · 0 complexity · ed14f7c5d429a5b778ed277b0ddb0acb MD5 · raw file 

    

  1. /*
    2. 

  2.  * OMAP4 Clock domains framework
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2009-2011 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2009-2011 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Abhijit Pagare (abhijitpagare@ti.com)
    8. 

  8.  * Benoit Cousson (b-cousson@ti.com)
    9. 

  9.  * Paul Walmsley (paul@pwsan.com)
    10. 

  10.  *
    11. 

  11.  * This file is automatically generated from the OMAP hardware databases.
    12. 

  12.  * We respectfully ask that any modifications to this file be coordinated
    13. 

  13.  * with the public linux-omap@vger.kernel.org mailing list and the
    14. 

  14.  * authors above to ensure that the autogeneration scripts are kept
    15. 

  15.  * up-to-date with the file contents.
    16. 

  16.  *
    17. 

  17.  * This program is free software; you can redistribute it and/or modify
    18. 

  18.  * it under the terms of the GNU General Public License version 2 as
    19. 

  19.  * published by the Free Software Foundation.
    20. 

  20.  */
    21. 

  21. 

  22. #include <linux/kernel.h>
    23. 

  23. #include <linux/io.h>
    24. 

  24. 

  25. #include "clockdomain.h"
    26. 

  26. #include "cm1_44xx.h"
    27. 

  27. #include "cm2_44xx.h"
    28. 

  28. 

  29. #include "cm-regbits-44xx.h"
    30. 

  30. #include "prm44xx.h"
    31. 

  31. #include "prcm44xx.h"
    32. 

  32. #include "prcm_mpu44xx.h"
    33. 

  33. 

  34. /* Static Dependencies for OMAP4 Clock Domains */
    35. 

  35. 

  36. static struct clkdm_dep d2d_wkup_sleep_deps[] = {
    37. 

  37. 	{
    38. 

  38. 		.clkdm_name	 = "abe_clkdm",
    39. 

  39. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    40. 

  40. 	},
    41. 

  41. 	{
    42. 

  42. 		.clkdm_name	 = "ivahd_clkdm",
    43. 

  43. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    44. 

  44. 	},
    45. 

  45. 	{
    46. 

  46. 		.clkdm_name	 = "l3_1_clkdm",
    47. 

  47. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    48. 

  48. 	},
    49. 

  49. 	{
    50. 

  50. 		.clkdm_name	 = "l3_2_clkdm",
    51. 

  51. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    52. 

  52. 	},
    53. 

  53. 	{
    54. 

  54. 		.clkdm_name	 = "l3_emif_clkdm",
    55. 

  55. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    56. 

  56. 	},
    57. 

  57. 	{
    58. 

  58. 		.clkdm_name	 = "l3_init_clkdm",
    59. 

  59. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    60. 

  60. 	},
    61. 

  61. 	{
    62. 

  62. 		.clkdm_name	 = "l4_cfg_clkdm",
    63. 

  63. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    64. 

  64. 	},
    65. 

  65. 	{
    66. 

  66. 		.clkdm_name	 = "l4_per_clkdm",
    67. 

  67. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    68. 

  68. 	},
    69. 

  69. 	{ NULL },
    70. 

  70. };
    71. 

  71. 

  72. static struct clkdm_dep ducati_wkup_sleep_deps[] = {
    73. 

  73. 	{
    74. 

  74. 		.clkdm_name	 = "abe_clkdm",
    75. 

  75. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    76. 

  76. 	},
    77. 

  77. 	{
    78. 

  78. 		.clkdm_name	 = "ivahd_clkdm",
    79. 

  79. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    80. 

  80. 	},
    81. 

  81. 	{
    82. 

  82. 		.clkdm_name	 = "l3_1_clkdm",
    83. 

  83. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    84. 

  84. 	},
    85. 

  85. 	{
    86. 

  86. 		.clkdm_name	 = "l3_2_clkdm",
    87. 

  87. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    88. 

  88. 	},
    89. 

  89. 	{
    90. 

  90. 		.clkdm_name	 = "l3_dss_clkdm",
    91. 

  91. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    92. 

  92. 	},
    93. 

  93. 	{
    94. 

  94. 		.clkdm_name	 = "l3_emif_clkdm",
    95. 

  95. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    96. 

  96. 	},
    97. 

  97. 	{
    98. 

  98. 		.clkdm_name	 = "l3_gfx_clkdm",
    99. 

  99. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    100. 

  100. 	},
    101. 

  101. 	{
    102. 

  102. 		.clkdm_name	 = "l3_init_clkdm",
    103. 

  103. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    104. 

  104. 	},
    105. 

  105. 	{
    106. 

  106. 		.clkdm_name	 = "l4_cfg_clkdm",
    107. 

  107. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    108. 

  108. 	},
    109. 

  109. 	{
    110. 

  110. 		.clkdm_name	 = "l4_per_clkdm",
    111. 

  111. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    112. 

  112. 	},
    113. 

  113. 	{
    114. 

  114. 		.clkdm_name	 = "l4_secure_clkdm",
    115. 

  115. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    116. 

  116. 	},
    117. 

  117. 	{
    118. 

  118. 		.clkdm_name	 = "l4_wkup_clkdm",
    119. 

  119. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    120. 

  120. 	},
    121. 

  121. 	{
    122. 

  122. 		.clkdm_name	 = "tesla_clkdm",
    123. 

  123. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    124. 

  124. 	},
    125. 

  125. 	{ NULL },
    126. 

  126. };
    127. 

  127. 

  128. static struct clkdm_dep iss_wkup_sleep_deps[] = {
    129. 

  129. 	{
    130. 

  130. 		.clkdm_name	 = "ivahd_clkdm",
    131. 

  131. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    132. 

  132. 	},
    133. 

  133. 	{
    134. 

  134. 		.clkdm_name	 = "l3_1_clkdm",
    135. 

  135. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    136. 

  136. 	},
    137. 

  137. 	{
    138. 

  138. 		.clkdm_name	 = "l3_emif_clkdm",
    139. 

  139. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    140. 

  140. 	},
    141. 

  141. 	{ NULL },
    142. 

  142. };
    143. 

  143. 

  144. static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
    145. 

  145. 	{
    146. 

  146. 		.clkdm_name	 = "l3_1_clkdm",
    147. 

  147. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    148. 

  148. 	},
    149. 

  149. 	{
    150. 

  150. 		.clkdm_name	 = "l3_emif_clkdm",
    151. 

  151. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    152. 

  152. 	},
    153. 

  153. 	{ NULL },
    154. 

  154. };
    155. 

  155. 

  156. static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
    157. 

  157. 	{
    158. 

  158. 		.clkdm_name	 = "abe_clkdm",
    159. 

  159. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    160. 

  160. 	},
    161. 

  161. 	{
    162. 

  162. 		.clkdm_name	 = "ducati_clkdm",
    163. 

  163. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    164. 

  164. 	},
    165. 

  165. 	{
    166. 

  166. 		.clkdm_name	 = "ivahd_clkdm",
    167. 

  167. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    168. 

  168. 	},
    169. 

  169. 	{
    170. 

  170. 		.clkdm_name	 = "l3_1_clkdm",
    171. 

  171. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    172. 

  172. 	},
    173. 

  173. 	{
    174. 

  174. 		.clkdm_name	 = "l3_dss_clkdm",
    175. 

  175. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    176. 

  176. 	},
    177. 

  177. 	{
    178. 

  178. 		.clkdm_name	 = "l3_emif_clkdm",
    179. 

  179. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    180. 

  180. 	},
    181. 

  181. 	{
    182. 

  182. 		.clkdm_name	 = "l3_init_clkdm",
    183. 

  183. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    184. 

  184. 	},
    185. 

  185. 	{
    186. 

  186. 		.clkdm_name	 = "l4_cfg_clkdm",
    187. 

  187. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    188. 

  188. 	},
    189. 

  189. 	{
    190. 

  190. 		.clkdm_name	 = "l4_per_clkdm",
    191. 

  191. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    192. 

  192. 	},
    193. 

  193. 	{
    194. 

  194. 		.clkdm_name	 = "l4_secure_clkdm",
    195. 

  195. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    196. 

  196. 	},
    197. 

  197. 	{
    198. 

  198. 		.clkdm_name	 = "l4_wkup_clkdm",
    199. 

  199. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    200. 

  200. 	},
    201. 

  201. 	{ NULL },
    202. 

  202. };
    203. 

  203. 

  204. static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
    205. 

  205. 	{
    206. 

  206. 		.clkdm_name	 = "ivahd_clkdm",
    207. 

  207. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    208. 

  208. 	},
    209. 

  209. 	{
    210. 

  210. 		.clkdm_name	 = "l3_2_clkdm",
    211. 

  211. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    212. 

  212. 	},
    213. 

  213. 	{
    214. 

  214. 		.clkdm_name	 = "l3_emif_clkdm",
    215. 

  215. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    216. 

  216. 	},
    217. 

  217. 	{ NULL },
    218. 

  218. };
    219. 

  219. 

  220. static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
    221. 

  221. 	{
    222. 

  222. 		.clkdm_name	 = "ivahd_clkdm",
    223. 

  223. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    224. 

  224. 	},
    225. 

  225. 	{
    226. 

  226. 		.clkdm_name	 = "l3_1_clkdm",
    227. 

  227. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    228. 

  228. 	},
    229. 

  229. 	{
    230. 

  230. 		.clkdm_name	 = "l3_emif_clkdm",
    231. 

  231. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    232. 

  232. 	},
    233. 

  233. 	{ NULL },
    234. 

  234. };
    235. 

  235. 

  236. static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
    237. 

  237. 	{
    238. 

  238. 		.clkdm_name	 = "abe_clkdm",
    239. 

  239. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    240. 

  240. 	},
    241. 

  241. 	{
    242. 

  242. 		.clkdm_name	 = "ivahd_clkdm",
    243. 

  243. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    244. 

  244. 	},
    245. 

  245. 	{
    246. 

  246. 		.clkdm_name	 = "l3_emif_clkdm",
    247. 

  247. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    248. 

  248. 	},
    249. 

  249. 	{
    250. 

  250. 		.clkdm_name	 = "l4_cfg_clkdm",
    251. 

  251. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    252. 

  252. 	},
    253. 

  253. 	{
    254. 

  254. 		.clkdm_name	 = "l4_per_clkdm",
    255. 

  255. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    256. 

  256. 	},
    257. 

  257. 	{
    258. 

  258. 		.clkdm_name	 = "l4_secure_clkdm",
    259. 

  259. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    260. 

  260. 	},
    261. 

  261. 	{
    262. 

  262. 		.clkdm_name	 = "l4_wkup_clkdm",
    263. 

  263. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    264. 

  264. 	},
    265. 

  265. 	{ NULL },
    266. 

  266. };
    267. 

  267. 

  268. static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
    269. 

  269. 	{
    270. 

  270. 		.clkdm_name	 = "l3_1_clkdm",
    271. 

  271. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    272. 

  272. 	},
    273. 

  273. 	{
    274. 

  274. 		.clkdm_name	 = "l3_emif_clkdm",
    275. 

  275. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    276. 

  276. 	},
    277. 

  277. 	{
    278. 

  278. 		.clkdm_name	 = "l4_per_clkdm",
    279. 

  279. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    280. 

  280. 	},
    281. 

  281. 	{ NULL },
    282. 

  282. };
    283. 

  283. 

  284. static struct clkdm_dep mpu_wkup_sleep_deps[] = {
    285. 

  285. 	{
    286. 

  286. 		.clkdm_name	 = "abe_clkdm",
    287. 

  287. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    288. 

  288. 	},
    289. 

  289. 	{
    290. 

  290. 		.clkdm_name	 = "ducati_clkdm",
    291. 

  291. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    292. 

  292. 	},
    293. 

  293. 	{
    294. 

  294. 		.clkdm_name	 = "ivahd_clkdm",
    295. 

  295. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    296. 

  296. 	},
    297. 

  297. 	{
    298. 

  298. 		.clkdm_name	 = "l3_1_clkdm",
    299. 

  299. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    300. 

  300. 	},
    301. 

  301. 	{
    302. 

  302. 		.clkdm_name	 = "l3_2_clkdm",
    303. 

  303. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    304. 

  304. 	},
    305. 

  305. 	{
    306. 

  306. 		.clkdm_name	 = "l3_dss_clkdm",
    307. 

  307. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    308. 

  308. 	},
    309. 

  309. 	{
    310. 

  310. 		.clkdm_name	 = "l3_emif_clkdm",
    311. 

  311. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    312. 

  312. 	},
    313. 

  313. 	{
    314. 

  314. 		.clkdm_name	 = "l3_gfx_clkdm",
    315. 

  315. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    316. 

  316. 	},
    317. 

  317. 	{
    318. 

  318. 		.clkdm_name	 = "l3_init_clkdm",
    319. 

  319. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    320. 

  320. 	},
    321. 

  321. 	{
    322. 

  322. 		.clkdm_name	 = "l4_cfg_clkdm",
    323. 

  323. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    324. 

  324. 	},
    325. 

  325. 	{
    326. 

  326. 		.clkdm_name	 = "l4_per_clkdm",
    327. 

  327. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    328. 

  328. 	},
    329. 

  329. 	{
    330. 

  330. 		.clkdm_name	 = "l4_secure_clkdm",
    331. 

  331. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    332. 

  332. 	},
    333. 

  333. 	{
    334. 

  334. 		.clkdm_name	 = "l4_wkup_clkdm",
    335. 

  335. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    336. 

  336. 	},
    337. 

  337. 	{
    338. 

  338. 		.clkdm_name	 = "tesla_clkdm",
    339. 

  339. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    340. 

  340. 	},
    341. 

  341. 	{ NULL },
    342. 

  342. };
    343. 

  343. 

  344. static struct clkdm_dep tesla_wkup_sleep_deps[] = {
    345. 

  345. 	{
    346. 

  346. 		.clkdm_name	 = "abe_clkdm",
    347. 

  347. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    348. 

  348. 	},
    349. 

  349. 	{
    350. 

  350. 		.clkdm_name	 = "ivahd_clkdm",
    351. 

  351. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    352. 

  352. 	},
    353. 

  353. 	{
    354. 

  354. 		.clkdm_name	 = "l3_1_clkdm",
    355. 

  355. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    356. 

  356. 	},
    357. 

  357. 	{
    358. 

  358. 		.clkdm_name	 = "l3_2_clkdm",
    359. 

  359. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    360. 

  360. 	},
    361. 

  361. 	{
    362. 

  362. 		.clkdm_name	 = "l3_emif_clkdm",
    363. 

  363. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    364. 

  364. 	},
    365. 

  365. 	{
    366. 

  366. 		.clkdm_name	 = "l3_init_clkdm",
    367. 

  367. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    368. 

  368. 	},
    369. 

  369. 	{
    370. 

  370. 		.clkdm_name	 = "l4_cfg_clkdm",
    371. 

  371. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    372. 

  372. 	},
    373. 

  373. 	{
    374. 

  374. 		.clkdm_name	 = "l4_per_clkdm",
    375. 

  375. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    376. 

  376. 	},
    377. 

  377. 	{
    378. 

  378. 		.clkdm_name	 = "l4_wkup_clkdm",
    379. 

  379. 		.omap_chip	 = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
    380. 

  380. 	},
    381. 

  381. 	{ NULL },
    382. 

  382. };
    383. 

  383. 

  384. static struct clockdomain l4_cefuse_44xx_clkdm = {
    385. 

  385. 	.name		  = "l4_cefuse_clkdm",
    386. 

  386. 	.pwrdm		  = { .name = "cefuse_pwrdm" },
    387. 

  387. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    388. 

  388. 	.cm_inst	  = OMAP4430_CM2_CEFUSE_INST,
    389. 

  389. 	.clkdm_offs	  = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
    390. 

  390. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    391. 

  391. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    392. 

  392. };
    393. 

  393. 

  394. static struct clockdomain l4_cfg_44xx_clkdm = {
    395. 

  395. 	.name		  = "l4_cfg_clkdm",
    396. 

  396. 	.pwrdm		  = { .name = "core_pwrdm" },
    397. 

  397. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    398. 

  398. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    399. 

  399. 	.clkdm_offs	  = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
    400. 

  400. 	.dep_bit	  = OMAP4430_L4CFG_STATDEP_SHIFT,
    401. 

  401. 	.flags		  = CLKDM_CAN_HWSUP,
    402. 

  402. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    403. 

  403. };
    404. 

  404. 

  405. static struct clockdomain tesla_44xx_clkdm = {
    406. 

  406. 	.name		  = "tesla_clkdm",
    407. 

  407. 	.pwrdm		  = { .name = "tesla_pwrdm" },
    408. 

  408. 	.prcm_partition	  = OMAP4430_CM1_PARTITION,
    409. 

  409. 	.cm_inst	  = OMAP4430_CM1_TESLA_INST,
    410. 

  410. 	.clkdm_offs	  = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
    411. 

  411. 	.dep_bit	  = OMAP4430_TESLA_STATDEP_SHIFT,
    412. 

  412. 	.wkdep_srcs	  = tesla_wkup_sleep_deps,
    413. 

  413. 	.sleepdep_srcs	  = tesla_wkup_sleep_deps,
    414. 

  414. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    415. 

  415. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    416. 

  416. };
    417. 

  417. 

  418. static struct clockdomain l3_gfx_44xx_clkdm = {
    419. 

  419. 	.name		  = "l3_gfx_clkdm",
    420. 

  420. 	.pwrdm		  = { .name = "gfx_pwrdm" },
    421. 

  421. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    422. 

  422. 	.cm_inst	  = OMAP4430_CM2_GFX_INST,
    423. 

  423. 	.clkdm_offs	  = OMAP4430_CM2_GFX_GFX_CDOFFS,
    424. 

  424. 	.dep_bit	  = OMAP4430_GFX_STATDEP_SHIFT,
    425. 

  425. 	.wkdep_srcs	  = l3_gfx_wkup_sleep_deps,
    426. 

  426. 	.sleepdep_srcs	  = l3_gfx_wkup_sleep_deps,
    427. 

  427. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    428. 

  428. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    429. 

  429. };
    430. 

  430. 

  431. static struct clockdomain ivahd_44xx_clkdm = {
    432. 

  432. 	.name		  = "ivahd_clkdm",
    433. 

  433. 	.pwrdm		  = { .name = "ivahd_pwrdm" },
    434. 

  434. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    435. 

  435. 	.cm_inst	  = OMAP4430_CM2_IVAHD_INST,
    436. 

  436. 	.clkdm_offs	  = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
    437. 

  437. 	.dep_bit	  = OMAP4430_IVAHD_STATDEP_SHIFT,
    438. 

  438. 	.wkdep_srcs	  = ivahd_wkup_sleep_deps,
    439. 

  439. 	.sleepdep_srcs	  = ivahd_wkup_sleep_deps,
    440. 

  440. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    441. 

  441. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    442. 

  442. };
    443. 

  443. 

  444. static struct clockdomain l4_secure_44xx_clkdm = {
    445. 

  445. 	.name		  = "l4_secure_clkdm",
    446. 

  446. 	.pwrdm		  = { .name = "l4per_pwrdm" },
    447. 

  447. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    448. 

  448. 	.cm_inst	  = OMAP4430_CM2_L4PER_INST,
    449. 

  449. 	.clkdm_offs	  = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
    450. 

  450. 	.dep_bit	  = OMAP4430_L4SEC_STATDEP_SHIFT,
    451. 

  451. 	.wkdep_srcs	  = l4_secure_wkup_sleep_deps,
    452. 

  452. 	.sleepdep_srcs	  = l4_secure_wkup_sleep_deps,
    453. 

  453. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    454. 

  454. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    455. 

  455. };
    456. 

  456. 

  457. static struct clockdomain l4_per_44xx_clkdm = {
    458. 

  458. 	.name		  = "l4_per_clkdm",
    459. 

  459. 	.pwrdm		  = { .name = "l4per_pwrdm" },
    460. 

  460. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    461. 

  461. 	.cm_inst	  = OMAP4430_CM2_L4PER_INST,
    462. 

  462. 	.clkdm_offs	  = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
    463. 

  463. 	.dep_bit	  = OMAP4430_L4PER_STATDEP_SHIFT,
    464. 

  464. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    465. 

  465. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    466. 

  466. };
    467. 

  467. 

  468. static struct clockdomain abe_44xx_clkdm = {
    469. 

  469. 	.name		  = "abe_clkdm",
    470. 

  470. 	.pwrdm		  = { .name = "abe_pwrdm" },
    471. 

  471. 	.prcm_partition	  = OMAP4430_CM1_PARTITION,
    472. 

  472. 	.cm_inst	  = OMAP4430_CM1_ABE_INST,
    473. 

  473. 	.clkdm_offs	  = OMAP4430_CM1_ABE_ABE_CDOFFS,
    474. 

  474. 	.dep_bit	  = OMAP4430_ABE_STATDEP_SHIFT,
    475. 

  475. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    476. 

  476. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    477. 

  477. };
    478. 

  478. 

  479. static struct clockdomain l3_instr_44xx_clkdm = {
    480. 

  480. 	.name		  = "l3_instr_clkdm",
    481. 

  481. 	.pwrdm		  = { .name = "core_pwrdm" },
    482. 

  482. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    483. 

  483. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    484. 

  484. 	.clkdm_offs	  = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
    485. 

  485. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    486. 

  486. };
    487. 

  487. 

  488. static struct clockdomain l3_init_44xx_clkdm = {
    489. 

  489. 	.name		  = "l3_init_clkdm",
    490. 

  490. 	.pwrdm		  = { .name = "l3init_pwrdm" },
    491. 

  491. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    492. 

  492. 	.cm_inst	  = OMAP4430_CM2_L3INIT_INST,
    493. 

  493. 	.clkdm_offs	  = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
    494. 

  494. 	.dep_bit	  = OMAP4430_L3INIT_STATDEP_SHIFT,
    495. 

  495. 	.wkdep_srcs	  = l3_init_wkup_sleep_deps,
    496. 

  496. 	.sleepdep_srcs	  = l3_init_wkup_sleep_deps,
    497. 

  497. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    498. 

  498. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    499. 

  499. };
    500. 

  500. 

  501. static struct clockdomain d2d_44xx_clkdm = {
    502. 

  502. 	.name		  = "d2d_clkdm",
    503. 

  503. 	.pwrdm		  = { .name = "core_pwrdm" },
    504. 

  504. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    505. 

  505. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    506. 

  506. 	.clkdm_offs	  = OMAP4430_CM2_CORE_D2D_CDOFFS,
    507. 

  507. 	.wkdep_srcs	  = d2d_wkup_sleep_deps,
    508. 

  508. 	.sleepdep_srcs	  = d2d_wkup_sleep_deps,
    509. 

  509. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    510. 

  510. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    511. 

  511. };
    512. 

  512. 

  513. static struct clockdomain mpu0_44xx_clkdm = {
    514. 

  514. 	.name		  = "mpu0_clkdm",
    515. 

  515. 	.pwrdm		  = { .name = "cpu0_pwrdm" },
    516. 

  516. 	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
    517. 

  517. 	.cm_inst	  = OMAP4430_PRCM_MPU_CPU0_INST,
    518. 

  518. 	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
    519. 

  519. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    520. 

  520. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    521. 

  521. };
    522. 

  522. 

  523. static struct clockdomain mpu1_44xx_clkdm = {
    524. 

  524. 	.name		  = "mpu1_clkdm",
    525. 

  525. 	.pwrdm		  = { .name = "cpu1_pwrdm" },
    526. 

  526. 	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
    527. 

  527. 	.cm_inst	  = OMAP4430_PRCM_MPU_CPU1_INST,
    528. 

  528. 	.clkdm_offs	  = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
    529. 

  529. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    530. 

  530. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    531. 

  531. };
    532. 

  532. 

  533. static struct clockdomain l3_emif_44xx_clkdm = {
    534. 

  534. 	.name		  = "l3_emif_clkdm",
    535. 

  535. 	.pwrdm		  = { .name = "core_pwrdm" },
    536. 

  536. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    537. 

  537. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    538. 

  538. 	.clkdm_offs	  = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
    539. 

  539. 	.dep_bit	  = OMAP4430_MEMIF_STATDEP_SHIFT,
    540. 

  540. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    541. 

  541. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    542. 

  542. };
    543. 

  543. 

  544. static struct clockdomain l4_ao_44xx_clkdm = {
    545. 

  545. 	.name		  = "l4_ao_clkdm",
    546. 

  546. 	.pwrdm		  = { .name = "always_on_core_pwrdm" },
    547. 

  547. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    548. 

  548. 	.cm_inst	  = OMAP4430_CM2_ALWAYS_ON_INST,
    549. 

  549. 	.clkdm_offs	  = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
    550. 

  550. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    551. 

  551. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    552. 

  552. };
    553. 

  553. 

  554. static struct clockdomain ducati_44xx_clkdm = {
    555. 

  555. 	.name		  = "ducati_clkdm",
    556. 

  556. 	.pwrdm		  = { .name = "core_pwrdm" },
    557. 

  557. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    558. 

  558. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    559. 

  559. 	.clkdm_offs	  = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
    560. 

  560. 	.dep_bit	  = OMAP4430_DUCATI_STATDEP_SHIFT,
    561. 

  561. 	.wkdep_srcs	  = ducati_wkup_sleep_deps,
    562. 

  562. 	.sleepdep_srcs	  = ducati_wkup_sleep_deps,
    563. 

  563. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    564. 

  564. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    565. 

  565. };
    566. 

  566. 

  567. static struct clockdomain mpu_44xx_clkdm = {
    568. 

  568. 	.name		  = "mpuss_clkdm",
    569. 

  569. 	.pwrdm		  = { .name = "mpu_pwrdm" },
    570. 

  570. 	.prcm_partition	  = OMAP4430_CM1_PARTITION,
    571. 

  571. 	.cm_inst	  = OMAP4430_CM1_MPU_INST,
    572. 

  572. 	.clkdm_offs	  = OMAP4430_CM1_MPU_MPU_CDOFFS,
    573. 

  573. 	.wkdep_srcs	  = mpu_wkup_sleep_deps,
    574. 

  574. 	.sleepdep_srcs	  = mpu_wkup_sleep_deps,
    575. 

  575. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    576. 

  576. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    577. 

  577. };
    578. 

  578. 

  579. static struct clockdomain l3_2_44xx_clkdm = {
    580. 

  580. 	.name		  = "l3_2_clkdm",
    581. 

  581. 	.pwrdm		  = { .name = "core_pwrdm" },
    582. 

  582. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    583. 

  583. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    584. 

  584. 	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_2_CDOFFS,
    585. 

  585. 	.dep_bit	  = OMAP4430_L3_2_STATDEP_SHIFT,
    586. 

  586. 	.flags		  = CLKDM_CAN_HWSUP,
    587. 

  587. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    588. 

  588. };
    589. 

  589. 

  590. static struct clockdomain l3_1_44xx_clkdm = {
    591. 

  591. 	.name		  = "l3_1_clkdm",
    592. 

  592. 	.pwrdm		  = { .name = "core_pwrdm" },
    593. 

  593. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    594. 

  594. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    595. 

  595. 	.clkdm_offs	  = OMAP4430_CM2_CORE_L3_1_CDOFFS,
    596. 

  596. 	.dep_bit	  = OMAP4430_L3_1_STATDEP_SHIFT,
    597. 

  597. 	.flags		  = CLKDM_CAN_HWSUP,
    598. 

  598. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    599. 

  599. };
    600. 

  600. 

  601. static struct clockdomain iss_44xx_clkdm = {
    602. 

  602. 	.name		  = "iss_clkdm",
    603. 

  603. 	.pwrdm		  = { .name = "cam_pwrdm" },
    604. 

  604. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    605. 

  605. 	.cm_inst	  = OMAP4430_CM2_CAM_INST,
    606. 

  606. 	.clkdm_offs	  = OMAP4430_CM2_CAM_CAM_CDOFFS,
    607. 

  607. 	.wkdep_srcs	  = iss_wkup_sleep_deps,
    608. 

  608. 	.sleepdep_srcs	  = iss_wkup_sleep_deps,
    609. 

  609. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    610. 

  610. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    611. 

  611. };
    612. 

  612. 

  613. static struct clockdomain l3_dss_44xx_clkdm = {
    614. 

  614. 	.name		  = "l3_dss_clkdm",
    615. 

  615. 	.pwrdm		  = { .name = "dss_pwrdm" },
    616. 

  616. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    617. 

  617. 	.cm_inst	  = OMAP4430_CM2_DSS_INST,
    618. 

  618. 	.clkdm_offs	  = OMAP4430_CM2_DSS_DSS_CDOFFS,
    619. 

  619. 	.dep_bit	  = OMAP4430_DSS_STATDEP_SHIFT,
    620. 

  620. 	.wkdep_srcs	  = l3_dss_wkup_sleep_deps,
    621. 

  621. 	.sleepdep_srcs	  = l3_dss_wkup_sleep_deps,
    622. 

  622. 	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
    623. 

  623. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    624. 

  624. };
    625. 

  625. 

  626. static struct clockdomain l4_wkup_44xx_clkdm = {
    627. 

  627. 	.name		  = "l4_wkup_clkdm",
    628. 

  628. 	.pwrdm		  = { .name = "wkup_pwrdm" },
    629. 

  629. 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
    630. 

  630. 	.cm_inst	  = OMAP4430_PRM_WKUP_CM_INST,
    631. 

  631. 	.clkdm_offs	  = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
    632. 

  632. 	.dep_bit	  = OMAP4430_L4WKUP_STATDEP_SHIFT,
    633. 

  633. 	.flags		  = CLKDM_CAN_HWSUP,
    634. 

  634. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    635. 

  635. };
    636. 

  636. 

  637. static struct clockdomain emu_sys_44xx_clkdm = {
    638. 

  638. 	.name		  = "emu_sys_clkdm",
    639. 

  639. 	.pwrdm		  = { .name = "emu_pwrdm" },
    640. 

  640. 	.prcm_partition	  = OMAP4430_PRM_PARTITION,
    641. 

  641. 	.cm_inst	  = OMAP4430_PRM_EMU_CM_INST,
    642. 

  642. 	.clkdm_offs	  = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
    643. 

  643. 	.flags		  = CLKDM_CAN_HWSUP,
    644. 

  644. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    645. 

  645. };
    646. 

  646. 

  647. static struct clockdomain l3_dma_44xx_clkdm = {
    648. 

  648. 	.name		  = "l3_dma_clkdm",
    649. 

  649. 	.pwrdm		  = { .name = "core_pwrdm" },
    650. 

  650. 	.prcm_partition	  = OMAP4430_CM2_PARTITION,
    651. 

  651. 	.cm_inst	  = OMAP4430_CM2_CORE_INST,
    652. 

  652. 	.clkdm_offs	  = OMAP4430_CM2_CORE_SDMA_CDOFFS,
    653. 

  653. 	.wkdep_srcs	  = l3_dma_wkup_sleep_deps,
    654. 

  654. 	.sleepdep_srcs	  = l3_dma_wkup_sleep_deps,
    655. 

  655. 	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
    656. 

  656. 	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
    657. 

  657. };
    658. 

  658. 

  659. /* As clockdomains are added or removed above, this list must also be changed */
    660. 

  660. static struct clockdomain *clockdomains_omap44xx[] __initdata = {
    661. 

  661. 	&l4_cefuse_44xx_clkdm,
    662. 

  662. 	&l4_cfg_44xx_clkdm,
    663. 

  663. 	&tesla_44xx_clkdm,
    664. 

  664. 	&l3_gfx_44xx_clkdm,
    665. 

  665. 	&ivahd_44xx_clkdm,
    666. 

  666. 	&l4_secure_44xx_clkdm,
    667. 

  667. 	&l4_per_44xx_clkdm,
    668. 

  668. 	&abe_44xx_clkdm,
    669. 

  669. 	&l3_instr_44xx_clkdm,
    670. 

  670. 	&l3_init_44xx_clkdm,
    671. 

  671. 	&d2d_44xx_clkdm,
    672. 

  672. 	&mpu0_44xx_clkdm,
    673. 

  673. 	&mpu1_44xx_clkdm,
    674. 

  674. 	&l3_emif_44xx_clkdm,
    675. 

  675. 	&l4_ao_44xx_clkdm,
    676. 

  676. 	&ducati_44xx_clkdm,
    677. 

  677. 	&mpu_44xx_clkdm,
    678. 

  678. 	&l3_2_44xx_clkdm,
    679. 

  679. 	&l3_1_44xx_clkdm,
    680. 

  680. 	&iss_44xx_clkdm,
    681. 

  681. 	&l3_dss_44xx_clkdm,
    682. 

  682. 	&l4_wkup_44xx_clkdm,
    683. 

  683. 	&emu_sys_44xx_clkdm,
    684. 

  684. 	&l3_dma_44xx_clkdm,
    685. 

  685. 	NULL
    686. 

  686. };
    687. 

  687. 

  688. void __init omap44xx_clockdomains_init(void)
    689. 

  689. {
    690. 

  690. 	clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
    691. 

  691. }
    692.