/arch/arm/mach-omap2/cm2xxx_3xxx.c

https://github.com/AICP/kernel_asus_grouper · C · 557 lines · 458 code · 51 blank · 48 comment · 10 complexity · 1d9ba8945a2315a60a392f2fb10ebea2 MD5 · raw file 

    

  1. /*
    2. 

  2.  * OMAP2/3 CM module functions
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2009 Nokia Corporation
    5. 

  5.  * Paul Walmsley
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or modify
    8. 

  8.  * it under the terms of the GNU General Public License version 2 as
    9. 

  9.  * published by the Free Software Foundation.
    10. 

  10.  */
    11. 

  11. 

  12. #include <linux/kernel.h>
    13. 

  13. #include <linux/types.h>
    14. 

  14. #include <linux/delay.h>
    15. 

  15. #include <linux/spinlock.h>
    16. 

  16. #include <linux/list.h>
    17. 

  17. #include <linux/errno.h>
    18. 

  18. #include <linux/err.h>
    19. 

  19. #include <linux/io.h>
    20. 

  20. 

  21. #include <plat/common.h>
    22. 

  22. 

  23. #include "cm.h"
    24. 

  24. #include "cm2xxx_3xxx.h"
    25. 

  25. #include "cm-regbits-24xx.h"
    26. 

  26. #include "cm-regbits-34xx.h"
    27. 

  27. 

  28. /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
    29. 

  29. #define DPLL_AUTOIDLE_DISABLE				0x0
    30. 

  30. #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP		0x3
    31. 

  31. 

  32. /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
    33. 

  33. #define OMAP2XXX_APLL_AUTOIDLE_DISABLE			0x0
    34. 

  34. #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP		0x3
    35. 

  35. 

  36. static const u8 cm_idlest_offs[] = {
    37. 

  37. 	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
    38. 

  38. };
    39. 

  39. 

  40. u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
    41. 

  41. {
    42. 

  42. 	return __raw_readl(cm_base + module + idx);
    43. 

  43. }
    44. 

  44. 

  45. void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
    46. 

  46. {
    47. 

  47. 	__raw_writel(val, cm_base + module + idx);
    48. 

  48. }
    49. 

  49. 

  50. /* Read-modify-write a register in a CM module. Caller must lock */
    51. 

  51. u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
    52. 

  52. {
    53. 

  53. 	u32 v;
    54. 

  54. 

  55. 	v = omap2_cm_read_mod_reg(module, idx);
    56. 

  56. 	v &= ~mask;
    57. 

  57. 	v |= bits;
    58. 

  58. 	omap2_cm_write_mod_reg(v, module, idx);
    59. 

  59. 

  60. 	return v;
    61. 

  61. }
    62. 

  62. 

  63. u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
    64. 

  64. {
    65. 

  65. 	return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
    66. 

  66. }
    67. 

  67. 

  68. u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
    69. 

  69. {
    70. 

  70. 	return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
    71. 

  71. }
    72. 

  72. 

  73. /*
    74. 

  74.  *
    75. 

  75.  */
    76. 

  76. 

  77. static void _write_clktrctrl(u8 c, s16 module, u32 mask)
    78. 

  78. {
    79. 

  79. 	u32 v;
    80. 

  80. 

  81. 	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
    82. 

  82. 	v &= ~mask;
    83. 

  83. 	v |= c << __ffs(mask);
    84. 

  84. 	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
    85. 

  85. }
    86. 

  86. 

  87. bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
    88. 

  88. {
    89. 

  89. 	u32 v;
    90. 

  90. 	bool ret = 0;
    91. 

  91. 

  92. 	BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
    93. 

  93. 

  94. 	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
    95. 

  95. 	v &= mask;
    96. 

  96. 	v >>= __ffs(mask);
    97. 

  97. 

  98. 	if (cpu_is_omap24xx())
    99. 

  99. 		ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
    100. 

  100. 	else
    101. 

  101. 		ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
    102. 

  102. 

  103. 	return ret;
    104. 

  104. }
    105. 

  105. 

  106. void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
    107. 

  107. {
    108. 

  108. 	_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
    109. 

  109. }
    110. 

  110. 

  111. void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
    112. 

  112. {
    113. 

  113. 	_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
    114. 

  114. }
    115. 

  115. 

  116. void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
    117. 

  117. {
    118. 

  118. 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
    119. 

  119. }
    120. 

  120. 

  121. void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
    122. 

  122. {
    123. 

  123. 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
    124. 

  124. }
    125. 

  125. 

  126. void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
    127. 

  127. {
    128. 

  128. 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
    129. 

  129. }
    130. 

  130. 

  131. void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
    132. 

  132. {
    133. 

  133. 	_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
    134. 

  134. }
    135. 

  135. 

  136. /*
    137. 

  137.  * DPLL autoidle control
    138. 

  138.  */
    139. 

  139. 

  140. static void _omap2xxx_set_dpll_autoidle(u8 m)
    141. 

  141. {
    142. 

  142. 	u32 v;
    143. 

  143. 

  144. 	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
    145. 

  145. 	v &= ~OMAP24XX_AUTO_DPLL_MASK;
    146. 

  146. 	v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
    147. 

  147. 	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
    148. 

  148. }
    149. 

  149. 

  150. void omap2xxx_cm_set_dpll_disable_autoidle(void)
    151. 

  151. {
    152. 

  152. 	_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
    153. 

  153. }
    154. 

  154. 

  155. void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
    156. 

  156. {
    157. 

  157. 	_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
    158. 

  158. }
    159. 

  159. 

  160. /*
    161. 

  161.  * APLL autoidle control
    162. 

  162.  */
    163. 

  163. 

  164. static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
    165. 

  165. {
    166. 

  166. 	u32 v;
    167. 

  167. 

  168. 	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
    169. 

  169. 	v &= ~mask;
    170. 

  170. 	v |= m << __ffs(mask);
    171. 

  171. 	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
    172. 

  172. }
    173. 

  173. 

  174. void omap2xxx_cm_set_apll54_disable_autoidle(void)
    175. 

  175. {
    176. 

  176. 	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
    177. 

  177. 				    OMAP24XX_AUTO_54M_MASK);
    178. 

  178. }
    179. 

  179. 

  180. void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
    181. 

  181. {
    182. 

  182. 	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
    183. 

  183. 				    OMAP24XX_AUTO_54M_MASK);
    184. 

  184. }
    185. 

  185. 

  186. void omap2xxx_cm_set_apll96_disable_autoidle(void)
    187. 

  187. {
    188. 

  188. 	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
    189. 

  189. 				    OMAP24XX_AUTO_96M_MASK);
    190. 

  190. }
    191. 

  191. 

  192. void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
    193. 

  193. {
    194. 

  194. 	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
    195. 

  195. 				    OMAP24XX_AUTO_96M_MASK);
    196. 

  196. }
    197. 

  197. 

  198. /*
    199. 

  199.  *
    200. 

  200.  */
    201. 

  201. 

  202. /**
    203. 

  203.  * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
    204. 

  204.  * @prcm_mod: PRCM module offset
    205. 

  205.  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
    206. 

  206.  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
    207. 

  207.  *
    208. 

  208.  * XXX document
    209. 

  209.  */
    210. 

  210. int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
    211. 

  211. {
    212. 

  212. 	int ena = 0, i = 0;
    213. 

  213. 	u8 cm_idlest_reg;
    214. 

  214. 	u32 mask;
    215. 

  215. 

  216. 	if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
    217. 

  217. 		return -EINVAL;
    218. 

  218. 

  219. 	cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
    220. 

  220. 

  221. 	mask = 1 << idlest_shift;
    222. 

  222. 

  223. 	if (cpu_is_omap24xx())
    224. 

  224. 		ena = mask;
    225. 

  225. 	else if (cpu_is_omap34xx())
    226. 

  226. 		ena = 0;
    227. 

  227. 	else
    228. 

  228. 		BUG();
    229. 

  229. 

  230. 	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
    231. 

  231. 			  MAX_MODULE_READY_TIME, i);
    232. 

  232. 

  233. 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
    234. 

  234. }
    235. 

  235. 

  236. /*
    237. 

  237.  * Context save/restore code - OMAP3 only
    238. 

  238.  */
    239. 

  239. #ifdef CONFIG_ARCH_OMAP3
    240. 

  240. struct omap3_cm_regs {
    241. 

  241. 	u32 iva2_cm_clksel1;
    242. 

  242. 	u32 iva2_cm_clksel2;
    243. 

  243. 	u32 cm_sysconfig;
    244. 

  244. 	u32 sgx_cm_clksel;
    245. 

  245. 	u32 dss_cm_clksel;
    246. 

  246. 	u32 cam_cm_clksel;
    247. 

  247. 	u32 per_cm_clksel;
    248. 

  248. 	u32 emu_cm_clksel;
    249. 

  249. 	u32 emu_cm_clkstctrl;
    250. 

  250. 	u32 pll_cm_autoidle;
    251. 

  251. 	u32 pll_cm_autoidle2;
    252. 

  252. 	u32 pll_cm_clksel4;
    253. 

  253. 	u32 pll_cm_clksel5;
    254. 

  254. 	u32 pll_cm_clken2;
    255. 

  255. 	u32 cm_polctrl;
    256. 

  256. 	u32 iva2_cm_fclken;
    257. 

  257. 	u32 iva2_cm_clken_pll;
    258. 

  258. 	u32 core_cm_fclken1;
    259. 

  259. 	u32 core_cm_fclken3;
    260. 

  260. 	u32 sgx_cm_fclken;
    261. 

  261. 	u32 wkup_cm_fclken;
    262. 

  262. 	u32 dss_cm_fclken;
    263. 

  263. 	u32 cam_cm_fclken;
    264. 

  264. 	u32 per_cm_fclken;
    265. 

  265. 	u32 usbhost_cm_fclken;
    266. 

  266. 	u32 core_cm_iclken1;
    267. 

  267. 	u32 core_cm_iclken2;
    268. 

  268. 	u32 core_cm_iclken3;
    269. 

  269. 	u32 sgx_cm_iclken;
    270. 

  270. 	u32 wkup_cm_iclken;
    271. 

  271. 	u32 dss_cm_iclken;
    272. 

  272. 	u32 cam_cm_iclken;
    273. 

  273. 	u32 per_cm_iclken;
    274. 

  274. 	u32 usbhost_cm_iclken;
    275. 

  275. 	u32 iva2_cm_autoidle2;
    276. 

  276. 	u32 mpu_cm_autoidle2;
    277. 

  277. 	u32 iva2_cm_clkstctrl;
    278. 

  278. 	u32 mpu_cm_clkstctrl;
    279. 

  279. 	u32 core_cm_clkstctrl;
    280. 

  280. 	u32 sgx_cm_clkstctrl;
    281. 

  281. 	u32 dss_cm_clkstctrl;
    282. 

  282. 	u32 cam_cm_clkstctrl;
    283. 

  283. 	u32 per_cm_clkstctrl;
    284. 

  284. 	u32 neon_cm_clkstctrl;
    285. 

  285. 	u32 usbhost_cm_clkstctrl;
    286. 

  286. 	u32 core_cm_autoidle1;
    287. 

  287. 	u32 core_cm_autoidle2;
    288. 

  288. 	u32 core_cm_autoidle3;
    289. 

  289. 	u32 wkup_cm_autoidle;
    290. 

  290. 	u32 dss_cm_autoidle;
    291. 

  291. 	u32 cam_cm_autoidle;
    292. 

  292. 	u32 per_cm_autoidle;
    293. 

  293. 	u32 usbhost_cm_autoidle;
    294. 

  294. 	u32 sgx_cm_sleepdep;
    295. 

  295. 	u32 dss_cm_sleepdep;
    296. 

  296. 	u32 cam_cm_sleepdep;
    297. 

  297. 	u32 per_cm_sleepdep;
    298. 

  298. 	u32 usbhost_cm_sleepdep;
    299. 

  299. 	u32 cm_clkout_ctrl;
    300. 

  300. };
    301. 

  301. 

  302. static struct omap3_cm_regs cm_context;
    303. 

  303. 

  304. void omap3_cm_save_context(void)
    305. 

  305. {
    306. 

  306. 	cm_context.iva2_cm_clksel1 =
    307. 

  307. 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
    308. 

  308. 	cm_context.iva2_cm_clksel2 =
    309. 

  309. 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
    310. 

  310. 	cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
    311. 

  311. 	cm_context.sgx_cm_clksel =
    312. 

  312. 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
    313. 

  313. 	cm_context.dss_cm_clksel =
    314. 

  314. 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
    315. 

  315. 	cm_context.cam_cm_clksel =
    316. 

  316. 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
    317. 

  317. 	cm_context.per_cm_clksel =
    318. 

  318. 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
    319. 

  319. 	cm_context.emu_cm_clksel =
    320. 

  320. 		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
    321. 

  321. 	cm_context.emu_cm_clkstctrl =
    322. 

  322. 		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
    323. 

  323. 	/*
    324. 

  324. 	 * As per erratum i671, ROM code does not respect the PER DPLL
    325. 

  325. 	 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
    326. 

  326. 	 * In this case, even though this register has been saved in
    327. 

  327. 	 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
    328. 

  328. 	 * by ourselves. So, we need to save it anyway.
    329. 

  329. 	 */
    330. 

  330. 	cm_context.pll_cm_autoidle =
    331. 

  331. 		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
    332. 

  332. 	cm_context.pll_cm_autoidle2 =
    333. 

  333. 		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
    334. 

  334. 	cm_context.pll_cm_clksel4 =
    335. 

  335. 		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
    336. 

  336. 	cm_context.pll_cm_clksel5 =
    337. 

  337. 		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
    338. 

  338. 	cm_context.pll_cm_clken2 =
    339. 

  339. 		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
    340. 

  340. 	cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
    341. 

  341. 	cm_context.iva2_cm_fclken =
    342. 

  342. 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
    343. 

  343. 	cm_context.iva2_cm_clken_pll =
    344. 

  344. 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
    345. 

  345. 	cm_context.core_cm_fclken1 =
    346. 

  346. 		omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
    347. 

  347. 	cm_context.core_cm_fclken3 =
    348. 

  348. 		omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
    349. 

  349. 	cm_context.sgx_cm_fclken =
    350. 

  350. 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
    351. 

  351. 	cm_context.wkup_cm_fclken =
    352. 

  352. 		omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
    353. 

  353. 	cm_context.dss_cm_fclken =
    354. 

  354. 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
    355. 

  355. 	cm_context.cam_cm_fclken =
    356. 

  356. 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
    357. 

  357. 	cm_context.per_cm_fclken =
    358. 

  358. 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
    359. 

  359. 	cm_context.usbhost_cm_fclken =
    360. 

  360. 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
    361. 

  361. 	cm_context.core_cm_iclken1 =
    362. 

  362. 		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
    363. 

  363. 	cm_context.core_cm_iclken2 =
    364. 

  364. 		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
    365. 

  365. 	cm_context.core_cm_iclken3 =
    366. 

  366. 		omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
    367. 

  367. 	cm_context.sgx_cm_iclken =
    368. 

  368. 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
    369. 

  369. 	cm_context.wkup_cm_iclken =
    370. 

  370. 		omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
    371. 

  371. 	cm_context.dss_cm_iclken =
    372. 

  372. 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
    373. 

  373. 	cm_context.cam_cm_iclken =
    374. 

  374. 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
    375. 

  375. 	cm_context.per_cm_iclken =
    376. 

  376. 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
    377. 

  377. 	cm_context.usbhost_cm_iclken =
    378. 

  378. 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
    379. 

  379. 	cm_context.iva2_cm_autoidle2 =
    380. 

  380. 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
    381. 

  381. 	cm_context.mpu_cm_autoidle2 =
    382. 

  382. 		omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
    383. 

  383. 	cm_context.iva2_cm_clkstctrl =
    384. 

  384. 		omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
    385. 

  385. 	cm_context.mpu_cm_clkstctrl =
    386. 

  386. 		omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
    387. 

  387. 	cm_context.core_cm_clkstctrl =
    388. 

  388. 		omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
    389. 

  389. 	cm_context.sgx_cm_clkstctrl =
    390. 

  390. 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
    391. 

  391. 	cm_context.dss_cm_clkstctrl =
    392. 

  392. 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
    393. 

  393. 	cm_context.cam_cm_clkstctrl =
    394. 

  394. 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
    395. 

  395. 	cm_context.per_cm_clkstctrl =
    396. 

  396. 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
    397. 

  397. 	cm_context.neon_cm_clkstctrl =
    398. 

  398. 		omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
    399. 

  399. 	cm_context.usbhost_cm_clkstctrl =
    400. 

  400. 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
    401. 

  401. 				      OMAP2_CM_CLKSTCTRL);
    402. 

  402. 	cm_context.core_cm_autoidle1 =
    403. 

  403. 		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
    404. 

  404. 	cm_context.core_cm_autoidle2 =
    405. 

  405. 		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
    406. 

  406. 	cm_context.core_cm_autoidle3 =
    407. 

  407. 		omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
    408. 

  408. 	cm_context.wkup_cm_autoidle =
    409. 

  409. 		omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
    410. 

  410. 	cm_context.dss_cm_autoidle =
    411. 

  411. 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
    412. 

  412. 	cm_context.cam_cm_autoidle =
    413. 

  413. 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
    414. 

  414. 	cm_context.per_cm_autoidle =
    415. 

  415. 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
    416. 

  416. 	cm_context.usbhost_cm_autoidle =
    417. 

  417. 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
    418. 

  418. 	cm_context.sgx_cm_sleepdep =
    419. 

  419. 		omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
    420. 

  420. 				      OMAP3430_CM_SLEEPDEP);
    421. 

  421. 	cm_context.dss_cm_sleepdep =
    422. 

  422. 		omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
    423. 

  423. 	cm_context.cam_cm_sleepdep =
    424. 

  424. 		omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
    425. 

  425. 	cm_context.per_cm_sleepdep =
    426. 

  426. 		omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
    427. 

  427. 	cm_context.usbhost_cm_sleepdep =
    428. 

  428. 		omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
    429. 

  429. 				      OMAP3430_CM_SLEEPDEP);
    430. 

  430. 	cm_context.cm_clkout_ctrl =
    431. 

  431. 		omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
    432. 

  432. 				      OMAP3_CM_CLKOUT_CTRL_OFFSET);
    433. 

  433. }
    434. 

  434. 

  435. void omap3_cm_restore_context(void)
    436. 

  436. {
    437. 

  437. 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
    438. 

  438. 			       CM_CLKSEL1);
    439. 

  439. 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
    440. 

  440. 			       CM_CLKSEL2);
    441. 

  441. 	__raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
    442. 

  442. 	omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
    443. 

  443. 			       CM_CLKSEL);
    444. 

  444. 	omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
    445. 

  445. 			       CM_CLKSEL);
    446. 

  446. 	omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
    447. 

  447. 			       CM_CLKSEL);
    448. 

  448. 	omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
    449. 

  449. 			       CM_CLKSEL);
    450. 

  450. 	omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
    451. 

  451. 			       CM_CLKSEL1);
    452. 

  452. 	omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
    453. 

  453. 			       OMAP2_CM_CLKSTCTRL);
    454. 

  454. 	/*
    455. 

  455. 	 * As per erratum i671, ROM code does not respect the PER DPLL
    456. 

  456. 	 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
    457. 

  457. 	 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
    458. 

  458. 	 */
    459. 

  459. 	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
    460. 

  460. 			       CM_AUTOIDLE);
    461. 

  461. 	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
    462. 

  462. 			       CM_AUTOIDLE2);
    463. 

  463. 	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
    464. 

  464. 			       OMAP3430ES2_CM_CLKSEL4);
    465. 

  465. 	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
    466. 

  466. 			       OMAP3430ES2_CM_CLKSEL5);
    467. 

  467. 	omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
    468. 

  468. 			       OMAP3430ES2_CM_CLKEN2);
    469. 

  469. 	__raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
    470. 

  470. 	omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
    471. 

  471. 			       CM_FCLKEN);
    472. 

  472. 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
    473. 

  473. 			       OMAP3430_CM_CLKEN_PLL);
    474. 

  474. 	omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
    475. 

  475. 			       CM_FCLKEN1);
    476. 

  476. 	omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
    477. 

  477. 			       OMAP3430ES2_CM_FCLKEN3);
    478. 

  478. 	omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
    479. 

  479. 			       CM_FCLKEN);
    480. 

  480. 	omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
    481. 

  481. 	omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
    482. 

  482. 			       CM_FCLKEN);
    483. 

  483. 	omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
    484. 

  484. 			       CM_FCLKEN);
    485. 

  485. 	omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
    486. 

  486. 			       CM_FCLKEN);
    487. 

  487. 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
    488. 

  488. 			       OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
    489. 

  489. 	omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
    490. 

  490. 			       CM_ICLKEN1);
    491. 

  491. 	omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
    492. 

  492. 			       CM_ICLKEN2);
    493. 

  493. 	omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
    494. 

  494. 			       CM_ICLKEN3);
    495. 

  495. 	omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
    496. 

  496. 			       CM_ICLKEN);
    497. 

  497. 	omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
    498. 

  498. 	omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
    499. 

  499. 			       CM_ICLKEN);
    500. 

  500. 	omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
    501. 

  501. 			       CM_ICLKEN);
    502. 

  502. 	omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
    503. 

  503. 			       CM_ICLKEN);
    504. 

  504. 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
    505. 

  505. 			       OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
    506. 

  506. 	omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
    507. 

  507. 			       CM_AUTOIDLE2);
    508. 

  508. 	omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
    509. 

  509. 			       CM_AUTOIDLE2);
    510. 

  510. 	omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
    511. 

  511. 			       OMAP2_CM_CLKSTCTRL);
    512. 

  512. 	omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
    513. 

  513. 			       OMAP2_CM_CLKSTCTRL);
    514. 

  514. 	omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
    515. 

  515. 			       OMAP2_CM_CLKSTCTRL);
    516. 

  516. 	omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
    517. 

  517. 			       OMAP2_CM_CLKSTCTRL);
    518. 

  518. 	omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
    519. 

  519. 			       OMAP2_CM_CLKSTCTRL);
    520. 

  520. 	omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
    521. 

  521. 			       OMAP2_CM_CLKSTCTRL);
    522. 

  522. 	omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
    523. 

  523. 			       OMAP2_CM_CLKSTCTRL);
    524. 

  524. 	omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
    525. 

  525. 			       OMAP2_CM_CLKSTCTRL);
    526. 

  526. 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
    527. 

  527. 			       OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
    528. 

  528. 	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
    529. 

  529. 			       CM_AUTOIDLE1);
    530. 

  530. 	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
    531. 

  531. 			       CM_AUTOIDLE2);
    532. 

  532. 	omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
    533. 

  533. 			       CM_AUTOIDLE3);
    534. 

  534. 	omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
    535. 

  535. 			       CM_AUTOIDLE);
    536. 

  536. 	omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
    537. 

  537. 			       CM_AUTOIDLE);
    538. 

  538. 	omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
    539. 

  539. 			       CM_AUTOIDLE);
    540. 

  540. 	omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
    541. 

  541. 			       CM_AUTOIDLE);
    542. 

  542. 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
    543. 

  543. 			       OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
    544. 

  544. 	omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
    545. 

  545. 			       OMAP3430_CM_SLEEPDEP);
    546. 

  546. 	omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
    547. 

  547. 			       OMAP3430_CM_SLEEPDEP);
    548. 

  548. 	omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
    549. 

  549. 			       OMAP3430_CM_SLEEPDEP);
    550. 

  550. 	omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
    551. 

  551. 			       OMAP3430_CM_SLEEPDEP);
    552. 

  552. 	omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
    553. 

  553. 			       OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
    554. 

  554. 	omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
    555. 

  555. 			       OMAP3_CM_CLKOUT_CTRL_OFFSET);
    556. 

  556. }
    557. 

  557. #endif
    558.