PageRenderTime 21ms CodeModel.GetById 11ms app.highlight 4ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/powerpc/boot/dts/pdm360ng.dts

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
Device Tree | 410 lines | 333 code | 51 blank | 26 comment | 0 complexity | 68d28aa536300b33b41e704099b5a60a MD5 | raw file
  1/*
  2 * Device Tree Source for IFM PDM360NG.
  3 *
  4 * Copyright 2009 - 2010 DENX Software Engineering.
  5 * Anatolij Gustschin <agust@denx.de>
  6 *
  7 * Based on MPC5121E ADS dts.
  8 * Copyright 2008 Freescale Semiconductor Inc.
  9 *
 10 * This program is free software; you can redistribute it and/or modify it
 11 * under the terms of the GNU General Public License as published by the
 12 * Free Software Foundation; either version 2 of the License, or (at your
 13 * option) any later version.
 14 */
 15
 16/dts-v1/;
 17
 18/ {
 19	model = "pdm360ng";
 20	compatible = "ifm,pdm360ng";
 21	#address-cells = <1>;
 22	#size-cells = <1>;
 23	interrupt-parent = <&ipic>;
 24
 25	aliases {
 26		ethernet0 = &eth0;
 27	};
 28
 29	cpus {
 30		#address-cells = <1>;
 31		#size-cells = <0>;
 32
 33		PowerPC,5121@0 {
 34			device_type = "cpu";
 35			reg = <0>;
 36			d-cache-line-size = <0x20>;	// 32 bytes
 37			i-cache-line-size = <0x20>;	// 32 bytes
 38			d-cache-size = <0x8000>;	// L1, 32K
 39			i-cache-size = <0x8000>;	// L1, 32K
 40			timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
 41			bus-frequency = <198000000>;	// 198 MHz csb bus
 42			clock-frequency = <396000000>;	// 396 MHz ppc core
 43		};
 44	};
 45
 46	memory {
 47		device_type = "memory";
 48		reg = <0x00000000 0x20000000>;	// 512MB at 0
 49	};
 50
 51	nfc@40000000 {
 52		compatible = "fsl,mpc5121-nfc";
 53		reg = <0x40000000 0x100000>;
 54		interrupts = <0x6 0x8>;
 55		#address-cells = <0x1>;
 56		#size-cells = <0x1>;
 57		bank-width = <0x1>;
 58		chips = <0x1>;
 59
 60		partition@0 {
 61			label = "nand0";
 62			reg = <0x0 0x40000000>;
 63		};
 64	};
 65
 66	sram@50000000 {
 67		compatible = "fsl,mpc5121-sram";
 68		reg = <0x50000000 0x20000>;	// 128K at 0x50000000
 69	};
 70
 71	localbus@80000020 {
 72		compatible = "fsl,mpc5121-localbus";
 73		#address-cells = <2>;
 74		#size-cells = <1>;
 75		reg = <0x80000020 0x40>;
 76
 77		ranges = <0x0 0x0 0xf0000000 0x10000000   /* Flash */
 78			  0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
 79
 80		flash@0,0 {
 81			compatible = "amd,s29gl01gp", "cfi-flash";
 82			reg = <0 0x00000000 0x08000000
 83			       0 0x08000000 0x08000000>;
 84			#address-cells = <1>;
 85			#size-cells = <1>;
 86			bank-width = <4>;
 87			device-width = <2>;
 88
 89			partition@0 {
 90				label = "u-boot";
 91				reg = <0x00000000 0x00080000>;
 92				read-only;
 93			};
 94			partition@80000 {
 95				label = "environment";
 96				reg = <0x00080000 0x00080000>;
 97				read-only;
 98			};
 99			partition@100000 {
100				label = "splash-image";
101				reg = <0x00100000 0x00080000>;
102				read-only;
103			};
104			partition@180000 {
105				label = "device-tree";
106				reg = <0x00180000 0x00040000>;
107			};
108			partition@1c0000 {
109				label = "kernel";
110				reg = <0x001c0000 0x00500000>;
111			};
112			partition@6c0000 {
113				label = "filesystem";
114				reg = <0x006c0000 0x07940000>;
115			};
116		};
117
118		mram0@2,0 {
119			compatible = "mtd-ram";
120			reg = <2 0x00000 0x10000>;
121			bank-width = <2>;
122		};
123
124		mram1@2,10000 {
125			compatible = "mtd-ram";
126			reg = <2 0x010000 0x10000>;
127			bank-width = <2>;
128		};
129	};
130
131	soc@80000000 {
132		compatible = "fsl,mpc5121-immr";
133		#address-cells = <1>;
134		#size-cells = <1>;
135		#interrupt-cells = <2>;
136		ranges = <0x0 0x80000000 0x400000>;
137		reg = <0x80000000 0x400000>;
138		bus-frequency = <66000000>;	// 66 MHz ips bus
139
140		// IPIC
141		// interrupts cell = <intr #, sense>
142		// sense values match linux IORESOURCE_IRQ_* defines:
143		// sense == 8: Level, low assertion
144		// sense == 2: Edge, high-to-low change
145		//
146		ipic: interrupt-controller@c00 {
147			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
148			interrupt-controller;
149			#address-cells = <0>;
150			#interrupt-cells = <2>;
151			reg = <0xc00 0x100>;
152		};
153
154		rtc@a00 {	// Real time clock
155			compatible = "fsl,mpc5121-rtc";
156			reg = <0xa00 0x100>;
157			interrupts = <79 0x8 80 0x8>;
158		};
159
160		reset@e00 {	// Reset module
161			compatible = "fsl,mpc5121-reset";
162			reg = <0xe00 0x100>;
163		};
164
165		clock@f00 {	// Clock control
166			compatible = "fsl,mpc5121-clock";
167			reg = <0xf00 0x100>;
168		};
169
170		pmc@1000{	//Power Management Controller
171			compatible = "fsl,mpc5121-pmc";
172			reg = <0x1000 0x100>;
173			interrupts = <83 0x2>;
174		};
175
176		gpio@1100 {
177			compatible = "fsl,mpc5121-gpio";
178			reg = <0x1100 0x100>;
179			interrupts = <78 0x8>;
180		};
181
182		can@1300 {
183			compatible = "fsl,mpc5121-mscan";
184			interrupts = <12 0x8>;
185			reg = <0x1300 0x80>;
186		};
187
188		can@1380 {
189			compatible = "fsl,mpc5121-mscan";
190			interrupts = <13 0x8>;
191			reg = <0x1380 0x80>;
192		};
193
194		i2c@1700 {
195			#address-cells = <1>;
196			#size-cells = <0>;
197			compatible = "fsl,mpc5121-i2c";
198			reg = <0x1700 0x20>;
199			interrupts = <0x9 0x8>;
200			fsl,preserve-clocking;
201
202			eeprom@50 {
203				compatible = "at,24c01";
204				reg = <0x50>;
205			};
206
207			rtc@68 {
208				compatible = "stm,m41t00";
209				reg = <0x68>;
210			};
211		};
212
213		i2c@1740 {
214			#address-cells = <1>;
215			#size-cells = <0>;
216			compatible = "fsl,mpc5121-i2c";
217			reg = <0x1740 0x20>;
218			interrupts = <0xb 0x8>;
219			fsl,preserve-clocking;
220		};
221
222		i2ccontrol@1760 {
223			compatible = "fsl,mpc5121-i2c-ctrl";
224			reg = <0x1760 0x8>;
225		};
226
227		axe@2000 {
228			compatible = "fsl,mpc5121-axe";
229			reg = <0x2000 0x100>;
230			interrupts = <42 0x8>;
231		};
232
233		display@2100 {
234			compatible = "fsl,mpc5121-diu";
235			reg = <0x2100 0x100>;
236			interrupts = <64 0x8>;
237		};
238
239		can@2300 {
240			compatible = "fsl,mpc5121-mscan";
241			interrupts = <90 0x8>;
242			reg = <0x2300 0x80>;
243		};
244
245		can@2380 {
246			compatible = "fsl,mpc5121-mscan";
247			interrupts = <91 0x8>;
248			reg = <0x2380 0x80>;
249		};
250
251		viu@2400 {
252			compatible = "fsl,mpc5121-viu";
253			reg = <0x2400 0x400>;
254			interrupts = <67 0x8>;
255		};
256
257		mdio@2800 {
258			compatible = "fsl,mpc5121-fec-mdio";
259			reg = <0x2800 0x200>;
260			#address-cells = <1>;
261			#size-cells = <0>;
262			phy: ethernet-phy@0 {
263				compatible = "smsc,lan8700";
264				reg = <0x1f>;
265			};
266		};
267
268		eth0: ethernet@2800 {
269			compatible = "fsl,mpc5121-fec";
270			reg = <0x2800 0x200>;
271			local-mac-address = [ 00 00 00 00 00 00 ];
272			interrupts = <4 0x8>;
273			phy-handle = < &phy >;
274		};
275
276		// USB1 using external ULPI PHY
277		usb@3000 {
278			compatible = "fsl,mpc5121-usb2-dr";
279			reg = <0x3000 0x600>;
280			#address-cells = <1>;
281			#size-cells = <0>;
282			interrupts = <43 0x8>;
283			dr_mode = "host";
284			phy_type = "ulpi";
285		};
286
287		// USB0 using internal UTMI PHY
288		usb@4000 {
289			compatible = "fsl,mpc5121-usb2-dr";
290			reg = <0x4000 0x600>;
291			#address-cells = <1>;
292			#size-cells = <0>;
293			interrupts = <44 0x8>;
294			dr_mode = "otg";
295			phy_type = "utmi_wide";
296			fsl,invert-pwr-fault;
297		};
298
299		// IO control
300		ioctl@a000 {
301			compatible = "fsl,mpc5121-ioctl";
302			reg = <0xA000 0x1000>;
303		};
304
305		// 512x PSCs are not 52xx PSCs compatible
306		serial@11000 {
307			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
308			cell-index = <0>;
309			reg = <0x11000 0x100>;
310			interrupts = <40 0x8>;
311			fsl,rx-fifo-size = <16>;
312			fsl,tx-fifo-size = <16>;
313		};
314
315		serial@11100 {
316			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
317			cell-index = <1>;
318			reg = <0x11100 0x100>;
319			interrupts = <40 0x8>;
320			fsl,rx-fifo-size = <16>;
321			fsl,tx-fifo-size = <16>;
322		};
323
324		serial@11200 {
325			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
326			cell-index = <2>;
327			reg = <0x11200 0x100>;
328			interrupts = <40 0x8>;
329			fsl,rx-fifo-size = <16>;
330			fsl,tx-fifo-size = <16>;
331		};
332
333		serial@11300 {
334			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
335			cell-index = <3>;
336			reg = <0x11300 0x100>;
337			interrupts = <40 0x8>;
338			fsl,rx-fifo-size = <16>;
339			fsl,tx-fifo-size = <16>;
340		};
341
342		serial@11400 {
343			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
344			cell-index = <4>;
345			reg = <0x11400 0x100>;
346			interrupts = <40 0x8>;
347			fsl,rx-fifo-size = <16>;
348			fsl,tx-fifo-size = <16>;
349		};
350
351		serial@11600 {
352			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
353			cell-index = <6>;
354			reg = <0x11600 0x100>;
355			interrupts = <40 0x8>;
356			fsl,rx-fifo-size = <16>;
357			fsl,tx-fifo-size = <16>;
358		};
359
360		serial@11800 {
361			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
362			cell-index = <8>;
363			reg = <0x11800 0x100>;
364			interrupts = <40 0x8>;
365			fsl,rx-fifo-size = <16>;
366			fsl,tx-fifo-size = <16>;
367		};
368
369		serial@11B00 {
370			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
371			cell-index = <11>;
372			reg = <0x11B00 0x100>;
373			interrupts = <40 0x8>;
374			fsl,rx-fifo-size = <16>;
375			fsl,tx-fifo-size = <16>;
376		};
377
378		pscfifo@11f00 {
379			compatible = "fsl,mpc5121-psc-fifo";
380			reg = <0x11f00 0x100>;
381			interrupts = <40 0x8>;
382		};
383
384		spi@11900 {
385			compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
386			cell-index = <9>;
387			#address-cells = <1>;
388			#size-cells = <0>;
389			reg = <0x11900 0x100>;
390			interrupts = <40 0x8>;
391			fsl,rx-fifo-size = <16>;
392			fsl,tx-fifo-size = <16>;
393
394			// 7845 touch screen controller
395			ts@0 {
396				compatible = "ti,ads7846";
397				reg = <0x0>;
398				spi-max-frequency = <3000000>;
399				// pen irq is GPIO25
400				interrupts = <78 0x8>;
401			};
402		};
403
404		dma@14000 {
405			compatible = "fsl,mpc5121-dma";
406			reg = <0x14000 0x1800>;
407			interrupts = <65 0x8>;
408		};
409	};
410};