PageRenderTime 16ms CodeModel.GetById 10ms app.highlight 2ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/powerpc/boot/dts/ps3.dts

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
Device Tree | 70 lines | 28 code | 8 blank | 34 comment | 0 complexity | 3bfc6c6c2be7c8197965d3057d5507b9 MD5 | raw file
 1/*
 2 *  PS3 Game Console device tree.
 3 *
 4 *  Copyright (C) 2007 Sony Computer Entertainment Inc.
 5 *  Copyright 2007 Sony Corp.
 6 *
 7 *  This program is free software; you can redistribute it and/or modify
 8 *  it under the terms of the GNU General Public License as published by
 9 *  the Free Software Foundation; version 2 of the License.
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *  GNU General Public License for more details.
15 *
16 *  You should have received a copy of the GNU General Public License
17 *  along with this program; if not, write to the Free Software
18 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19 */
20
21/dts-v1/;
22
23/ {
24	model = "SonyPS3";
25	compatible = "sony,ps3";
26	#size-cells = <2>;
27	#address-cells = <2>;
28
29	chosen {
30	};
31
32	/*
33	 * We'll get the size of the bootmem block from lv1 after startup,
34	 * so we'll put a null entry here.
35	 */
36
37	memory {
38		device_type = "memory";
39		reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
40	};
41
42	/*
43	 * The boot cpu is always zero for PS3.
44	 *
45	 * dtc expects a clock-frequency and timebase-frequency entries, so
46	 * we'll put a null entries here.  These will be initialized after
47	 * startup with data from lv1.
48	 *
49	 * Seems the only way currently to indicate a processor has multiple
50	 * threads is with an ibm,ppc-interrupt-server#s entry.  We'll put one
51	 * here so we can bring up both of ours.  See smp_setup_cpu_maps().
52	 */
53
54	cpus {
55		#size-cells = <0>;
56		#address-cells = <1>;
57
58		cpu@0 {
59			device_type = "cpu";
60			reg = <0x00000000>;
61			ibm,ppc-interrupt-server#s = <0x0 0x1>;
62			clock-frequency = <0>;
63			timebase-frequency = <0>;
64			i-cache-size = <32768>;
65			d-cache-size = <32768>;
66			i-cache-line-size = <128>;
67			d-cache-line-size = <128>;
68		};
69	};
70};