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/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h

https://github.com/AICP/kernel_google_msm
C Header | 57 lines | 30 code | 12 blank | 15 comment | 0 complexity | 89c599eeaccf2ec12db34a2e39549429 MD5 | raw file
 1/*
 2 * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
 3 *
 4 * Platform definitions for IXDP2X01 && IXDP2801 systems
 5 *
 6 * Author: Deepak Saxena <dsaxena@plexity.net>
 7 *
 8 * Copyright 2004 (c) MontaVista Software, Inc. 
 9 *
10 * Based on original code Copyright (c) 2002-2003 Intel Corporation
11 * 
12 * This file is licensed under  the terms of the GNU General Public 
13 * License version 2. This program is licensed "as is" without any 
14 * warranty of any kind, whether express or implied.
15 */
16
17#ifndef __IXDP2X01_H__
18#define __IXDP2X01_H__
19
20#define	IXDP2X01_PHYS_CPLD_BASE		0xc6024000
21#define	IXDP2X01_VIRT_CPLD_BASE		0xfe000000
22#define	IXDP2X01_CPLD_REGION_SIZE	0x00100000
23
24#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
25#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
26
27#define IXDP2X01_UART1_VIRT_BASE	IXDP2X01_CPLD_VIRT_REG(0x40)
28#define IXDP2X01_UART1_PHYS_BASE	IXDP2X01_CPLD_PHYS_REG(0x40)
29
30#define IXDP2X01_UART2_VIRT_BASE	IXDP2X01_CPLD_VIRT_REG(0x60)
31#define IXDP2X01_UART2_PHYS_BASE	IXDP2X01_CPLD_PHYS_REG(0x60)
32
33#define IXDP2X01_CS8900_VIRT_BASE	IXDP2X01_CPLD_VIRT_REG(0x80)
34#define IXDP2X01_CS8900_VIRT_END	(IXDP2X01_CS8900_VIRT_BASE + 16)
35
36#define IXDP2X01_CPLD_RESET_REG         IXDP2X01_CPLD_VIRT_REG(0x00)
37#define IXDP2X01_INT_MASK_SET_REG	IXDP2X01_CPLD_VIRT_REG(0x08)
38#define IXDP2X01_INT_STAT_REG		IXDP2X01_CPLD_VIRT_REG(0x0C)
39#define IXDP2X01_INT_RAW_REG		IXDP2X01_CPLD_VIRT_REG(0x10) 
40#define IXDP2X01_INT_MASK_CLR_REG	IXDP2X01_INT_RAW_REG
41#define IXDP2X01_INT_SIM_REG		IXDP2X01_CPLD_VIRT_REG(0x14)
42
43#define IXDP2X01_CPLD_FLASH_REG		IXDP2X01_CPLD_VIRT_REG(0x20)
44
45#define IXDP2X01_CPLD_FLASH_INTERN 	0x8000
46#define IXDP2X01_CPLD_FLASH_BANK_MASK 	0xF
47#define IXDP2X01_FLASH_WINDOW_BITS 	25
48#define IXDP2X01_FLASH_WINDOW_SIZE 	(1 << IXDP2X01_FLASH_WINDOW_BITS)
49#define IXDP2X01_FLASH_WINDOW_MASK 	(IXDP2X01_FLASH_WINDOW_SIZE - 1)
50
51#define	IXDP2X01_UART_CLK		1843200
52
53#define	IXDP2X01_GPIO_I2C_ENABLE	0x02
54#define	IXDP2X01_GPIO_SCL		0x07
55#define	IXDP2X01_GPIO_SDA		0x06
56
57#endif /* __IXDP2x01_H__ */