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/arch/powerpc/boot/dts/sbc8548.dts

https://github.com/aicjofs/android_kernel_lge_v500_20d
Device Tree | 428 lines | 369 code | 44 blank | 15 comment | 0 complexity | 4e70061be00fc4a3ed02bf2d2c9409bb MD5 | raw file
  1/*
  2 * SBC8548 Device Tree Source
  3 *
  4 * Copyright 2007 Wind River Systems Inc.
  5 *
  6 * Paul Gortmaker (see MAINTAINERS for contact information)
  7 *
  8 * This program is free software; you can redistribute  it and/or modify it
  9 * under  the terms of  the GNU General  Public License as published by the
 10 * Free Software Foundation;  either version 2 of the  License, or (at your
 11 * option) any later version.
 12 */
 13
 14
 15/dts-v1/;
 16
 17/ {
 18	model = "SBC8548";
 19	compatible = "SBC8548";
 20	#address-cells = <1>;
 21	#size-cells = <1>;
 22
 23	aliases {
 24		ethernet0 = &enet0;
 25		ethernet1 = &enet1;
 26		serial0 = &serial0;
 27		serial1 = &serial1;
 28		pci0 = &pci0;
 29		pci1 = &pci1;
 30	};
 31
 32	cpus {
 33		#address-cells = <1>;
 34		#size-cells = <0>;
 35
 36		PowerPC,8548@0 {
 37			device_type = "cpu";
 38			reg = <0>;
 39			d-cache-line-size = <0x20>;	// 32 bytes
 40			i-cache-line-size = <0x20>;	// 32 bytes
 41			d-cache-size = <0x8000>;	// L1, 32K
 42			i-cache-size = <0x8000>;	// L1, 32K
 43			timebase-frequency = <0>;	// From uboot
 44			bus-frequency = <0>;
 45			clock-frequency = <0>;
 46			next-level-cache = <&L2>;
 47		};
 48	};
 49
 50	memory {
 51		device_type = "memory";
 52		reg = <0x00000000 0x10000000>;
 53	};
 54
 55	localbus@e0000000 {
 56		#address-cells = <2>;
 57		#size-cells = <1>;
 58		compatible = "simple-bus";
 59		reg = <0xe0000000 0x5000>;
 60		interrupt-parent = <&mpic>;
 61
 62		ranges = <0x0 0x0 0xff800000 0x00800000		/*8MB Flash*/
 63			  0x3 0x0 0xf0000000 0x04000000		/*64MB SDRAM*/
 64			  0x4 0x0 0xf4000000 0x04000000 	/*64MB SDRAM*/
 65			  0x5 0x0 0xf8000000 0x00b10000		/* EPLD */
 66			  0x6 0x0 0xfb800000 0x04000000>;	/*64MB Flash*/
 67
 68
 69		flash@0,0 {
 70			#address-cells = <1>;
 71			#size-cells = <1>;
 72			compatible = "cfi-flash";
 73			reg = <0x0 0x0 0x800000>;
 74			bank-width = <1>;
 75			device-width = <1>;
 76			partition@0x0 {
 77				label = "space";
 78				reg = <0x00000000 0x00100000>;
 79			};
 80			partition@0x100000 {
 81				label = "bootloader";
 82				reg = <0x00100000 0x00700000>;
 83				read-only;
 84			};
 85		};
 86
 87		epld@5,0 {
 88			compatible = "wrs,epld-localbus";
 89			#address-cells = <2>;
 90			#size-cells = <1>;
 91			reg = <0x5 0x0 0x00b10000>;
 92			ranges = <
 93				0x0 0x0 0x5 0x000000 0x1fff	/* LED */
 94				0x1 0x0 0x5 0x100000 0x1fff	/* Switches */
 95				0x3 0x0 0x5 0x300000 0x1fff	/* HW Rev. */
 96				0xb 0x0	0x5 0xb00000 0x1fff	/* EEPROM */
 97			>;
 98
 99			led@0,0 {
100				compatible = "led";
101				reg = <0x0 0x0 0x1fff>;
102			};
103
104			switches@1,0 {
105				compatible = "switches";
106				reg = <0x1 0x0 0x1fff>;
107			};
108
109			hw-rev@3,0 {
110				compatible = "hw-rev";
111				reg = <0x3 0x0 0x1fff>;
112			};
113
114			eeprom@b,0 {
115				compatible = "eeprom";
116				reg = <0xb 0 0x1fff>;
117			};
118
119		};
120
121		alt-flash@6,0 {
122			#address-cells = <1>;
123			#size-cells = <1>;
124			reg = <0x6 0x0 0x04000000>;
125			compatible = "cfi-flash";
126			bank-width = <4>;
127			device-width = <1>;
128			partition@0x0 {
129				label = "bootloader";
130				reg = <0x00000000 0x00100000>;
131				read-only;
132			};
133			partition@0x00100000 {
134				label = "file-system";
135				reg = <0x00100000 0x01f00000>;
136			};
137			partition@0x02000000 {
138				label = "boot-config";
139				reg = <0x02000000 0x00100000>;
140			};
141			partition@0x02100000 {
142				label = "space";
143				reg = <0x02100000 0x01f00000>;
144			};
145                };
146        };
147
148	soc8548@e0000000 {
149		#address-cells = <1>;
150		#size-cells = <1>;
151		device_type = "soc";
152		ranges = <0x00000000 0xe0000000 0x00100000>;
153		bus-frequency = <0>;
154		compatible = "simple-bus";
155
156		ecm-law@0 {
157			compatible = "fsl,ecm-law";
158			reg = <0x0 0x1000>;
159			fsl,num-laws = <10>;
160		};
161
162		ecm@1000 {
163			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
164			reg = <0x1000 0x1000>;
165			interrupts = <17 2>;
166			interrupt-parent = <&mpic>;
167		};
168
169		memory-controller@2000 {
170			compatible = "fsl,mpc8548-memory-controller";
171			reg = <0x2000 0x1000>;
172			interrupt-parent = <&mpic>;
173			interrupts = <0x12 0x2>;
174		};
175
176		L2: l2-cache-controller@20000 {
177			compatible = "fsl,mpc8548-l2-cache-controller";
178			reg = <0x20000 0x1000>;
179			cache-line-size = <0x20>;	// 32 bytes
180			cache-size = <0x80000>;	// L2, 512K
181			interrupt-parent = <&mpic>;
182			interrupts = <0x10 0x2>;
183		};
184
185		i2c@3000 {
186			#address-cells = <1>;
187			#size-cells = <0>;
188			cell-index = <0>;
189			compatible = "fsl-i2c";
190			reg = <0x3000 0x100>;
191			interrupts = <0x2b 0x2>;
192			interrupt-parent = <&mpic>;
193			dfsrr;
194		};
195
196		i2c@3100 {
197			#address-cells = <1>;
198			#size-cells = <0>;
199			cell-index = <1>;
200			compatible = "fsl-i2c";
201			reg = <0x3100 0x100>;
202			interrupts = <0x2b 0x2>;
203			interrupt-parent = <&mpic>;
204			dfsrr;
205		};
206
207		dma@21300 {
208			#address-cells = <1>;
209			#size-cells = <1>;
210			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
211			reg = <0x21300 0x4>;
212			ranges = <0x0 0x21100 0x200>;
213			cell-index = <0>;
214			dma-channel@0 {
215				compatible = "fsl,mpc8548-dma-channel",
216						"fsl,eloplus-dma-channel";
217				reg = <0x0 0x80>;
218				cell-index = <0>;
219				interrupt-parent = <&mpic>;
220				interrupts = <20 2>;
221			};
222			dma-channel@80 {
223				compatible = "fsl,mpc8548-dma-channel",
224						"fsl,eloplus-dma-channel";
225				reg = <0x80 0x80>;
226				cell-index = <1>;
227				interrupt-parent = <&mpic>;
228				interrupts = <21 2>;
229			};
230			dma-channel@100 {
231				compatible = "fsl,mpc8548-dma-channel",
232						"fsl,eloplus-dma-channel";
233				reg = <0x100 0x80>;
234				cell-index = <2>;
235				interrupt-parent = <&mpic>;
236				interrupts = <22 2>;
237			};
238			dma-channel@180 {
239				compatible = "fsl,mpc8548-dma-channel",
240						"fsl,eloplus-dma-channel";
241				reg = <0x180 0x80>;
242				cell-index = <3>;
243				interrupt-parent = <&mpic>;
244				interrupts = <23 2>;
245			};
246		};
247
248		enet0: ethernet@24000 {
249			#address-cells = <1>;
250			#size-cells = <1>;
251			cell-index = <0>;
252			device_type = "network";
253			model = "eTSEC";
254			compatible = "gianfar";
255			reg = <0x24000 0x1000>;
256			ranges = <0x0 0x24000 0x1000>;
257			local-mac-address = [ 00 00 00 00 00 00 ];
258			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
259			interrupt-parent = <&mpic>;
260			tbi-handle = <&tbi0>;
261			phy-handle = <&phy0>;
262
263			mdio@520 {
264				#address-cells = <1>;
265				#size-cells = <0>;
266				compatible = "fsl,gianfar-mdio";
267				reg = <0x520 0x20>;
268
269				phy0: ethernet-phy@19 {
270					interrupt-parent = <&mpic>;
271					interrupts = <0x6 0x1>;
272					reg = <0x19>;
273					device_type = "ethernet-phy";
274				};
275				phy1: ethernet-phy@1a {
276					interrupt-parent = <&mpic>;
277					interrupts = <0x7 0x1>;
278					reg = <0x1a>;
279					device_type = "ethernet-phy";
280				};
281				tbi0: tbi-phy@11 {
282					reg = <0x11>;
283					device_type = "tbi-phy";
284				};
285			};
286		};
287
288		enet1: ethernet@25000 {
289			#address-cells = <1>;
290			#size-cells = <1>;
291			cell-index = <1>;
292			device_type = "network";
293			model = "eTSEC";
294			compatible = "gianfar";
295			reg = <0x25000 0x1000>;
296			ranges = <0x0 0x25000 0x1000>;
297			local-mac-address = [ 00 00 00 00 00 00 ];
298			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
299			interrupt-parent = <&mpic>;
300			tbi-handle = <&tbi1>;
301			phy-handle = <&phy1>;
302
303			mdio@520 {
304				#address-cells = <1>;
305				#size-cells = <0>;
306				compatible = "fsl,gianfar-tbi";
307				reg = <0x520 0x20>;
308
309				tbi1: tbi-phy@11 {
310					reg = <0x11>;
311					device_type = "tbi-phy";
312				};
313			};
314		};
315
316		serial0: serial@4500 {
317			cell-index = <0>;
318			device_type = "serial";
319			compatible = "fsl,ns16550", "ns16550";
320			reg = <0x4500 0x100>;	// reg base, size
321			clock-frequency = <0>;	// should we fill in in uboot?
322			interrupts = <0x2a 0x2>;
323			interrupt-parent = <&mpic>;
324		};
325
326		serial1: serial@4600 {
327			cell-index = <1>;
328			device_type = "serial";
329			compatible = "fsl,ns16550", "ns16550";
330			reg = <0x4600 0x100>;	// reg base, size
331			clock-frequency = <0>;	// should we fill in in uboot?
332			interrupts = <0x2a 0x2>;
333			interrupt-parent = <&mpic>;
334		};
335
336		global-utilities@e0000 {	//global utilities reg
337			compatible = "fsl,mpc8548-guts";
338			reg = <0xe0000 0x1000>;
339			fsl,has-rstcr;
340		};
341
342		crypto@30000 {
343			compatible = "fsl,sec2.1", "fsl,sec2.0";
344			reg = <0x30000 0x10000>;
345			interrupts = <45 2>;
346			interrupt-parent = <&mpic>;
347			fsl,num-channels = <4>;
348			fsl,channel-fifo-len = <24>;
349			fsl,exec-units-mask = <0xfe>;
350			fsl,descriptor-types-mask = <0x12b0ebf>;
351		};
352
353		mpic: pic@40000 {
354			interrupt-controller;
355			#address-cells = <0>;
356			#interrupt-cells = <2>;
357			reg = <0x40000 0x40000>;
358			compatible = "chrp,open-pic";
359			device_type = "open-pic";
360		};
361	};
362
363	pci0: pci@e0008000 {
364		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
365		interrupt-map = <
366			/* IDSEL 0x01 (PCI-X slot) @66MHz */
367			0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
368			0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
369			0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
370			0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
371
372			/* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
373			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
374			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
375			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
376			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
377
378		interrupt-parent = <&mpic>;
379		interrupts = <0x18 0x2>;
380		bus-range = <0 0>;
381		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
382			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
383		clock-frequency = <66000000>;
384		#interrupt-cells = <1>;
385		#size-cells = <2>;
386		#address-cells = <3>;
387		reg = <0xe0008000 0x1000>;
388		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
389		device_type = "pci";
390	};
391
392	pci1: pcie@e000a000 {
393		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
394		interrupt-map = <
395
396			/* IDSEL 0x0 (PEX) */
397			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
398			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
399			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
400			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
401
402		interrupt-parent = <&mpic>;
403		interrupts = <0x1a 0x2>;
404		bus-range = <0x0 0xff>;
405		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
406			  0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
407		clock-frequency = <33000000>;
408		#interrupt-cells = <1>;
409		#size-cells = <2>;
410		#address-cells = <3>;
411		reg = <0xe000a000 0x1000>;
412		compatible = "fsl,mpc8548-pcie";
413		device_type = "pci";
414		pcie@0 {
415			reg = <0x0 0x0 0x0 0x0 0x0>;
416			#size-cells = <2>;
417			#address-cells = <3>;
418			device_type = "pci";
419			ranges = <0x02000000 0x0 0xa0000000
420				  0x02000000 0x0 0xa0000000
421				  0x0 0x10000000
422
423				  0x01000000 0x0 0x00000000
424				  0x01000000 0x0 0x00000000
425				  0x0 0x00800000>;
426		};
427	};
428};